JPS5961186A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5961186A JPS5961186A JP17202682A JP17202682A JPS5961186A JP S5961186 A JPS5961186 A JP S5961186A JP 17202682 A JP17202682 A JP 17202682A JP 17202682 A JP17202682 A JP 17202682A JP S5961186 A JPS5961186 A JP S5961186A
- Authority
- JP
- Japan
- Prior art keywords
- film
- conductive film
- mask
- semiconductor substrate
- window
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 29
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 11
- 239000012535 impurity Substances 0.000 claims abstract description 7
- 238000010438 heat treatment Methods 0.000 claims abstract description 3
- 239000011800 void material Substances 0.000 claims description 5
- 238000000034 method Methods 0.000 abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 12
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052782 aluminium Inorganic materials 0.000 abstract description 8
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 6
- 239000000377 silicon dioxide Substances 0.000 abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 238000000206 photolithography Methods 0.000 abstract description 4
- 238000004544 sputter deposition Methods 0.000 abstract description 4
- 230000003071 parasitic effect Effects 0.000 abstract description 3
- 230000003647 oxidation Effects 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- 238000001704 evaporation Methods 0.000 abstract 2
- 230000005669 field effect Effects 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 239000012808 vapor phase Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000002893 slag Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
発明の技術分野
本発明は、電界効果トランジスタを小型化する際に適用
して有効な半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a method of manufacturing a semiconductor device that is effective when applied to miniaturize field effect transistors.
従来技術と問題点
従来、ＭＩＳ電界効果トランジスリスいはショア）キ・
ゲート型電界効果トランジスタ等を高速動作させたり高
集積化する為、それ等の微小化が図られてきた。Conventional technology and problems Conventionally, MIS field effect transistors (Shore) Ki.
BACKGROUND ART In order to operate gate-type field effect transistors at high speed and increase their integration, efforts have been made to miniaturize gate-type field effect transistors and the like.
てあった。そして、それに加えて各パターンをセルフ・
アラインメント方式で形成することで、より一層の微小
化を図る努力がなされてきた。There was. In addition, each pattern can be self-created.
Efforts have been made to achieve further miniaturization by forming by alignment method.
然し乍ら、従来、採用されてきたセルフ・アラインメン
ト方式には一長一短があり、電界効果半導体装置の製造
に於いては、ＭＩＳ構造のゲート電極とソース及びトレ
イン各領域とをセルフ・アラインメン１−させること以
外には実用化されていない現状である。However, the conventionally employed self-alignment methods have advantages and disadvantages, and in manufacturing field effect semiconductor devices, there are no methods other than self-alignment between the gate electrode and the source and train regions of the MIS structure. Currently, it has not been put into practical use.
発明の目的
本発明は、電界効果半導体装置の殆との部分を１！ルフ
・アラ・インメント的に製造できるようにすることで微
小化を可能とし、それに依り寄生容量及びノリース１１
（抗が低減され、且つ、超高速、低消費電力である電界
９．果半導体装置を提供し。辞テ′４るものである。OBJECTS OF THE INVENTION The present invention provides a method for converting most parts of a field effect semiconductor device into 1! Miniaturization is possible by making it possible to manufacture it in a similar manner, thereby reducing parasitic capacitance and Norris 11
(It is an object of the present invention to provide an electric field semiconductor device with reduced resistance, ultra-high speed, and low power consumption.)
発明の構成
本発明こは、半導体基板」―に絶縁１模と不純物がｉｎ
ｉ 濃度にドープされた帯状の第１の導７ｍ股と活性領
域形成予定部分に窓を有する第１の一７スクｌ均とを順
に形成し、次に、第１の導電膜を選択的に除去して前記
窓と同パターンの開１」を形成してからサイド・エツチ
ングを行ない第１のマスク膜の下に空所を形成し、次に
、第２のマスク膜を形成してから第１のマスク膜を除去
することに依りその上のｆｆ１２のマスク膜をリフト・
オフし、次に、残留した第２のマスク膜と第１の導電膜
との間の前記絶縁膜を除去して半導体基板の一部表面を
露出し、次に、第２のマスク膜を除去しｔから酸化可能
な材料からなる第２の導電膜を形成して第１の導電膜と
半導体基板との電気接続を行ない、次に、熱処理を行な
って第１の導電膜から半導体基板に不純物を拡散しソー
ス領域及びトレイン領域を形成するようにしている。Structure of the Invention The present invention is directed to a semiconductor substrate in which an insulator and impurities are injected into a semiconductor substrate.
A first conductive film doped with a concentration of 7 m and a first conductive film having a window in the area where the active region is to be formed are sequentially formed, and then the first conductive film is selectively formed. After forming an opening 1 in the same pattern as the window, side etching is performed to form a void under the first mask film, and then a second mask film is formed, and then a second mask film is formed. By removing the mask film of ff1, the mask film of ff12 above it is lifted.
Then, the remaining insulating film between the second mask film and the first conductive film is removed to expose a part of the surface of the semiconductor substrate, and then the second mask film is removed. A second conductive film made of an oxidizable material is formed from the first conductive film to establish an electrical connection between the first conductive film and the semiconductor substrate, and then heat treatment is performed to remove impurities from the first conductive film to the semiconductor substrate. is diffused to form a source region and a train region.
発明の実施例
第１図乃至第８図は本発明−実施例を解説する為の工程
要所に於＋）る半導体装置の要部９ノ断側面図であり、
以下、これ等の図を参照しつつ説明する。Embodiments of the Invention FIGS. 1 to 8 are cross-sectional side views of main parts 9 of a semiconductor device at important process points for explaining embodiments of the present invention.
The explanation will be given below with reference to these figures.
第１図参照
■ 面指数（１００）の主面を持つｐ型シリコン半導体
括板ｌに化学気相１ｔＣ積法を適用し、厚さ例えば１０
００（人〕の窒化シリコン絶Ｉｒ５．膜２を形成する。Refer to Fig. 1 ■ Chemical vapor phase 1tC product method is applied to a p-type silicon semiconductor board l having a main surface with a surface index of (100), and the thickness is, for example, 10.
A silicon nitride-free Ir5.00 film 2 is formed.
尚、これは、厚さ例えば５００〔入〕の二酸化シリコン
絶縁膜と厚さ例えば１０００ （人〕の窒化シリコン絶
縁膜からなる多層絶縁膜であっても良い。Incidentally, this may be a multilayer insulating film consisting of a silicon dioxide insulating film having a thickness of, for example, 500 μm and a silicon nitride insulating film having a thickness of, for example, 1000 μm.
■ 化学気相１（Ｆ積法を適用し、砒素を高濃度にトー
プした厚さ例えば４０００ （人〕の多結晶シリコン
１１染（第１の導電膜）３を形成する。(2) Applying a chemical vapor phase 1 (F product method), a polycrystalline silicon 11 dye (first conductive film) 3 doped with arsenic at a high concentration and having a thickness of, for example, 4,000 mm is formed.
■ フォト・リソグラフィ技術に′ζ、多結晶ソリコン
膜３を所定間隔を維持した多数の・１１）状にパターニ
ングする。(2) Using photolithography technology, the polycrystalline silicon film 3 is patterned into a large number of 11) shapes with predetermined spacing maintained.
■ フォト・リソグラフィ技術にて、窓５を有するフォ
ト・レシスｌ−１ｉ（第１のマスク膜）４を形成する。(2) A photoresis l-1i (first mask film) 4 having a window 5 is formed using photolithography technology.
第２図参照
■ フォト・レジスト膜４をマスクとして、リアクティ
ブ・スパッタ・エツチング法等の手段を適用し、多結晶
シリコン膜３を工・ノチングし−Ｃ前記窓５と類似形状
の開口を形成する。Refer to Fig. 2■ Using the photoresist film 4 as a mask, the polycrystalline silicon film 3 is etched and notched by applying a method such as a reactive sputter etching method to form an opening having a similar shape to the window 5. do.
（■ ツメ］・・レジスト膜４をマスクとして多結晶シ
リコン膜３のサイド・エツチングを行なう。この際に適
用するエツチング技術としては、ＣＦ４と０２の混合ガ
スをエッチャントとするプラスマエソチング法或いはウ
ェット・エツチング法等を採用して良い。(■ TIP) Side etching of the polycrystalline silicon film 3 is performed using the resist film 4 as a mask.Etching techniques to be applied at this time include plasma etching using a mixed gas of CF4 and 02 as an etchant, or wet etching.・Etching method etc. may be used.
これに依り、フォト・レジスト膜４１よ庇４Δが形成さ
れる。尚、記号６はサイト・エノグ〜ングに依り形成さ
れた空所を指示してＧ１て、この空所６の奥行は０．２
〔μｍ〕程度もあれＧよ良Ｇ１゜第３図参照
■ スパッタ法或いは蒸着法を適用し、ｌｙさ（り１１
えば１０００ 〔人〕のアルミニウム−ＩＩＷ （第２
（７）マスク膜）７を形成する。このアルミニウムｌ
ｑ ７ Ｌ上空所６に対向して露出されている窒化ノリ
コンＳ色牟象膜２の部分には付着しない。As a result, an eave 4Δ is formed from the photoresist film 41. In addition, the symbol 6 indicates the void formed by the site enog~ng, and the depth of this void 6 is 0.2.
[μm] G or better G1゜Refer to Figure 3 ■ Sputtering or vapor deposition method is applied,
For example, 1000 [people] of aluminum-IIW (second
(7) Mask film) 7 is formed. This aluminum
It does not adhere to the portion of the nitrided noricon S color film 2 that is exposed facing the q 7 L upper space 6 .
第４図参照
■ フォト・レジスト膜４の剥離液中Ｇこ浸漬すること
に依りフォト・レジスト膜４を溶解除去１−ると同時に
その上のアルミニウム肱７をＩＪフｌ−・、４−フする
。Refer to Fig. 4 ■ The photoresist film 4 is dissolved and removed by dipping it in the stripping solution 1-, and at the same time the aluminum collar 7 on it is removed by IJ flush, 4-flush. do.
■ 前記工程でパターニングされた７ルミニウム膜７を
マスクとして窒化シリコン絶縁膜２の工・ノチングを行
なう。この時の工・ノチング番こむよ、ＣＦ４１０２を
エッチャントとするりアクティブ゛・スノぐツク エツ
チング法を適用することができる。(2) Processing and notching of the silicon nitride insulating film 2 is performed using the 7-luminium film 7 patterned in the above step as a mask. At this time, an active notching method can be applied using CF4102 as an etchant.
これに依り、窒化シリコン絶縁膜２には、溝状の窓８及
び９が形成され、その窓８及び９内にはシリコン半導体
基板１の表面が露出する。As a result, groove-shaped windows 8 and 9 are formed in the silicon nitride insulating film 2, and the surface of the silicon semiconductor substrate 1 is exposed within the windows 8 and 9.
第５図参１（（（
［相］ アルミニウム膜７を除去してから、化学気相堆
稍法にて、厚さ例えば３０００ （人〕程度の多結晶シ
リコン膜（第２の導電膜）１０を形成する。Figure 5 Reference 1 ((([Phase] After removing the aluminum film 7, a polycrystalline silicon film (second conductive film) 10 with a thickness of, for example, about 3,000 mm is formed by chemical vapor deposition. form.
第６図参！！（１
■ エッヂヤントとじてＣＣＩ、或いはＣＦ、１０２カ
スを用いたりアクティブ・イオン・エツチング法にて、
窒化シリコン膜２の表面が露出“Ｊろまで多結晶ノリ：
ｌン股１ｏをエツチングする。ごのＪ、・）に：■−ソ
チングすると多結晶シリ：Ｉン３の平ｊ、１４な表面が
露出゛Ｊる。See Figure 6! ! (1) Using CCI, CF, or 102 slag as an edgeant, or using active ion etching,
The surface of the silicon nitride film 2 is exposed with polycrystalline glue:
Etching the crotch 1o. When the surface of the polycrystalline silicon layer 3 is sown, the flat surface of the polycrystalline silicon layer 3 is exposed.
これに依り、多結晶シリコンＩＩＡ ｌ Ｏは窒化シリ
：Ｊン絶縁膜２に形成された溝状の窓８及び９の近（Ｘ
にのめ残留さ−ｌることができる。尚、残Ｗ、ｌ シた
多結晶シリコン欣を記９Ｉｌ及び１２て（ｈ示しである
・
第７図参照
＠ 熱酸化法にて多結晶シリコン膜３，１１．１２の表
面を酸化し、厚さ例えば２０００ （人〕程度の二酸化
シリコン絶縁膜１３を形成する。゛これと同時に多結晶
シリコン膜３がら半導体基板１に砒素が拡散され、ｎ＋
型領領域１５１６が形成される。このｎ＋型領領域１５
１６はソース領域及びトレイン領域となるものである。As a result, the polycrystalline silicon IIA lO is deposited near the groove-shaped windows 8 and 9 formed in the silicon nitride insulating film 2 (X
It can be left behind for a long time. Note that the remaining W, l and polycrystalline silicon layers are shown in 9Il and 12 (h is shown. See Figure 7. The surfaces of the polycrystalline silicon films 3, 11, and 12 are oxidized by thermal oxidation method, and the thickness is For example, a silicon dioxide insulating film 13 having a thickness of about 2,000 people is formed. At the same time, arsenic is diffused into the semiconductor substrate 1 from the polycrystalline silicon film 3, and n+
A mold region 1516 is formed. This n+ type region 15
16 is a source region and a train region.
第８図参照
０７オト・リソグラフィ技術にて二酸化シリコン絶縁膜
１３をエツチングして電極コンタク１−窓Ｉ７及び１８
を形成する。Refer to Figure 8 07 Etching the silicon dioxide insulating film 13 using photolithography technology to form electrode contact 1 - window I7 and 18.
form.
■ スパッタ法或いは蒸着法を適用してアルミニウム膜
を形成し、これをパターニンクしてグー１−電極１９、
ソース電極２０、ドレイン電極２１を形成し完成する。■ Apply sputtering or vapor deposition to form an aluminum film, pattern this to form goo 1-electrode 19,
A source electrode 20 and a drain electrode 21 are formed and completed.
前記実施例では、窒化シリコン絶縁膜２をケート絶縁膜
として使用したが、それを用いずに、新たにシリコン半
導体基板１を熱酸化或いは熱窒化してケート絶縁膜を形
成しても良い。In the embodiment described above, the silicon nitride insulating film 2 was used as the gate insulating film, but instead of using it, the silicon semiconductor substrate 1 may be thermally oxidized or thermally nitrided to form a gate insulating film.
ごのような」−程を採るごとに依り、従来技術に比較し
て、例えばソース領域及び１′Ｌ・イン領域の大きさは
１桁以上も微イ、■化することか一ζきる。For example, the size of the source region and the 1'L/in region can be reduced by more than one order of magnitude compared to the prior art, depending on the degree of change taken.
因に、ソース領域とチャネル領域と１ルイン領域を加え
た長さを１ 〔μｍ〕以）にすることができる。Incidentally, the total length of the source region, channel region, and one Ruin region can be set to 1 [μm] or less.
第９図は、前記］］程で製造される電界効果半導体装置
に於けるパターンの関係を表わす要口１；平面図である
。FIG. 9 is a plan view illustrating the relationship between patterns in the field effect semiconductor device manufactured in the above step 1.
図に於いて、３１はフィールド絶縁膜に形成されるパタ
ーン、３２はフォｌ−・レジスｌ ＩＩＷ ４で形成さ
れるパターン、３３は電極コンタクト窓１７及び１８で
形成されるパターン、３４はケート電極１９で形成され
るパターンをそれぞれ示している。In the figure, 31 is a pattern formed on the field insulating film, 32 is a pattern formed on Fol-Resist IIW 4, 33 is a pattern formed on electrode contact windows 17 and 18, and 34 is a gate electrode. The patterns formed in step 19 are shown respectively.
発明の効果
本発明に依れば、半導体基板上に絶縁膜、不純物を高濃
度にドープされ多数の帯状になされた第１の導電膜、活
性領域形成予定部分に窓を有する第１のマスク映をそれ
ぞれ形成し、第１の導電膜に開口を形成してから第１の
導電膜をサイド・エツチングして空所を形成し、該空所
に対向する前記絶縁膜をエツチングして半導体基板を露
出さゼてから第２の導電膜を形成して半導体基板と第１
の導電膜との電気接触を採り、その後、熱処理して第１
の導電膜から半導体基板に不純物を拡１）ｋシソース領
域及びドレイン領域を形成するようにしているので、電
極の引き出し部分がセルフ・アラインメント的に形成さ
れ、その面、ｒｆｆは著しく小さなものとすることがで
き、また、ソース領域及びドレイン領域もセルフ・アラ
インメント的に形成−ζきるので、アラインメント余裕
を必要とせず、その面積を小さくすることが可能である
から電界りＪ果半導体装置の集積度を向上するのに有す
ノである。そして、その小型化に依り、寄生容量を低下
さ−１ることができ、高周波性能を向上させることも可
能である。Effects of the Invention According to the present invention, an insulating film is formed on a semiconductor substrate, a first conductive film doped with impurities in a large number of strips, and a first mask film having a window in a portion where an active region is to be formed. After forming an opening in the first conductive film, side etching the first conductive film to form a cavity, and etching the insulating film opposite to the cavity to form a semiconductor substrate. After the exposure, a second conductive film is formed to connect the semiconductor substrate and the first conductive film.
electrical contact with the conductive film, and then heat-treated the first
1) Since the impurity is spread from the conductive film to the semiconductor substrate to form the source region and drain region, the electrode extension portion is formed in a self-aligned manner, and the rff on that surface is extremely small. In addition, since the source and drain regions can be formed in a self-aligned manner, alignment margins are not required and the area can be reduced, which reduces the electric field and the integration density of the semiconductor device. It is a good idea to improve your skills. By reducing the size, parasitic capacitance can be reduced by -1, and high frequency performance can be improved.
第１図乃至第８図は本発明−実施例を説明する為の工程
要所に於ける半導体装置の要部切断側面図、第９図は前
記実施例にて製造される電界効果半導体装置に於けるパ
ターンの関係を表わす要部平面図である。
図に於いて、■はノリコン半導体基板、２は窒化シリコ
ン膜、３は多結晶シリコン膜、４はフォト・レジスト膜
、５は窓、６は空所、７はアルミ。
ニウム膜、８及び９はコンタクト窓、１０，１１゜１２
は多結晶シリコン膜、１３は二酸化シリコン絶縁膜、１
５及び１６はｎ＋型領領域１７及び１８は電極コンタク
ト窓、１９はケート電極、２０はソース電極、２１はト
レイン電極である。
特許出願人 富士通株式会社
代理人弁理士 玉蟲 久五部
（外３名）1 to 8 are cross-sectional side views of main parts of a semiconductor device at important process points for explaining the present invention-embodiments, and FIG. 9 is a side view of a field-effect semiconductor device manufactured in the above embodiment. FIG. 3 is a plan view of main parts showing the relationship between patterns in the drawing. In the figure, ■ is a Noricon semiconductor substrate, 2 is a silicon nitride film, 3 is a polycrystalline silicon film, 4 is a photoresist film, 5 is a window, 6 is a void, and 7 is aluminum. Ni film, 8 and 9 are contact windows, 10, 11゜12
1 is a polycrystalline silicon film, 13 is a silicon dioxide insulating film, and 1 is a polycrystalline silicon film.
5 and 16 are n+ type regions 17 and 18 are electrode contact windows, 19 is a gate electrode, 20 is a source electrode, and 21 is a train electrode. Patent applicant: Fujitsu Ltd. Representative Patent Attorney: Kugobe Tamamushi (3 others)
Claims (1)
・１１シ状の第１の導電膜と活性領域形成予定部分に窓
を有する第１のマスク膜とを順に形成し、次に、第１の
導電膜を選択的に除去して前記窓と同パターンの開口を
形成してからサイド・エツチングを行なって第１のマス
ク膜の下に空所を形成し、次に、第２のマスク膜を形成
してから第１のマスク膜を除去することに依りその上の
第２のマスク膜をリフト・オフし、次に、残留した第２
のマスク膜と第１の導電膜との間の前記絶縁膜を除去し
て半導体基板の一部表面を露出し、次に、第２のマスク
膜を除去してから酸化可能な月利からなる第２の導電膜
を形成して第１の導電膜と半導体基板との電気接続を行
ない、次に、熱処理を行なって第１の導電膜から半導体
基板に不純物を拡（１にシソース領域及びドレイン領域
を形成する工程が含まれてなることを特徴とする半導体
装置の製造方法。An insulating film, a first conductive film doped with impurities at a high concentration, and a first mask film having a window in a portion where an active region is to be formed are sequentially formed on a semiconductor substrate. The first conductive film is selectively removed to form an opening in the same pattern as the window, side etching is performed to form a void under the first mask film, and then the second mask film is etched. After forming the film, the second mask film thereon is lifted off by removing the first mask film, and then the remaining second mask film is removed.
The insulating film between the mask film and the first conductive film is removed to expose a part of the surface of the semiconductor substrate, and then the second mask film is removed. A second conductive film is formed to electrically connect the first conductive film and the semiconductor substrate, and then heat treatment is performed to spread impurities from the first conductive film to the semiconductor substrate (1) A method of manufacturing a semiconductor device, comprising the step of forming a region.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17202682A JPS5961186A (en) | 1982-09-30 | 1982-09-30 | Manufacture of semiconductor device |
| US06/537,017 US4545114A (en) | 1982-09-30 | 1983-09-29 | Method of producing semiconductor device |
| EP83305971A EP0107416B1 (en) | 1982-09-30 | 1983-09-30 | Method of producing semiconductor device |
| DE8383305971T DE3380615D1 (en) | 1982-09-30 | 1983-09-30 | Method of producing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17202682A JPS5961186A (en) | 1982-09-30 | 1982-09-30 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5961186A true JPS5961186A (en) | 1984-04-07 |
| JPH0481328B2 JPH0481328B2 (en) | 1992-12-22 |
Family
ID=15934141
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17202682A Granted JPS5961186A (en) | 1982-09-30 | 1982-09-30 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5961186A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5492070A (en) * | 1977-12-29 | 1979-07-20 | Nippon Telegr & Teleph Corp <Ntt> | Mis field effect transistor and its manufacture |
-
1982
- 1982-09-30 JP JP17202682A patent/JPS5961186A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5492070A (en) * | 1977-12-29 | 1979-07-20 | Nippon Telegr & Teleph Corp <Ntt> | Mis field effect transistor and its manufacture |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0481328B2 (en) | 1992-12-22 |
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