JPS5960663A - Expansion system of address of microprocessor - Google Patents

Abstract

PURPOSE:To expand easily an address, by providing a register designating a microprocessor having a limited number of addresses or a memory having partly overlapped addresses is to be used. CONSTITUTION:An operation program OP is accommodated in an area (addresses a-a', a''-b) of a memory M1. The same addresses as the addresses a- a' of the area A are assigned duplicatedly to the other memory M2, and a diagnostic program DP having less frequency is accommodated in the area B of the M2. The area C (addresses c-c') is accommodated with a diagnostic program receiving program. Other useful program is accommodated additionally to an area D consisting of addresses c''-d. One address (e) is given to a register R provided in addition to the memories M1, M2. The addresses a-a' of the memories M1, M2 to be used is designated by the address (e) to the microprocessor unit (not shown). Thus, the address is expanded easily.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a microprocessor address expansion scheme and, more particularly, to a microprocessor address expansion scheme that can send out only a limited number of unique addresses. Regarding expansion methods.

Prior Art and Problems As a microprocessor, an LSI configured as a general-purpose microprocessor unit is often used. However, the number of addresses that a microprocessor unit can send cannot exceed a specific number. For example, 1
This is because a microprocessor unit with six bins cannot send out more than 216 addresses, and it is also impossible to increase the number of bins.

For example, when a control device of an information processing device is configured with a microprocessor, the control device often has a diagnostic program for self-diagnosis. However, this diagnostic program is normally accessed much less frequently than the operation program that performs actual control operations.

In order to accommodate the diagnostic program, as well as the operating program, a fixed address is naturally required for the microprocessor.

FIG. 1 is a diagram showing the above-mentioned program accommodation method according to the prior art. In the figure, M indicates a memory, in which area A stores an operation program and area B stores a diagnostic program. R is a register provided in D1 of the above memory. Upper b [4 Memory addresses are α to b for area A, c to c for area B, and one address e for register R if there is one register. Assign. Although the frequency of access to area B (address c-d) containing the diagnostic program is not infrequent, the address t-d mentioned above cannot be used for accessing the operation program control program that performs normal operations. .

As described above, according to the conventional technology, in the above-mentioned control device using a microprocessor unit, the number of addresses sent by the microprocessor unit is a number specific to the microprocessor unit. Even if the access frequency is extremely low, if it is a necessary program, the required number of addresses must be set up to accommodate the program, so even if there are other useful programs, However, there are cases where there is a shortage of addresses for the useful program and it cannot be accommodated, which is a disadvantage in that the ability of the control device v using a microprocessor can be improved.

OBJECTS OF THE INVENTION The present invention obviates the above-mentioned drawbacks of the prior art and substantially extends the address sending of microprocessors having a limited unique number of addresses, thereby adding useful programs. The purpose is to improve the capabilities of control devices that accommodate and use microprocessors.

Examples of the invention Hereinafter, embodiments of the present invention will be explained with reference to the drawings.

FIG. 2 shows a program storage system according to the present invention, and M, . . . M2 indicate memories. Area A(0)+A(x) corresponding to area A in Figure 1 (address α~α'
α″~b) accommodates the operation program OP. Note that the address a given to area A(0)
The same address as ~α' is redundantly assigned to area B of another memory M2, and the diagnostic program ρP is stored in area B of this memory M2. Area C (address c-c') contains a diagnostic program reception program (DPRP).
is accommodated. This diagnostic program reception program (DPRP) is a program for reception and notification of results, and its function is only 1m, so
The capacitance is very small and the area C may be small. By allocating addresses in this manner, an empty area is created which is accessed by addresses C'' to d, and other useful programs can be additionally accommodated in this area.

The above memo IJ Ml, register R provided outside M2
As in FIG. 1, one address e is assigned to 7.

Since the program is stored in the microprocessor unit MPU, if addresses α to α' are selected, both areas A(0) and B will be accessed at the same time, which is inconvenient. In order to avoid this inconvenience, the control device using the microprocessor unit (MPU) has the connection configuration shown in No. 6M.

In FIG. 6, MPU is a microprocessor unit, R is a register, ROM6, ROM1 .
RO) 12 is a read-only memory, AB is an address bus, and DB is a data bus. Area A in Figure 2 (
0) is in the read-only memory ROMI, the same area, ((1), (? and D are in the read-only memory ROM0, area B is the read-only memory ROM.

Read-only memory R, which is a different memory device from
OM, respectively.

Microprocessor unit MPU is at address α″
~,! +, C-CZ C#~d to address bus A
When sent to E, the area corresponding to the sent address,
((1) Data is read from the corresponding address of the read-only memory ROMo containing +C and D onto the data bus DB.

Microprocessor unit MPU area A (0
) corresponding read-only memory ROM, I) or a different read-only memory Rohr2 corresponding to area B.
Specify either one of the memory devices 6° (R
on or ROM2) to duplicate addresses α to α
To read the contents of ′, the microprocessor:
L = Mprt, if, sends address e for selecting register R to address bus AB, also sends information specifying read-only memory ROMI or ROMz to data bus DB, and sends this information to data bus DB. is stored in register R. It is assumed that each cell of register R is composed of a flip-flop, and when there is address information specifying register R on address bus AB, each cell is temporarily set to data on data bus DB. . For example, when specifying read-only memory ROA (1) to operate, make sure that the specific 1 bit (control bit CB) of register R reaches "0#" and read-only memory When specifying ROMx to operate, select the above data so that it becomes "1" as well.In this case, the control pin (CB) is used to operate only one of the memory devices ROM1 and ROM2. This is the specified information.

, the information of the control bit CB at the above-mentioned specific position of register R is transmitted from that position of register R to both the read-only memory ROM and R0M2, and if the control bit CB is 0'', the information of the control bit CB is・Only memory ROM1
If the control bit CB is 1'' and the read-only memory ROM2 is operable, and the control bit CB is 1'', then the read-only memory ROMI is
is inoperable, and read-only memory R0M2 is enabled.

Now, for example, set the control pin (above) CB to 0'', designate the read-only memory ROMt as operable and the read-only memory ROM as inoperable, and set the microprocessor unit to 0''. ) A(P
When U selects duplicate addresses a to α' and sends them to address bus AB, read-only memory IJ
Since ROkf2 is inoperable, only the operable read-only memory ROM1 operates, receives the above address, and transfers its contents from this address to the data bus DB.
Read out.

In the above, set the control pitch (CB) to 0" instead of "1".
”, contrary to the above, read-only memory ROM becomes inoperable and read-only memory IJ RO
Since AI2 is designated as operational, the read-only memory ROA is
Data is extracted from fz.

In an information processing system using a microprocessor unit as shown in FIG.
R4N+ and ROAf2 are located in area A (
11, (' and D1 as well as area A(0) and area B
, and programs are stored in each area.

The normal operation is in areas A (0) and A in Figure 2.
(1) In some cases, this is performed by a program (operation program) stored in the area. A diagnostic program DP is accommodated in an area B designated by an address that overlaps (is the same as) area A (0). This information processing system has at least duplicate control devices, so if one system is currently in use, the other system is on standby as a backup.

Now, for example, if the current system requires diagnosis, the other redundant system will operate normally as the current system, and the system requiring diagnosis will be disconnected from the system and the diagnostic program will be run. Start up and perform diagnosis.

To perform diagnosis, the system control device disconnected from the system starts the diagnostic program reception program DPRP stored in area C.

This program DPRP first checks the normality of the control bits of register R, and then checks the read-only memory R corresponding to area B where the diagnostic program np is stored.
Set the control bit of register R to "1" to enable OM2. Thereafter, when the microprocessor unit JfPU first sends the address α to the address bus AE and runs the memory from the address α, the diagnostic program DP stored in the read-only memory IJ RoAr2 is activated and self-diagnosis is performed. It is done. At this time, read-only memory ROM
, is not activated because it is in an inoperable state, and the operation program OP balance stored therein does not run.

After the diagnosis is completed, the diagnosis result is saved by the diagnosis program DP on a rank access memory (not shown) provided in the same way as the read-only memory ROMo, and the diagnosis program reception stored in area C is Return to the program DPRP.

The register R is set to trill by the program DPRP.
? 11=The 11 bit is returned to 0'' and returns to normal operation.

Figure 4 shows the above operation, that is, when one system is performing normal operation as a working fit, when it becomes necessary to diagnose, self-diagnosis is performed and normal m1 is restored again.
It is a diagram showing the flow of the 91 works of the grant that returns to one work.

In the above embodiment, the control device configured using a microprocessor unit is duplicated, so the system that performs self-diagnosis is disconnected from the system, and the normal operation is performed by other thread control devices. Therefore, there is no need to perform normal operations, and only the diagnostic program DP runs. Therefore, when accessing duplicate addresses α to α′, it is important to be aware of whether to access the read-only memory ROM or ROM2 using register R.
control bits only.

Although one embodiment of the present invention has been described above, the present invention is not limited to the above embodiment, and various modifications can be made within the technical scope thereof.

Effects of the Invention Since the present invention is configured as described above, in a control device for an information processing device configured using a known microprocessor unit to which only a limited number of unique addresses can be assigned, This has the effect of allowing some addresses to be used redundantly, thereby extending the addresses of the microprocessor unit. By additionally accommodating useful programs, takes, etc. to the expanded address, the information processing device u
This has the effect of improving the performance of the control device used.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a program accommodating method according to the prior art, FIG. 2 is a diagram showing a program accommodating method according to the present invention, and FIG. 6 is a diagram showing a connection of an example of a control device according to the present invention for an information processing device. A block diagram showing the configuration, and FIG. 4 is an operation flow diagram in an embodiment of the present invention. AIPU...Micro processor unit, R.
・Register, ROMoHROM1, ROM2 ・
= Read-only memory, AB...address node, DB...take node Patent applicant Fujitsu Limited Representative Patent Attorney Hisabu Tamamushi (6 others) 33 Figure 1 2nd mouthpiece 3 Figure 4

Claims (1)

[Claims] A microprocessor that can only send out a limited number of 1ml addresses, a different memory device to which some of the addresses are given over and over again, and a device that can only operate one of the above memory devices. and a register for setting designation information of a memory device to be operated, and information designating a memory device to be operated is set in advance in the register, and when the duplicate address is sent by the microprocessor, the register is set in the register. The address extension method of the tossle microprocessor is characterized in that only one memory device specified by specified information is operated.