JPS61139858A - Access control system for dual port memory - Google Patents

Abstract

PURPOSE:To collect securely information for trouble analysis when abnormality occurs by allowing access to only one block of a dual port memory from a system common bus side normally and allowing access to an optionally specified block when abnormality occurs. CONSTITUTION:A system common bus interface part is provided with a memory block specifying circuit which specifies from the side of the system common bus 2 which block of the dual port memory 4 is selected and accessed and a lock circuit 23 which is allowed to function only when the abnormal state of the dual port memory 4 is detected. The memory specifying circuit is normally off through the lock circuit 23 to allow access to only one predetermined block area of the dual port memory 4 from the side of the system common bus 2 and if a microprocessor becomes unable to operate in the abnormal state, the memory block specifying circuit is put in operation to access a desired memory block from the side of the system common bus 2.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is arranged in a device with a built-in processor such as an input/output control device connected to a common bus of a computer system, and is connected to a system common bus and an internal microprocessor bus. This invention relates to an access control method for a dual-port memory that can be accessed from both sides.

[Conventional technology]

In computer systems, as a means of efficiently exchanging information between various devices with built-in microprocessors connected to the system common bus, each device has an interface between the system common bus and the internal microprocessor bus. There is a way to provide dual port memory.

For example, in a human output control device, control registers for setting commands from the central processing unit and continuously outputting status are realized using dual port memory. Incidentally, recently, highly integrated and large capacity semiconductor memories have become available at low cost, so using them it is possible to construct a large capacity dual port memory despite a small amount of hardware. Therefore, it is recommended to use part of the storage area of the dual port memory as the control register area of the device, and use the other part for various purposes such as the stack area, work area, or data buffer area for the built-in microprocessor. It's normal.

In the dual-port memory used as described above, it is the control register area that originally needs to be accessed from the system common bus side, and other areas are accessed by the internal microprocessor according to commands from the central processing unit. Since this area is used for internal processing to control output devices, if this area is also accessible from the system common bus side, there is a risk of malfunction of the control device.

To this end, the address allocation range for the dual port memory on the system common bus side is narrowed down to the portion corresponding to the control register area allocated as part of the dual port memory, and only the control register area can be accessed from the system common bus side. A circuit configuration like this is adopted.

A dual port memory circuit in this type of input/output control device has conventionally been configured as shown in FIG.

That is, the input/output controller 1 has dual ports that interface to a system common bus 2 connected to an external central processing unit and an internal microprocessor bus 3 connected to an internal microprocessor (not shown). It has memory 4.

Here, the numbers of the system common bus 2, internal microprocessor bus 3, and memory (address) bus 5 are 16 (SA15 to 0) and 16 (IA
15-0) and 12 (MA12-1), among these, 5A15. It is assumed that lA15 and MA12 are the most significant bits (MSB), and that dual port memory 4 has a capacity of 8 kilobytes.

Then, when the dual port memory 4 is accessed from the internal microprocessor bus °3 side of the input/output control device 1, the addresses lA15 to IA15 of the internal microprocessor bus 3 are accessed.
13 is taken into the address comparison circuit 16, and a memory selection signal g indicating that the dual port memory 4 is being accessed is output.
7.

This memory access control circuit 17 receives the memory selection signal g and IAO, which is the least significant bit (LSB) of the address, and outputs an upper byte memory chip select signal as a memory access control signal, a lower byte memory chip select signal i, and a memory chip select signal i. In addition to the generation condition of the write enable signal j, the memory access exclusive control signal l is outputted, thereby requesting access to the dual port memory 4, and after obtaining permission for the request, that is, acquiring the right to access the dual port memory. After that, the address buffer control signal k is enabled and the gate of the address buffer 18 is opened.

As a result, the address buffer 18 has the address lAl
2 to 1 are output to the memory bus 5 side, and addresses MA12 to MA1 are applied to the address input terminals of each memory chip constituting the dual port memory 4.

Since the capacity of the dual port memory 4 is 8 kilobytes, the entire area can be addressed with 13 bits of addresses lAl2-0. - That is, from the internal microprocessor bus 3 side to the dual port memory 4
You will be able to access the entire area.

Next, as the control register area of the input/output control device 1, 25
It is assumed that 6 bytes are allocated to the system common bus address space and a 256 byte area in the dual port memory 4 is used for the control register.

When the control register area in the dual port memory 4 is accessed from the system common bus 2 side, the address comparison circuit 11 receives the upper addresses 5A15 to 8 excluding addresses SA7 to 0 that address 256 bytes, and this causes the dual port memory A memory selection signal a indicating that memory 4 is being accessed is output to the memory access control circuit 12.

This memory access control circuit 12, like the memory access control circuit 17 on the internal microprocessor bus 3 side, receives a memory selection signal a and an address SA.
0 is the upper byte memory chip select signal as the memory access control signal.

This is the condition for generating the lower byte memory chip select signal C and the memory write enable signal d, and its operation is similar to that of the memory access control circuit 17.

In addition, the input/output control device 1 has an address setting switch circuit 15, which divides 8 kilobytes of the dual port memory 4 into 32 block areas with 256-byte boundaries in advance, and selects which one of the block areas. A 5-bit switch determines whether the 256-byte area is to be used as a control register area.

Then, when the address buffer control signal e is output from the memory access control circuit 12, the address buffers 13 and 14 are activated, and the addresses SA7 to SA1 are activated.
and set values of the address setting switch circuit 15 are set at memory bus addresses MA7-1 and MAO (reflected on upper and lower height memory chip select signals S and C), respectively.
The desired byte or word within the 56-byte area is designated. For example, if binary "oooooo" is set in the address setting switch circuit 15, block "0" is set, and if binary "11111" is set, block 31 is set.

By the way, if some abnormality occurs in the control device with a built-in microprocessor, and the microprocessor becomes inoperable and the device is unable to perform its functions, the dual port memory 4 used by the microprocessor is useful for failure analysis. The contents of the stack area and work area and the history information of internal processing by the microprocessor are useful.

[Problem that the invention seeks to solve]

However, in the conventional dual-port memory access control method described above, access to the dual-port memory from the system common bus side is limited only to the control register area, so when an abnormality occurs in the control device as described above, The information that can be obtained from the system common bus side for failure analysis is only that set in the status register area prepared in the control register area.Moreover, the information set in this status register area is internal Since it is executed by a microprocessor, there is no guarantee that the information will be set correctly if the microprocessor becomes inoperable due to the occurrence of an abnormal condition. There is also a method of discharging the internal information of the device to the system common bus side using a command from the central processing unit, but in this case too, it is the internal microprocessor that executes the processing, and if an abnormal state occurs in the device. It is unreasonable to expect the microprocessor to perform normal command processing under these conditions.

In this way, with the conventional dual-port memory access control method, it is difficult to collect reliable and sufficient information about the control device from the system common bus side in order to analyze the failure of a device that has become inoperable due to an abnormal condition. The problem was that it couldn't be done.

Therefore, the present invention provides a system for collecting information for failure analysis when a control device becomes abnormal and becomes inoperable.
An object of the present invention is to provide a dual port memory access control method that allows access not only to a device control register area in a dual port memory but also to any other area from the system common bus side using a simple procedure.

[Means for solving problems]

In order to solve the above problems, the present invention provides a dual port memory that is connected to a system common bus and is provided in a device containing a built-in processor, and that is accessible from both the system common bus side and the internal processor bus side. A memory block designation circuit that allows specifying which block of the dual port memory to be selected and accessed from the system common bus side is provided at an interface with the system common path, and the memory block designation circuit is connected to the dual port memory. A lock circuit is provided that functions only when an abnormal state is detected in the device to which the The present invention is characterized in that when a device to which the memory belongs is in an abnormal state, access to any block of the dual port memory designated by the memory block designation circuit is enabled.

[Effect]

The present invention provides a system common bus interface with a memory block I accounting circuit that enables a system common bus to specify which block of dual port memory is to be selected and accessed, and a memory block designation circuit. A lock circuit is provided that operates only when it is detected that the device to which the dual port memory belongs is in an abnormal state, and when the device to which the dual port memory belongs is operating normally, the lock circuit deactivates the memory block designation circuit. Only one predetermined block area of the dual port memory can be accessed from the system common bus side, and when the microprocessor becomes inoperable due to an abnormal condition, the memory block designation circuit is activated and the system common bus By setting a desired memory block number to the memory block designation circuit from the side, access to the eight corresponding blocks of the dual port memory can be performed in exactly the same manner as during normal operation of the device.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, parts corresponding to those in FIG. 2 are given the same reference numerals, and a detailed explanation thereof will be omitted, but in the present invention, the interface with the control system common bus 2 of the input/output control device 1 A memory block designation register 21 as a memory block designation circuit, an address buffer 22, and a lock circuit 23 are provided in the section.

Lock circuit 23 is 1, memory block specification register 24
．． Latch circuit 25. Inverter 26 and AND circuit 27
, 28.29.

When 5-bit memory address data mapped to an address different from the address of the device control register area on the system common bus address space is supplied via the data buses SD4 to SD0, the register access control circuit 24 performs a logical AN register write signal m with value “1”
It is output to one input terminal of the D gate 27. The other input terminal of the AND gate 27 is supplied with a down signal n from an abnormal state detection circuit 30 that detects an abnormal state of the manual operation control 1. This abnormal state detection circuit 30 detects a logical value " when any abnormal state occurs in the input/output control device 1
A down signal n of 1" is output, and this down signal n is
It is supplied to the ND gate 27 and also to an internal microprocessor (not shown) to prompt the internal microprocessor to transition from a normal operating state to an inoperable state. Use what is commonly used for this type of equipment.

The memory block designation register 21 is an AND gate 27
It is possible to write the 5-bit memory block designation data transmitted from the system common bus 2 side via the 5 data signal lines of data buses SD4 to SD0 at the time when the logical value "1" output is input from the system common bus 2 side. The written data value is always output to the address buffer 22.

The launch circuit 25 latches the output signal of the AND gate 27, supplies the launch signal directly to one input terminal of the AND gate 2 as the register set status signal p, and also supplies the launch signal to one input terminal of the AND gate 29 via the inverter 26.
to one input side of the Note that the latch circuit 25 is
It is initialized only when the human output control device 1 is initialized by reset, and in that case, the register set stator large signal p is set to the logical value "0".

Further, the address buffer control signal e from the memory address control circuit "12" is supplied to the other input side of the AND gates 28 and 29, and the output signal of the AND gate 28 is supplied to the address buffer 22, and the output signal of the AND gate 29 is A signal is supplied to each address buffer 14 as an operation control signal.

Next, the effect will be explained. Now, assuming that the input/output control device 1 is operating normally, the down signal n from the abnormal state detection circuit 30 maintains the logical value "0", and the output of the AND gate 27 is also register accessed. The logic value "0" is maintained regardless of the state of the register write signal m of the control circuit 24, and therefore, the memory block designation register 21 is in a state where writing of memory address data from the system common bus 2 is prohibited. The register set status signal p, which is controlled and output from the latch circuit 25, maintains a logical value of "0". Therefore, from the AND gate 28, the address buffer control signal q
is not output, the gate of the address buffer 22 is controlled to be closed, and the inverted signal p at the inverter 26 has a logic value "L", and the AND gate 29 is opened, and the gate of the address buffer 22 is controlled to be closed. An address buffer control signal r based on the address buffer control signal e from the memory access control circuit 12 is output to the address buffer 14. As a result, the set value of address setting switch circuit 15 is output onto memory bus 5 as memory bus addresses MA12-MA8. At the same time, the address buffer control signal e from the memory access control circuit 12 opens the gate of the address buffer 13, and the addresses SA7-1 are output to the memory bus 5 as MA7-1.

Therefore, one of the 256-byte areas obtained by dividing the 8 kilobyte memory area of the dual port memory 4 into 32 equal parts is selected by the 5-bit addresses MA12 to MA8 on the memory bus 5, and the memory bus addresses MA7 to MA8 and the upper , M reflected in the lower memory chip select signal S, c
A byte or word at a desired address within the 256-byte area selected by the AO is specified, and the dual port memory 4 can be accessed in a normal state.

From the above normal state of the input/output control device 1, the input/output device 1
If any abnormal condition occurs in the abnormal condition detection circuit 2
5 outputs a down signal n having a logical value of "1". This down signal n causes an internal microprocessor (not shown) to transition from a normal operating state to an inoperable state. In this state, it is still possible to access the predetermined memory area assigned as the control register area of the dual port memory 4 from the system common bus 2 side as in normal operation.

From this state, the system common bus 2 side inputs a block number corresponding to the 256-byte area to be accessed from the data bus SD4 to SD4 to the memory block designation register 21.
When attempting to write 5-bit memory block data using , this is also supplied to the register access control circuit 24 , so a register write signal m with a logical value of "1" is sent from the register access control circuit 24 to the AND gate 27 . Output.

At this time, since the down signal n from the abnormal state detection circuit 30 has a logical value of "1", the A N D gate 27
A register set signal O with a logical value of “1” is output from
As a result, the memory block designation register 21 stores the data on the data buses SD4 to SD0, and constantly outputs the stored data value to the address buffer 22. At the same time, the register set signal 0 is latched by the latch circuit 25, thereby storing the state that data was stored in the memory block designation register 21 when the input/output control device 1 was in the down state, and representing the state. Outputs a register set status signal p with a logical value of "1".

Therefore, the output of the address buffer control signal r from the AND gate 29 is prohibited, and the output of the address I account data from the address buffer 14 is stopped.Instead, the output of the address I account data from the AND gate 28 is Buffer control (S) Based on No. e (address buffer control signal q is output).

Therefore, the gate of the address buffer 22 is opened, and the memory block number value already stored in the memory block designation register 21 is transferred to the memory bus address MA.
12 to 8 and output to the memory bus 5 side. On the other hand, address buffer 13 outputs addresses SA7-1 to memory bus 5 as MA7-1 in response to address buffer control signal e.

In this way, the 256-byte area of the dual port memory 4 corresponding to the memory block number arbitrarily set in the memory block designation register 21 can be accessed from the system common bus 2 side. That is, for example, the address setting switch circuit 15 receives the binary "oooooo".
is set, and even if the input/output control device 1 is in a normal operating state or in an inoperable state, if writing to the memory block designation register 21 is not performed,
Block “0” is accessed from the system common bus 2 side. Then, when the human output control device l is in an inoperable state, the memory block designation register 21 is set to binary “00”.
Assuming that data of 100" has been written, block "4" can be accessed from the system common bus 2 side. Also, by changing the value set in the memory block specification register 21, this can be accessed from the system common bus 2 side. Accordingly, the accessible blocks of the memory area of the dual port memory 4 can be changed.As a result,
Device internal information for failure analysis when an abnormal condition occurs can be collected from the dual port memory.

Furthermore, even if the input/output control device l performs a write operation to the memory block specification register 21 in a normal operating state, the down signal n from the abnormal state detection circuit 30 has a logical value of "O", so that Writing becomes invalid and does not affect access to the normal control register area of the dual port memory 4.

In the above embodiment, the case is explained in which the outputs from the address setting switch circuit 15 and the memory block designation register 21 are sent to the memory bus 5 side by controlling the address buffers 14 and 22, respectively. However, it is not limited to this,
The output signals of the address setting switch circuit 15 and the memory block designation register 21 are both supplied to the input side of a selection circuit, and this selection circuit selects one of the output signals by the register set status signal p from the launch circuit 25, and selects the output signal of the selection circuit. The selection signal may be supplied to one address buffer to which the address buffer control signal e from the memory access control circuit 12 is supplied.

Furthermore, in the above embodiment, a case has been described in which the input/output control device 1 is applied as a device using dual port memory, but the invention is not limited to this, and the present invention can also be applied to other devices having dual port memory. Of course, the invention can be applied.

Further, in the above embodiments, a case has been described in which a microprocessor is used as the processor, but the present invention is not limited to this, and it goes without saying that other processors may be used.

〔Effect of the invention〕

As explained above, according to the present invention, in a dual port memory that is connected to a system common bus and is provided in a device containing a built-in processor and that is accessible from both the system common bus side and the internal processor/7 subbus side, , a memory block designation circuit that enables designation from the system common bus side of which block of the dual port memory is to be selected and accessed; A lock circuit is provided that functions only when it is detected that the device to which the memory belongs is in an abnormal state. Under normal conditions, only one block area of the dual port memory can be accessed from the system common bus side. When the device to which the port memory belongs is in an abnormal state, any block of the dual port memory specified by the memory block designation circuit can be accessed, so that the device to which the dual port memory belongs can be accessed. When the device becomes inoperable, the entire area of dual port memory can be accessed from the system common bus side, making it easy to collect device internal information for failure analysis of the device in which the abnormal condition has occurred. The effect is that it can be carried out reliably.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional device. In the figure, 1 is an input/output control device, 2 is a system common bus, and 3 is a system common bus.
is an internal microprocessor bus, 4 is a dual port memory, 5 is a memory bus, 11.16 is an address comparison circuit, 12.17 is a memory access control circuit, 13, 14,
18. 22 is an address buffer, 15 is an address setting switch circuit, 21 is a memory block specification register, 23
24 is a lock circuit, 24 is a register access control circuit, and 25 is a lock circuit.
2 is a latch circuit, 26 is an inverter, 27.28° 29 is an AND circuit, and 30 is an abnormal state detection circuit.

Claims (1)

[Claims] In a dual port memory that is connected to a system common bus and is provided in a device containing a processor and that is accessible from both the system common bus side and the internal processor bus side, the dual port memory is connected to the system common bus in an interface section with the system common bus. A memory block designation circuit that allows you to specify which block of memory to select and access from the system common bus side, and a device that uses the memory block designation circuit to which the dual port memory belongs is in an abnormal state. Under normal conditions, only one block area of the dual-port memory can be accessed from the system common bus side, and when the device to which the dual-port memory belongs is in an abnormal state, A dual-port memory access control method, characterized in that an arbitrary block of the dual-port memory designated by a memory block designation circuit can be accessed.