JPS5958917A - Power-on reset circuit - Google Patents

Abstract

PURPOSE:To prevent surely the malfunction of a digital circuit at the application/interruption of a power supply, by starting the charging of a series connecting circuit comprising capacitors and resistors with the 1st switching circuit turned on at a permissible operating voltage or over, and turning on the 2nd switching circuit when the said capacitor is charged to a prescribed voltage or over. CONSTITUTION:When a voltage of a power supply Vcc is increased with the application of power supply and reaches a prescribed permissible operating voltage VA, the 1st Zener diode is conductive and a transistor (TR)Q1 is turned on. When a charging voltage Vc of a capacitor C1 reaches a prescribed value being the sum between a Zener voltage VZ2 of the 2nd Zener diode D2 and a base-emitter voltage VBE of a TRQ2, the TRQ2, i.e., the 2nd switching circuit is turned on. Since the base of a TRQ3 is grounded with the 1st switching circuit already, the 3rd switching circuit is in a state to be turned on, the power supply Vcc is applied to an output resistor R4 through the 2nd and the 3rd switching circuit, and a power-on reset signal V0 of high level is outputted from a terminal 1.

Description

DETAILED DESCRIPTION OF THE INVENTION 1. Field of the Invention The present invention relates to a power-on reset circuit for preventing malfunctions when turning on and off the power of a digital circuit.

Digital circuit using integrated circuit elements, lI? Microcomputers and the like may need to be reset for a period of time until the clock oscillator, such as a crystal, reaches stable oscillation even after the voltage exceeds a predetermined allowable operating voltage after the power is turned on. The power-on reset circuit is a circuit that continues to reset the digital circuit etc. for a necessary period in such a case.

Conventional technology An example of a conventional power-on reset circuit is shown in FIG.

In other words, a resistor R11 and a capacitor ell are connected to the power supply Vcc.
is connected in series, and a diode D21 is connected in parallel to the resistor Ru, and the photoelectric voltage of the capacitor Co is output from the terminal l and supplied to the target integrated circuit element 2 as a power-on reset signal Vo. do. Integrated circuit element 2
Power supply for operation is supplied from VC when the power supply Vcc is turned on, but in 1 when a power-on reset signal with a reset release voltage of 71 or more is given, the reset state is maintained, and when the reset h is a power on with a release voltage of 78 or more The reset is canceled by ON reset No. 48, and normal operation is performed. The resistor R11 has a high resistance and may be built into the integrated circuit element 2. The conventional circuit described above is
After FVcc is turned on, it is connected to capacitor C1l via resistor R11.
is charged, and when the charging voltage of the capacitor C11 reaches a predetermined level VB, the reset of the integrated circuit element 2 is released. Therefore, as shown in Fig. 2(a), 'l' when the power is turned on.
When the 1lL pressure rise is step-like, the power-on reseller No. 41 Vo resets the predetermined level after a certain period of time determined by the sizes of the resistor R11 and the capacitor C1l after the power is turned on, as shown in the same figure (b). 1 [Removal voltage Vn
It is possible to cancel the reset after exceeding t. On the other hand, the integrated circuit element 2 has a predetermined allowable operating voltage V immediately after the power is turned on.
A voltage of A or higher is being supplied. Therefore, the reset of the integrated circuit element 2 is canceled after a certain period of time has elapsed since the allowable operating voltage vA was applied. Furthermore, when the power is turned off, the charge in the capacitor C1l is immediately discharged through the diode D21, so the integrated circuit element 2 is immediately reset and does not malfunction.

However, the voltage rise and fall of the power supply vcc is shown in Figure 3 (
If the power-on reset signal Vo has a slope as shown in a), the power-on reset signal Vo is connected to the power supply Vcc as shown in (b) and c of the same figure.
The reset release voltage VB may be reached before the voltage reaches the allowable operating voltage vA. In this case, the integrated circuit element 2 is reset during the period X shown in the figure while being supplied with a power supply voltage that is less than the allowable operating voltage of 7 Å, so there is a risk of malfunction.

The same applies to the case where the source is cut at τ. That is, 8
The conventional power-on reset circuit shown in Figure JIJ1 may not serve its purpose.

In order to compensate for the above-mentioned drawbacks, a circuit configured as shown in FIG. 4 is also known. In this case, the voltage of the capacitor C1l in the conventional circuit shown in Fig. 241 is input to the transistor Q□□ base via the Zener diode Dll, the emitter of the transistor Qttit is grounded, and the collector is connected to the power supply Vcc via a resistor. has been done. The collector of the transistor Qu is connected to the base of the transistor Q21, the emitter of the transistor Q21 is grounded, and the collector is connected to the power supply Vcc through a resistor. The collector voltage of the transistor Q21 is output from the terminal l as a power-on reset signal o. 1 in the above circuit
．． Even when the rise of the power supply Vcc is sloped as shown in FIG. Zener voltage V7 of diode Dll and transistor.

11 sum of emitter voltage VTIE Vz + Vnp
: When the transistor Qll is turned on.

Transistor by turning on transistor Qll. 21 is turned off, the above Vz + VBE is the allowable operating voltage v
If it is set to be equal to A, the power-on reset signal ~'0 will always be equal to the power supply v
It will be output after he reaches cc when it reaches VA. Shigashi,
This delay time t varies depending on the rise time of the power supply Vcc, and the longer the rise time, the shorter the delay time t becomes. Therefore, there is a drawback that the minimum value of the delay time t cannot be guaranteed. Furthermore, when the power is turned off,
The discharge of the capacitor C1l starts when the power supply voltage Vz+Vn
p VD (VD Hatai: k -)” D21-1
1@direction voltage), that is, VA -vD, the transistor Q1t continues to be on for a while (during the period X) even after the power supply Vcc falls below the allowable operating voltage A. During this period X, the transistor Q21 is off, so the power-on reset signal V (1 is the fifth
As shown in Figure (c), the voltage is higher than the reset release voltage vB. That is, during one period X, the reset remains released and there is a drawback that malfunction of the integrated circuit cannot be prevented.

OBJECTS OF THE INVENTION An object of the present invention is to eliminate the above-mentioned conventional drawbacks, and to be able to release the reset after a certain period of time from the time when the power supply voltage reaches the allowable operating voltage of the integrated circuit, An object of the present invention is to provide a power-on reset circuit that can be reset immediately when the voltage drops below the voltage level.

A switching circuit of ft'Gl that turns on at a power supply voltage equal to or higher than the value, and a direct connection circuit of a capacitor, a resistor, and a first diode connected in series between the first switching circuit and the power supply; a second switching circuit that turns on when the voltage across the capacitor exceeds a certain value; and a second switching circuit that turns on the first switching circuit.

A third switching circuit that is turned on and off when turned off, and a second diode having a cathode connected to one end of the capacitor and an anode grounded, the second switching circuit, the third switching circuit, and an output. A series connection circuit with a resistor is connected between a power source and ground, and a power-on reset signal is output from one end of the output resistor.

Note that if the voltage of the capacitor is applied to the control input of the second switching circuit via the second Zener diode, it is easy to lengthen the fixed time period in reset 1.

Embodiments of the Invention Next VC1 The present invention will be described in detail with reference to the drawings.

FIG. 6 is a circuit diagram showing one embodiment of the present invention. That is, a series connection circuit consisting of a capacitor C1, a resistor R2, a first diode D3, and the collector-emitter of a transistor Q1 is connected between the power supply Vcc and the ground. The base of transistor Q1 is connected to the power supply Vcc IfC through a resistor R1 and a first Zener diode D1. Zener voltage Vz of first Zener diode D1
1 and the base-emitter voltage VBE of transistor Q1
The sum is set to be equal to the allowable operating voltage vA. Therefore, transistor Q1 is turned on when the voltage of power supply Vcc exceeds a certain allowable operating voltage VA. In this embodiment, transistor Qi + resistor R1
, and a Zener diode D1 constitute a first switching circuit.

Further, the power supply VccK is connected to the emitter of the transistor Q2, and the base of the transistor Q2 is connected to the connection point between the capacitor C1 and the resistor R2 via the second Zener diode D2. The emitter of the transistor Q3 is connected to the collector of the transistor Q2, the collector is connected to the ground through the output resistor R4, and the base is connected to the collector of the transistor Q1 through the resistor R3. 1, the cathode of the second diode p4 is connected to the capacitor C'i
and the end node is grounded. The above transistor Q2
is a second switching circuit, and transistor Q3 is a third switching circuit. In the second switching circuit, that is, the transistor Q2, the charge voltage Vc of the capacitor C1 is equal to the Zener charge voltage Vz2 of the second Zener diode D2 and the emitter-to-emitter voltage VBE of the transistor Q2.

It is in an off state until the voltage reaches 111, and becomes an on state when the voltage exceeds the above voltage. The third switching circuit, that is, the transistor Q3 is in an on state or a state that can be turned on when the transistor Q1 is on, and the transistor Q□
When it is off, it is in the off state. Diode D3
is the polarity that blocks the base current of transistor Q3. Further, the second and third switching circuits and the output resistor are connected in series, and the power-on reset signal Vo is output from one end of the output resistor R4 through the terminal l. It is at a high level only when both the second and third switching circuits are in the on state, and is at a low level when either one of the switches is off.

Next, the operation of this embodiment will be explained with reference to FIGS. 6 and 7. FIG. 7(a) shows the voltage of the power supply Vcc,
The figure (b) shows the charging of the capacitor C1, the voltage Vc,
FIG. 4C is a time chart showing the power-on reset signal Vo. First, when the power is turned on, the voltage of the power supply Vc rises as shown in FIG. 7(a), and when it reaches a certain allowable operating voltage vA, the first Zener diode becomes conductive and the transistor Q1 is turned on. Sunawaji.

The fAl switching circuit turns on. Due to this.

Charging of the capacitor C1 is started, and the charging voltage Vc of the capacitor C1 increases as shown in FIG. 7(b). This voltage is the Zener voltage V of the second Zener diode D2.
7.2 and the base-emitter voltage VI of transistor Q2
When the short value, which is the sum of IE, is reached, transistor Q2, that is, the second switching circuit is turned on.

On the other hand, since the base of the transistor Q3 is already grounded by the first switching circuit, the third switching circuit is in a state where it can be turned on, and the power supply Vcc tri
, is applied to the output resistor R4 through the second and third switching circuits, and is applied from terminal 1 to FIG. 7(c) vcjr;
A high-level power-on reset signal Vo is output. The delay time t until the voltage of the capacitor C1 turns on the second switching circuit is 'power supply Vc
Although it depends on the rising speed of c, it is determined by the capacitance and resistance of capacitor C1, the resistance value of capacitor C1, the Zener voltage Vz2 of the 20th Zener diode D2, etc. Therefore, this delay time is % The minimum value is when Vc is applied in a stepwise manner. Therefore, if this let small delay is 1!, and lto is set to D[a constant value, a delay time greater than to can be obtained. The 4゛♂i circuit (not shown) provides an acceptable operating type output voltage of more than s
Since the system is reliably reset for a certain delay time to after the water is supplied, there will be no malfunction. In addition, when the power is turned off, 18. The output is shown in Figure 7 (a
), when the allowable operating voltage VAt falls, the transistor Q1 turns off and the base current of the transistor Q3 is cut off, so the transistor Q3 also turns off. Therefore, the /war-on reset signal Vo immediately becomes a low level as shown in FIG. This completely prevents malfunctions of the integrated circuit. On the other hand, the transistor Q2 has a power supply Vcc of Vcc.
Z2+VBE VD (VD is tie, t-)-D4
17) It continues to be on until it descends to IIIQ direction 'KJf) and then turns off. Further, the electric charge of the capacitor C1 is discharged through the diode D4, and the voltage Vc of the capacitor C1 becomes 0 as shown in FIG. 4(b). The same figure (d) shows the above-mentioned operating transistor Q, 1=
Indicates the on/off state of Qa.

FIG. 8 shows a modification of the above embodiment, in which resistors L are connected between the emitters and bases of transistors Q1 to Q3 in FIG.
? In this case, the first Zener diode D1, the second Zener diode 1)
This has the advantage that the transistor Q1=Qa is prevented from being turned on due to leakage current of the transistor Q2 or the transistor Q1, and the switching operation can be performed more reliably.

The 91st page 1 is a circuit diagram showing a second embodiment of the present invention. This is a circuit in which a resistor Rs is inserted in series with the transistor Q3 and resistor R4 shown in FIG. In this case, if the resistor ζB is selected so as to ensure that the level of the terminal 1 after the reset is released is the TTL'1 level, the power consumption of the rank X terminal Q21Q3 can be reduced.

FIG. 10 is a circuit diagram showing a third embodiment of the present invention, and the difference from FIG. 6 is that the second Zener diode D2 is not included. It can be applied when the time that the power supply must continue to be reset after reaching the permissible operating voltage is relatively short. Figure 8, 4
The same effect can be obtained even if the second Zener diode D2 in the diagram L9 is deleted.

Effects of the Invention As described above, in the present invention, charging of a series connection circuit of a capacitor and a resistor is started by the first switching circuit which turns on the power supply when the voltage is higher than the allowable operating voltage, and the capacitor is charged to a voltage higher than a certain voltage. and a third switching circuit which turns on the second switching circuit when the first switching circuit is turned on, and which is controlled to be turned on or turned on when the first switching circuit is turned on, and which is turned off when the first switching circuit is turned off. The second. Since the series connection circuit of the third switching circuit and the output resistor is configured as a C-type circuit connected between the power supply and the ground, when the power is turned on, the power supply can remain constant after reaching the allowable operating voltage. In other words, it is possible to reliably prevent digital circuit malfunctions when the power is turned on and off at 1fJi.1. It has a soothing effect.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an example of a conventional reset circuit, Figs. 2 and 3 are waveform diagrams of various parts showing an example of the operation of the above conventional example, and Fig. 4 shows another conventional example. Circuit diagram, 5th
The figure is a waveform diagram showing the waveforms of various parts of the conventional example shown in Fig. 4, Fig. 6 is a circuit diagram showing the first embodiment of the present invention; Fig. 15 waveforms, time chart showing 1 hour operation, etc., Fig. 8 &i circuit diagram showing a modification of the first embodiment, Fig. 9. FIG. 7 is a circuit diagram showing a third embodiment. In the figure, l...terminal 2...integrated circuit element Q
1=Q3...Transistor Dl...First Zener diode D2...Second Zener diode D3.1) 4...Diode C1...Capacitor R1~], L3...Resistance ...Output resistance Rs~□Rs...Resistance Vcc...Power supply V
c... Charging of capacitor t 115. Voltage Vo: Power-on reset signal ■A: Allowable operating voltage Vz
1. Vz 2...t, the same] and Zener voltage of the second Zener diode V,... Reset release voltage ■BE... Transistor base-emitter voltage ■]... Forward voltage of the diode. Agent Patent Attorney Resident 1) Toshi Soka 2 Figure 3 Flute 4 Figure %JcC Figure 5 t-7 Tonarii! / Tokon Meditation 1 Lit
Fig. 6 Fig. 8 Fig. 7 Fig. 9 cc

Claims (1)

[Claims] (1) A first switching circuit whose one end is grounded and which is turned on by a power supply voltage of a certain value or more that is input through a Zener diode, and a capacitor, a resistor, and a resistor connected in series between the first switching circuit and the power supply. a first series connection circuit of diodes, a second switching circuit that is turned on when the voltage across the capacitor is equal to or higher than a certain value, and a third switching circuit that is turned on and off when the first switching circuit is turned on and off. circuit, and a second diode having a cathode connected to one end of the capacitor and an anode grounded, the series connection circuit of the second switching circuit, the third switching circuit, and the output resistor is connected between the power supply and the ground. A power-on reset circuit, characterized in that the power-on reset signal is output from one end of the output resistor. (2. In the power-on reset circuit according to claim a1, the voltage across the capacitor is applied to the control input of the second switching circuit via a second Zener diode. thing.