JPS58133035A - Power-on resetting circuit - Google Patents

Abstract

PURPOSE:To reset assuredly a digital circuit for a fixed time regardless of the rise time of a power supply, by detecting that the power supply voltage is equal to the allowable working voltage and then detecting a fixed subsequent time with the forward voltage of a constant voltage diode and a transistor. CONSTITUTION:The emitter of a pnp transistor TRQ2 is connected to the power supply voltage VCC; the collector of the TRQ2 is grounded via a resistance R2; and the base of the TRQ2 is connected to the VCC via a constant voltage diode D2 and a capacitor C1. Then the collector of an npn TRQ1 is connected to the joint between the capacitor C1 and a diode D2 via a resistance R1; and the emitter of the TRQ1 is grounded. Furthermore the base of the TRQ1 is connected to the VCC via a resistance R3 and a constant voltage diode D1. Then the allowable working voltage VA of the VCC is detected by a circuit consisting of a diode D1, the TRQ1 and the capacitor C1, and a fixed subsequent time (t) is detected by the forward voltage of the diode D2 and the TRQ2. Thus a reset signal is delivered assuredly through a reset terminal 1 and for a fixed time.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a reset circuit, and more particularly to a power-on reset circuit that prevents malfunctions when power is turned on or off in a digital circuit.

Digital circuit using integrated circuit elements, 4IK! With the power-on reset circuit of Italo computers, there are cases where it is necessary to continue resetting the clock oscillator, such as a crystal, for the time required for stable oscillation when the power supply is within tolerance.

In cases like Jin, traditionally the number one! A circuit like the one shown in IK was used. When a step power source W@e as shown in Fig. 2 is applied to this circuit, the conductor tcz
When VCE reaches the allowable operating voltage ■m, it continues to be reset for a further time t〇However, if a ramp-like VCC as shown in Fig. 3 is applied, There is a drawback that before Vcc reaches the allowable operating voltage YAK, the charging line to the capacitor CWt exceeds the reset release voltage Vi+ inside the integrated circuit element, and the reset is eliminated.

In order to compensate for this drawback, a table circuit as shown in FIG. 4 has been proposed. This circuit uses the reset release voltage as the zener voltage VDII of the constant voltage diode 0 and the transistor Qt.
t is summed with the pace-emitter voltage VBx t 1 This is set so that it is similar to the Kll capacity operating voltage 1 as shown in Fig. 5, and the capacitor C is connected through the resistor R11.
By taking advantage of the fact that the charging of Vce is delayed before the rise of Vce, the reset is always released after Vce reaches Vm.

However, in this circuit, the time t until Vcc reaches the allowable operating voltage M and the top of ffl IJ is released is VCC.
It depends on the start-up time, and the longer the start-up time υ, the shorter t becomes.

Furthermore, vcc is the pace-emitter voltage Vn of Qzt.
Until zzt is reached, the output transistor Qz1 cannot be turned on and the reset terminal 1 cannot be pulled to TTL10 level, so the integrated circuit element and the transistor Qx
If VB (VBK *s) occurs due to variations in t, there is a drawback that the reset is momentarily released at the rise and fall of Vce. By starting to charge the capacitor after the voltage reaches the voltage, the above drawback is solved, and a reset time longer than a certain time can be secured regardless of the startup time of the power supply VeC.In addition, collector-follower type PNP transistor amplification The purpose of the present invention is to provide a power-on reset circuit in which the reset output is taken from the collector of the circuit so that the reset output remains at the TTL "0" level during the rising period of Vce.

In order to achieve the above object, the power-on reset circuit according to the present invention includes a collector follower type PNP (PNP) transistor amplifier circuit whose other end of a collector resistor is connected to ground, and a capacitor whose one end is connected to a power supply and whose anode and the other end are grounded. The collector follower type PNP is connected to the cathode of the diode connected to the collector follower type PNP through a constant voltage diode or directly
) connected to the pace of the transistor, and the other end of the collector resistor was connected to this connection point, the emitter grounded plane NPN) transistor amplifier circuit, one end connected to the pace of the transistor (NPN), and the other end connected the cathode to the power supply and a resistor connected to the anode of the second constant voltage diode.

According to the above configuration, all the above-mentioned problems are solved and the object of the present invention is completely achieved.

Hereinafter, the present invention will be explained in more detail with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a power-on reset circuit according to the present invention.

In the figure, C2 is a transistor whose emitter is connected to the power supply Vcc, and R2 is a resistor connected between the collector and ground of transistor Q2.
P) A transistor amplifier circuit is formed. Ql is a transistor whose emitter is connected to ground, R1 is a resistor connected to the collector of transistor Q1, and together they form a transistor amplifier circuit.

C1 is V. C and a capacitor connected to the other end of resistor R1, D3 connects its anode to ground and its cathode to resistor R
This is a diode connected to the other end of 1.

A constant voltage diode 8 is inserted between the connection point of these 1Ct XRt 1Ds and the space of the transistor Ql.

In addition, a constant voltage diode Dth whose mocha electrode is connected to VCC between the pace of the transistor Q1 and the power supply VCC
, a series circuit of resistors R3 is inserted.

FIG. 7 is a waveform diagram for explaining the operation of this embodiment circuit.

When a power supply voltage VCC as shown in the figure is applied, the pace voltage of the transistor Qs also increases as the voltage increases. However, since the constant voltage diode Dl is connected in series, the transistor Q1 is cut off until the sum of the Zener voltage VDt of the diode D5 and the base-to-emitter voltage VBKI of the transistor Q1 is reached.

Therefore, since the capacitor fct is not charged during this period, the transistor (h) is also cut off, and the reset output vo is TTL since the resistance value of the resistor - is sufficiently small.
Continue to maintain “O”.

Power supply voltage V (IC2>' is ') K increase L te, VDI + V! III When the voltage increases, the voltage of pace Ka and VBII of the transistor Q1 is applied, so the base current flows through the resistor FLS and the constant voltage diode D1, and the transistor Q1 turns 1 on.

At this point, the capacitor C1 starts to be charged through the resistor, and the voltage Vo t' across KCI gradually rises.

However, as in the case of the transistor Ql, since there is a constant voltage diode D2, the transistor Q2 is cut off until the sum of the Zener voltage VD2 of the diode D2 and the base-emitter voltage VBII of the transistor Q1 is reached.

Therefore, during this period t, the reset output vo is “0”
Continue to maintain the level.

Note that this period is the shortest when tds Vcc is applied in a stepwise manner, and in this case t=set t.

If is set to the design value, no matter how the power supply rises, it is possible to continue reliably resetting for at least a period t after reaching the allowable operating voltage VAK.

Next is the charging voltage of capacitor C1. , is VDI +Vn
When it reaches zs, the charging voltage ■c凰 is ramped up by 7, and the voltage of VBII is applied to the pace of the transistor Q@, so that the pace current flows through the constant voltage diode D, and the transistor Q1 through the resistor R1. flows to transistor Q
! is turned on. As a result, the reset output vO is raised to the power supply voltage Vccl and the reset is released.

Next, a case where the power supply VCC is turned off will be described.

Vmuz VDI + VaNtz VDI + vB
Since zz + Voxss K is selected, the power supply voltage V
When OO falls to below V, the transistor Q1 cuts off, and at the same time the charge stored in the capacitor CIK is discharged through the diode Ds, and as a result, the transistor Q cuts off, and the reset output V becomes a.
It will be reset to 0 level.

! FIG. 8 is a circuit diagram showing a second embodiment of the present invention.

In this example, transistors Q1 and Q! of the configuration shown in FIG.
This is a circuit in which resistors R4 and Rs are added between the base and emitter, respectively.

If the resistor R4P%B-s is provided in this way, the power supply voltage Vo
.

It is possible to prevent the transistors Cb and Qz from turning 1-on-1 due to the leakage current of the constant voltage diodes Ds and D when the voltage is below Vm, and to ensure the switching operation of the transistors Ql and Qz. can.

FIG. 9 is a circuit diagram showing a third embodiment in which a resistor R- is further inserted between the collector of the transistor Q2 of the second embodiment and the resistor R/).

The resistor Rρ is selected so as to ensure that the level of the output terminal 1 after the reset is released is the T T L I 1g level.

In this way, the collector current of the transistor Q2 is limited, so that in addition to ensuring reliable switch operation, the power consumption of the transistor Q2 after the reset is released can be kept low. (Fig. 10 is a circuit diagram showing a fourth embodiment of the invention, in which the voltage regulator diode D2 is removed from the configuration of Fig. 6.1) In this example, after the power supply reaches the allowable operating voltage, This method can be applied when the time t required to continue resetting is relatively short.

In this embodiment as well, as in the case of Fig. 6, the resistors R4-Rh FLs can be added as shown in Figs. 8 and 9, and thereby the same effect as Fig. 8.9 can be obtained. It will be done.

As explained in detail above, the present invention detects when the power supply voltage reaches the allowable operating voltage with the forward voltage of the second voltage regulator diode and transistor, and then detects that the power supply voltage reaches the allowable operating voltage by the forward voltage of the second voltage regulator diode and transistor. By detecting the forward voltage or the forward voltage of the transistor, after the power supply is within tolerance, regardless of the power supply startup time,
This has the effect that the digital circuit can be reliably reset for a certain period of time.

[Brief explanation of the drawing]

@Figure 1 is a circuit diagram showing an example of a conventional reset circuit, Figures 2 and 3 are waveform diagrams of various parts of the circuit in Figure 1 when the rise time of the power supply voltage is changed, and Figure 4 is a circuit diagram of a conventional reset circuit. 5 is a waveform diagram of each part of FIG. 4, FIG. 6 is a circuit diagram showing one embodiment of the power-on reset circuit according to the present invention, and FIG. 7 is a circuit diagram showing another example of the reset circuit of the present invention. The waveform diagram of each part in FIG. 6 and FIGS. 8 to 10 are circuit diagrams showing other embodiments of the present invention. vA... Allowable operating voltage V of the integrated circuit element... Reset F release voltage inside the integrated circuit element VCC... Power supply voltage vo... Reset output terminal voltage VOI % vo 11... Capacitor C1, CI Voltage across both terminals Q = 1Q1t, C21...NPN) transistor Q1...PNP) transistor Dl, 1) 2, Dll... constant voltage diode D3...
・Diode C1, CIOs C1l "" Capacitor R1~as,
Rxs...Resistor 1...Reset terminal 2...Integrated circuit device patent applicant NEC Corporation

Claims (1)

[Claims] The other end of the collector resistor is connected to the ground (nine collector follower type PNP) transistor amplifier circuit, one end of which is connected to the power supply, the other end of the capacitor whose anode is connected to the ground, and the cathode of the diode is connected via a constant voltage diode, or
or directly connected to the base of the collector-follower type PNP) transistor, and the other end of the collector resistor is connected to this connection point. and a resistor connected to the anode of a second constant voltage diode whose cathode is electrically connected.