JPS5957543A - Data transmitting system - Google Patents

Abstract

PURPOSE:To control the loop access with a comparatively simple circuit, by controlling the right of data frame transmission of a node with a token, and controlling the switching of transmission/receiving with a repeat instruction. CONSTITUTION:The information from a loop 3 is converted into 1, 0 of TTL level in an electrooptic/optoelectric converting section 5 and transmitted to a pattern check circuit 12 in serial. The circuit 12 checks the separator pattern or the like. When a free token is detected at a token detecting circuit 13, the process to acquire the token is performed. When serial information from the circuit 12 is fully inputted to a receiving shift register 16, the information is transmitted to a buffer register 17. The content of a shift register 17 is transmitted to a transmission shift register 22 on the condition that a repeat command signal REPT is at logical 1. When the signal REPT is at logical 0 and a signal VSDT instructing the frame transmission is at logical 1, the data on a transmission data bus SBUS is transmitted to the register 22, and the data from the register 17 is blocked.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention connects a plurality of data relay devices in a ring shape using an information transmission medium, and exchanges information between terminals connected to a data relay LQW via an adapter. This relates to a data transmission method that performs.

[Conventional technology and problems]

FIG. 1 is a diagram showing an outline of a data transmission system, and FIGS. 2 and 3 are diagrams showing a transmission format.

In Figure 1, 1 is ADP (adapter), 2 is JJJ
X (Jangkunyong Box Data Relay Device), 3
is a loop, 4 is an interface line, 5 is a terminal, and N is a node. In the local area network, each node N is connected in a shilling manner by a loop 3. loop 3
is made of a transmission medium that flows bit-serial in the ] direction, and coaxial cables, optical fibers, etc. are used as transmission media. Each node N has JBX2, ADPl,
A terminal 5 and the like are included, and a JBX 2 is provided at the joint between each node N and the loop 3. Information exchange between arbitrary nodes N is performed from the terminal 5 via the ADP 1 and the JBX 2 by sharing the transmission medium of the loop 3. JBX2 has a repeat function, that is, a function to send the received information to the immediately adjacent node, and a function to branch the received information to ADP 1 of each node.
It also has a function to load the data on loop 3 by sending the data to JBX2. Generally, a frame placed on loop 3 is composed of several bytes. FIG. 2 shows the transmission format of the token frame, and FIG. 3 shows the format of the data frame. F is a separator pattern indicating the start or end of a frame, Ac1d access control section, SA is a source address section, Fe2
indicates a frame check sequence, a DAH destination address field, LC indicates a link control section, an IH information section, and a time fill pattern packed between TI4 frames.
Indicates that the frame is outside the area. In this way, the seven-letter pattern F is attached to the beginning and end of each frame as a separator turn, and the beginning of the frame is recognized by the separator pattern F at the beginning. The last separator pattern F indicates the end of the frame.

Therefore, the same pattern as separator pattern F must not be included in the frame, for example, in the data pattern, or if the pattern is simply created, the separator pattern
There may be cases where the same pattern as pattern F is included in the frame. In order to prevent this, the commonly used conventional method is to set the beginning and end of the 8-bit configuration to ``0'' as separator pattern F, and to set all the middle 6 bits to ``1''. Patterns other than separator pattern F are o
Staff ink (stuff 0). the result,
The same pattern as separator pattern F with 6 consecutive bits of "1" will no longer be mixed in with other patterns, but in the end if there is a pattern with 6 or more consecutive bits of "]", it will be followed by 5 bits "]". Next, an O-stuff ink operation is performed to stuff "0" bits, which causes the disadvantage that the length of the frame is not in bytes and changes, making the operation complicated. In addition, when loop 3 is configured using optical fiber as a transmission medium, AGC (Automatic Ga1nContv) is installed on the receiving side.
ol: automatic gain control) function, but if "0" or "1" continues for more than a certain number of bits, the AGC will not operate stably, and the level judgment function of rOJ and "1" will deteriorate. [Objective of the Invention] The present invention solves the above problems by providing a separator pattern that can be easily distinguished from other patterns, and a relatively simple circuit that can control loop access. Another object of the present invention is to provide a data transmission method that can guarantee stable operation of the AGC function.

[Structure of the invention]

To this end, the data transmission method of the present invention includes a plurality of adapters, a plurality of data relay devices connected to each of the plurality of adapters, and a transmission medium that connects the plurality of data relay devices in a ring shape, In a data transmission system in which information is exchanged between arbitrary nodes by sharing a medium, the data relay device has a transmission mode and a reception mode, and also has a buffer for storing an input bit sequence, an oscillator, and an oscillator. at least means for converting or repeating the input bit sequence stored in the buffer into an output bit sequence according to the output of the oscillator, and token control means for controlling the data frame transmission right of the node using a token. , the adapter and the data relay device change from the reception mode to the transmission mode upon acquiring a token under the control of the token control means, stop the operation of the repeat means, and stop the operation of the token control means. The present invention is characterized in that it is configured to change from a sending mode to a receiving mode upon sending out a token under control, and perform a process of operating the repeating means. Further, the data transmission method of the present invention includes a plurality of adapters, a plurality of data relay devices connected to each of the plurality of adapters, and a transmission medium that couples the plurality of data relay devices in a ring shape, the transmission medium In a data transmission system in which information is exchanged between arbitrary nodes by sharing the At the time, a 9-bit start pattern, 9-bit data pattern ¥n sets, and a 9-bit end pattern are sent out in sequence, and when data is received, the information between the start pattern and the end pattern is transmitted in sequence. is received as a data frame.

The above data pattern is such that the 9th pit is the complement of the 7th bit or another specific odd numbered bit, and
The pattern and the end pattern are characterized in that the 9th pit has the same value as the 7th bit, and the fill pattern is not configured in a pattern in which all bits have the same value.

[Embodiments of the invention]

Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 4 is a diagram showing one embodiment of a data relay device to which the present invention is applied, and FIG. 5 is a diagram showing a detailed example of the AC section of the transmission format. In FIG. 4, 5 is an EOloE (electrical-optical/optical-electrical) converter, 6 is an SP/PM3 (serial-parallel/parallel-serial) converter, and 7 is an OE converter.
Conversion circuit, 8 is EQL circuit, 9 is AGC circuit, 10 is F
l” circuit% 11 is a clock extraction circuit, 12 is a pattern check circuit, J3 is a token detection circuit, 14 is a frame detection circuit, 15 is a reception counter, 16 is R8R (reception shift register), 17 is BR (buffer)・Register), 18-digit OR circuit, 19 and 20 are AND circuits, 2
1-digit inverter, 22-digit 5sI (shift register for high-speed transmission), 23-digit transmission counter, 24 is a transmitter,
25 indicates an EO conversion circuit. EO10Eg exchange part 5,
An optical signal is received from the loop 3 to the OE conversion circuit 7, and the optical signal is converted into an electrical signal. The converted electrical signal is sent to the EQL circuit 8 and outputs either a logic "1" signal or a logic "0" signal.
A determination is made as to whether it is a signal. The electrical and mechanical signals output from the OE conversion circuit 7 are gain controlled by the AGC circuit 9. When logic "1" or logic "0" is output from the EQL circuit 8, that output is set in the FF circuit 10, and
The clock extraction circuit 11 extracts a clock from the output, and the clock is used as the pattern check circuit 12 of the FF circuit LO1sP/PS converter 6. Token detection circuit J
3. Complaint detection circuit 14, reception counter 15, BSR
Used as clock for I6 and BRI7. FF
The contents set in the circuit 10 are sent to the pattern check circuit 12 by the clock. The data sent out from the 5SR 22 of the S P/PS converter 6 is converted from a TTL level electrical signal to an optical signal by the EO converter circuit 25 and placed on the loop 3. ADPJ to JBX2
Token request signal RQ as an interface signal to
TKN is supplied to the token detection circuit 13, a repeat instruction signal REPT is supplied to the AND circuit 19 and the inverter 21, a transmission instruction signal VSDT is supplied to the AND circuit 20, and the transmission data is supplied to the AND circuit 20 through the transmission data bus 5I3US. Supplied. Also, from JBX2 to AD
As an interface signal to Pl, reception instruction signal VR
DT is sent out from the frame detection circuit 14, reception strobe signal 1 (STB) is sent out from the reception counter 15, and transmission strobe signal 5STB is sent out from the transmission counter 23.
The received data is sent out from the output terminal of the OR circuit 8 through the receive data bus. The token request signal RQTKN instructs ADPl to obtain a token when there is data to be transmitted.The token controls which node has the transmission right for the loop, and it is used to control the token. The acquired node can send data. As explained earlier with reference to FIGS. 2 and 3, the separator pattern F comes at the beginning of the frame, followed by the access control section AC. 5
As shown in the figure, a frame indicator bit FI is provided to indicate whether the frame is a data frame or a token frame. Then, the token frame is provided with a beep (TK) for displaying the token. One of the bits representing the token is e.g.
” indicates that the token is busy and there is a node that already has the token, and a logic “0” indicates that it is a free token and is ready to acquire the token. There is a bit. Next, an overview of the operation of the SP/PS converter 6 will be explained. E.O.
In the 10E converter 5, the information from the loop 3 is converted into TTL level rlJ and rOJ, and 1! “FIO to 1
When the bits are serially sent to the turn check circuit 12, the pattern check circuit 2 recognizes the separator pattern F and performs other frame checks. In the token detection circuit 13, when the token request signal RQ'I'KN is logic "]", a free signal is detected.
It is detected whether it is a token or not, and when a free token is detected, processing for acquiring the token is performed. That is, Fu IJ
−・When it is a token, set the bit to logic “1”
to make it a busy token and set the bit indicating token acquisition to logic ``1''. Its contents are transferred from the OR circuit 18 to the received data bus BUSf, A
I) P l is notified. The frame detection circuit 14 detects the received frame and sends the reception instruction signal VRDT to A.
Send to DPL. 17S]6 stores the serial information from the pattern check circuit 12, and when it is full, parallels it and sends it to H1t17. The contents of BRI 7 are ORed with the output of token detection circuit 18 and sent to ADPl via receive data bus RBUS.
Reception instruction signal VRD instructing to receive a frame
It is sent to the 5SR22 on the condition that T is logic "1" and the repeat instruction signal REPT, which instructs to execute the repeat function, is logic "1". Further, when the repeat instruction signal REPT is logic "0" and VSDT, which instructs to transmit a frame, is logic "1", the mode is set and the data on the transmission data path 5BUS is transmitted through the AND gate 20. Sent to 5SR2,2, BRI7
Data from is blocked.

The reception counter 15 counts the reception clock extracted by the clock extraction circuit 11 and sends out the reception strobe signal R8TB as the set timing of the reception byte. The transmission counter 23 counts the clock of the oscillator 24 and outputs the reception strobe signal R8TB. 5STB is sent as the set timing for the transmission byte. The serial data set in the 5SR 22 is converted into serial data according to the clock of the oscillator 24 and sequentially sent to the EO conversion circuit 25.

In ADP 1, when a data transmission request occurs, when the mode signal (not shown) indicates the transmission mode, or if the mode signal indicates the reception mode, the token request RQTKN is set to logic "1" and the transmission is performed. When the mode changes, the transmission strobe signal 5STBK is synchronized, the transmission instruction signal VSDT is set to a logical month, and the transmission data is sequentially placed on the transmission data battle bus 5BUS, so that the elapsed time in the transmission mode becomes a constant value. However, when there is no longer a data transmission request, a token frame made into a free token is sent and the repeat instruction signal REPT is set to logic "1".
S of the data relay device so that it transitions to reception mode.
A process of instructing the P/PS converter 6 is performed.

Further, in the present invention, a fill pattern and an inverted bit addition method are used to ensure that the AGC always operates stably. That is, a node that has the right to transmit transmits a fill pattern consisting of repeating 01'' while not transmitting a node.The data pattern includes 9 bits plus the 7th bit (or other specific odd number). The complement of υ, "0" or "1" can be kept to a maximum of 8 bits, and stable operation of the AGC can be guaranteed. Furthermore, the same value as the seventh bit is used for the ninth bit in the separator pattern. When transmitting a data frame, a 9-bit separator pattern, a 9-bit data pattern, and a 9-bit data pattern are transmitted in sequence.
When the pattern to be transmitted is a separator pattern, the same value as the 7th bit should be packed into the 9th bit, and when it is a data pattern, the inverted value of the 7th focus value should be packed into the 9th bit. Compared to the 0-stuff ink operation, a simple operation for every 8 bits is required, and the circuit is also simplified. Also, at the receiving node, the separator
The information between the patterns is received as a data frame, but the data pattern does not include a separator pattern, and the 7th and 9th bits are
By doing so, the separator nozzle and the data nozzle can be easily distinguished, and the identification circuit is also simplified. Since a frame is constructed in units of 9 bits in this way, the length of the frame does not vary as is the case with 0 stuffing operations, and it is also possible to have 8 or more consecutive bits of the same value. It becomes.

As mentioned above, the token frame or data frame starts with a separator turn,
It is ensured that no additions or subtractions are made to the frame's focus during the passage of Freno after recognizing the separator pattern. This is done by initializing the receive counter 15 and the transmit counter 23 each time a separator pattern is recognized, and by adjusting the time with the BRI 7 for bit shifts during frame passing.

Since there is some error in the oscillator 24 placed in each JBX, the input bit rate of the JBX differs from the output bit rate. In the transfer time of a fixed amount (71, bits) of input bits, there are output bits at n,→-8.

The relationship is as follows, where R is the accuracy of the oscillator. The accuracy of the oscillator is R2O, 7X10-', and the maximum amount of data transfer is (
4KB+20B)X-=37.044 bits,
The bit shift Δl is 1Δn l = 37.044X0.
7xlO-'=2 bits.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the data frame transmission right of a node is controlled using a token, and the switching between transmission and reception is controlled using a repeat instruction, so a relatively simple circuit can be used to loop the data frame.・Access can be controlled. Further, according to the present invention, a frame is constructed in units of 9 bits, the content packed into the 9th bit of the separator pattern and the data pattern is changed, and the pattern is arranged so that the same value does not continue for 8 bits or more. This ensures stable operation of the AGC and facilitates pattern identification.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an overview of a data transfer system, FIGS. 2 and 3 are diagrams showing examples of transmission formats, and FIG. 4 is a diagram showing an embodiment of a data relay device to which the present invention is applied.
FIG. 5 is a diagram showing a detailed example of the AC section of the transmission format. 1...ADP (adapter), 2...JBX (data relay bag, 3...loop, 4...interface line,
5... EOloE (electrical-optical/optical-electrical) conversion section, 6
...SP/PS (serial-parallel/parallel-serial) conversion section, 7...OE conversion [! 21st road, 8・
...EQL circuit, 9...AGC circuit, 10...FF
Circuit, 11... Flock extraction circuit, 12... Pattern check circuit, 13... Token detection circuit, 14
... Frame detection circuit, 15 ... Reception counter, 1
6...R2H (reception shift register), 17...
・BR (buffer register), 18...OR circuit,
19 and 20...AND circuit, 21...Inverter,
22... Transmission shift register, 23... Transmission counter, 24... Oscillator, 25... EO conversion circuit.

Claims (3)

[Claims] (1) A plurality of adapters, a plurality of data relay devices connected to each of the plurality of adapters, and a transmission medium that connects the plurality of data relay devices in a ring shape are provided, and the transmission medium is shared and any In a data transmission system in which information is exchanged between nodes, the data relay device has a transmission mode and a reception mode, and also has a buffer for storing an input bit sequence, an oscillator, and an input bit sequence stored in the buffer. repeating means for converting the pit sequence into an output bit sequence according to the output of the oscillator; and token control means for controlling the data frame transmission right of each node using a token;
The adapter and the data relay device change from the reception mode to the transmission mode on the condition that a token is acquired under the control of the token control means, stop the operation of the repeat means, and control the token control means. A data transmission method characterized in that the data transmission method is configured to change from a transmission mode to a reception mode on the condition that a token is transmitted at the bottom, and to perform a process of operating the repeating means. (2) As interface signals from the adapter to the data relay IT, a 1-bit token request signal instructs to request the transmission right and a 1-bit repeat instruction signal to instruct the release of the transmission right.
Transmission instruction signal bit and transmission data indicating the validity of the bit and transmission data! 1 bit, and as an interface signal from the data relay device to the adapter, includes 1 bit of a reception instruction signal indicating the validity of received data, 1 bit of an injury timing signal, 1 bit of a transmission timing signal, and n pits of transmission data, When a data transmission request occurs to the adapter, it sends a transmission instruction signal in synchronization with the transmission timing signal, provided that it is in transmission mode, or if it is in reception mode, it turns on the token request signal and then enters transmission mode. Turn on the repeat signal to sequentially load the transmission data onto the transmission data bus, and then turn on the repeat signal and send the above data on condition that the time elapsed in the transmission mode reaches a certain value or there is no longer a request to send d data. Data transmission method b according to claim 1, characterized in that the data transmission method b is configured to instruct the relay device to shift to reception mode KM. (3) A plurality of adapters, a plurality of data relay devices connected to each of the plurality of adapters, and a transmission medium that connects the plurality of data relay devices in a ring shape, and the transmission medium can be shared and used as desired. In a data transmission system that now exchanges information between nodes, a data relay device repeats a '01' fill-in while not transmitting data.
When transmitting data, send n sets of a 9-bit start pattern, a 9-bit data pattern, and a 9-bit end pattern, then send l1li', and when receiving data, combine the above start pattern and the above. Information between the end pattern and the start pattern is received as a data frame, and the 9th bit of the data pattern is the complement of the 7th pit or another specific odd numbered bit, and A data transmission system characterized in that the end pattern has a ninth pit having the same value as the seventh bit, and the fill pattern has a repeating pattern of '01'.