JPS573153A - Fault detection system - Google Patents

Fault detection system

Info

Publication number
JPS573153A
JPS573153A JP7617380A JP7617380A JPS573153A JP S573153 A JPS573153 A JP S573153A JP 7617380 A JP7617380 A JP 7617380A JP 7617380 A JP7617380 A JP 7617380A JP S573153 A JPS573153 A JP S573153A
Authority
JP
Japan
Prior art keywords
line
monitor device
break
clock break
receiver
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7617380A
Other languages
Japanese (ja)
Other versions
JPS6349946B2 (en
Inventor
Naruhiro Hayashi
Hisashi Morikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7617380A priority Critical patent/JPS573153A/en
Publication of JPS573153A publication Critical patent/JPS573153A/en
Publication of JPS6349946B2 publication Critical patent/JPS6349946B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring

Abstract

PURPOSE:To detect faults in the system rapidly and efficiently by a monitor device, by causing respective devices to be monitored to report faults of themselves to the monitor device spontaneously. CONSTITUTION:When power break occurs in a node ND 3, clock break is detected by a receiver 1 in the LA 4 side in an ND 4, and its information is reported to an input/output signal control part 7, and a corresponding pattern is generated there and is written in both buffer memories 3 and 4 in the LA side and the LB side. The contents of buffer memories 3 and 4 in the LA side and the LB side are read out by various transmission clocks and are transmitted to respective transmission lines of the LA 5 and the LB 4 by transmitters 5 and 6. In an ND 2, a bit pattern corresponding to detected clock break of the receiver in the LB 3 side is transmitted to the LA 3 and LB 2 similarly. A monitor device SV detects that communication with the ND 3 is impossible on a basis of information of clock break of the LA line of the ND 4 received from the LA line and clock break of the LB line of the ND 2 received from the LB line.
JP7617380A 1980-06-06 1980-06-06 Fault detection system Granted JPS573153A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7617380A JPS573153A (en) 1980-06-06 1980-06-06 Fault detection system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7617380A JPS573153A (en) 1980-06-06 1980-06-06 Fault detection system

Publications (2)

Publication Number Publication Date
JPS573153A true JPS573153A (en) 1982-01-08
JPS6349946B2 JPS6349946B2 (en) 1988-10-06

Family

ID=13597693

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7617380A Granted JPS573153A (en) 1980-06-06 1980-06-06 Fault detection system

Country Status (1)

Country Link
JP (1) JPS573153A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5957543A (en) * 1982-08-26 1984-04-03 Fujitsu Ltd Data transmitting system
JPS5980042A (en) * 1982-10-29 1984-05-09 Toshiba Corp Loop transmitter
JPS59221052A (en) * 1983-05-31 1984-12-12 Nec Corp Data transmission equipment
JPS6072355A (en) * 1983-09-28 1985-04-24 Fuji Facom Corp On-line off-line detecting system
JPS636934A (en) * 1986-06-26 1988-01-12 Nec Corp Network synchronizing system
US7940057B2 (en) 2007-08-23 2011-05-10 Fanuc Ltd Method of detecting disconnection and power discontinuity of I/O unit connected to numerical controller

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS516603A (en) * 1974-07-06 1976-01-20 Sumitomo Electric Industries DEETATSUSHI NHOSHIKI
JPS52136505A (en) * 1976-05-11 1977-11-15 Oki Electric Ind Co Ltd Automatic fault restoration system for loop transmission system
JPS5336104A (en) * 1976-09-16 1978-04-04 Hitachi Ltd Trouble discrimination equipment in loop-type data transmission system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS516603A (en) * 1974-07-06 1976-01-20 Sumitomo Electric Industries DEETATSUSHI NHOSHIKI
JPS52136505A (en) * 1976-05-11 1977-11-15 Oki Electric Ind Co Ltd Automatic fault restoration system for loop transmission system
JPS5336104A (en) * 1976-09-16 1978-04-04 Hitachi Ltd Trouble discrimination equipment in loop-type data transmission system

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5957543A (en) * 1982-08-26 1984-04-03 Fujitsu Ltd Data transmitting system
JPS5980042A (en) * 1982-10-29 1984-05-09 Toshiba Corp Loop transmitter
JPH0572142B2 (en) * 1982-10-29 1993-10-08 Tokyo Shibaura Electric Co
JPS59221052A (en) * 1983-05-31 1984-12-12 Nec Corp Data transmission equipment
JPS6072355A (en) * 1983-09-28 1985-04-24 Fuji Facom Corp On-line off-line detecting system
JPS636934A (en) * 1986-06-26 1988-01-12 Nec Corp Network synchronizing system
US7940057B2 (en) 2007-08-23 2011-05-10 Fanuc Ltd Method of detecting disconnection and power discontinuity of I/O unit connected to numerical controller

Also Published As

Publication number Publication date
JPS6349946B2 (en) 1988-10-06

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