JPS59221052A - Data transmission equipment - Google Patents

Abstract

PURPOSE:To form automatically a whole system into a loop again and to detect a faulty point by switching both input and output to their queuing systems when the break of a signal or a specific pattern is detected and at the same time storing the break of signal. CONSTITUTION:When the using 1st loop system transmission line is disconnected; a photoelectric converting circuit 30 of said transmission line converts a data line 52 into a signal all 1. In reply to this signal, a transmission line control circuit 32 outputs an interruption signal to a signal line 82. Then a processor 33 reads the status stored in a memory part 34 in response to said interruption signal. In response to this reading action, it is understood that the processor 33 is connected to the 1st loop system. Thus the processor 33 transmits the information showing the clock break to the circuit 32 together with data and a write pulse. The supply of data is inhibited to the 1st loop system transmission line in response to those data and pulse. At the same time, the 1st loop system transmission line is switched to the 2nd system transmission line. Furthermore, the status showing this state is stored to a memory part 34.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a data transmission device that performs loop switching in a loop data transmission system.

In conventional loop data transmission systems, two transmission lines are sometimes installed to transmit signals in opposite directions, taking into account failures in the transmission lines. Generally, only one transmission line is used, and in response to a failure in the currently used transmission line, the other transmission line is used.

Conventionally, this type of loop switching is called a "mask control station" or "sezuta station," and in response to the identification of a clock signal interruption, a special command is sent to the mask station through the standby system, and the mask station separately This has been done under the control of a special control device, such as switching between each station, using wired circuits (
・Ru. In this type of system, there is a possibility that the occurrence of a failure in the special control device may develop into a non-fatal failure, and there is a drawback that an extra special line is required.

In another system, when a mask control station detects an abnormality in a loop-shaped transmission path, it transfers frames in order from itself to recover.

However, if the mask control station goes down, it is completely useless (there is a drawback).

Purpose of the Invention An object of the present invention is to automatically reconfigure a loop between certain data transmission devices when a failure occurs in the active transmission path or in both the active and standby transmission paths. An object of the present invention is to provide a data transmission device capable of detecting in which section of a loop-shaped transmission path a failure has occurred.

Structure of the Invention The device of the present invention is a data transmission system that includes a pair of loop-shaped transmission paths having an active system and a standby system, and a plurality of data transmission devices connected to this transmission path. 5 pupil-separate detection means for at least one of identifying a disconnection of the signal from the operational loop transmission path and detecting a specific pattern indicating that the signal disconnection has been detected; and the operational loop transmission. In response to at least one of the interruption of the signal on the line and the reception of the specific pattern, the additional pattern is sent to the active loop transmission line, and both input and output are on standby.

a switching means for switching to the active loop transmission line; and a switching means for switching to the active loop transmission line in response to invalidation of the signal on the standby loop transmission line, switching the input side to the active loop transmission line and switching the output side to the standby loop transmission line to enter a loopback state. a connection means for connecting as a signal, a transmission means for transmitting the specific pattern to the output side in response to the invalidation of the signal on the input side after the loopback state, and a transmission means for detecting a signal disconnection in the operational loop transmission line. and means for storing the detected information in response.

Embodiment of the Invention Next, an embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, the system to which the present invention is applied is comprised of transmission devices 1-4, first loop-based transmission lines 11-14, and second loop-based transmission lines 21-24.

While operating as a normal system, the first loop system 1
Using transmission lines 1 to 14, the second loop system 21 to 24
The transmission line is in a bypass state (・ru).

Referring to FIG. 2, one embodiment of the present invention includes a first photoelectric conversion circuit 30. Second opto-electrical conversion circuit 31゛The clock signal is transmitted after opto-electrical conversion.
1. Data 1tR52 that transmits data after photoelectric conversion
and 62. Transmission line control circuit 32, loop system transmission line 11
Clock lines 54 and 64. which transmit clock signals for sending out signals to υ and υ・2■. a data line 5 for transmitting data to be sent to the loop system transmission lines 1 and 12;
5 and 56. Control signal lines 56 and 66 that transmit control signals for separately controlling the first and second photoelectric conversion circuits 30 and 31, respectively, and a processor 33 that performs microprogram control. Storage unit 34. take bus 8
1. Interrupt signal line 82. A signal line group 83 that transmits control signals for controlling the transmission line control circuit 32 and the storage unit 34
．． Address line 84 of storage unit 34. A write pulse line 85 for writing data into the storage section 34. A write pulse line 86 for writing data to the transmission line control circuit 32. A reset signal line 316 that provides a mask reset signal. Data is sent to the loop system transmission line 11 or 21 (・Request signal line 87 transmits a transmission signal that turns on, signal line 88 transmits an interrupt signal when a specific frame is detected. It consists of a signal line 89 that transmits an interrupt signal when the signal is input.

Referring to FIG. 3, the transmission line control circuit 32 of FIG. 2 includes the clock signal disconnection detection circuit 91. A transmitter/receiver circuit 92 that controls data from or to the loop system transmission line. Decoder 93. Clock generation circuit 94. Flip-flop 101 indicating that transmission to the first loop transmission path is possible. Flip-flop 201 indicates that transmission to the second loop-based transmission path is possible, and flip-flop 1o2 . Flip-flop 202, which indicates that reception from the second loop transmission path is possible. Flip-flop 70 tube 103 for instructing bypass to the first loop transmission line; flip-flop 203 for instructing bypass to the second loop transmission line. (・Signal line 301 that sends out a clock detection signal indicating signal detection; Output signal line 32J that sends out the output signal of flip-flop 102; Output signal line 322 that sends out the output signal of flip-flop 202; Clock; A clock signal line 315 that provides an internal clock from the generation circuit 94.
Signal lines 317 and 318 . that provide signals generated from decoder 93 . Serial data line 311, reception clock line 312. and an AND circuit 401 (.

Referring to FIG. 4, the clock signal disconnection detection circuit 91 of FIG. 3 detects the flip-flop 110. The flip-flop 114/ and the flip-flop 124, which indicate a clock signal disconnection transitioning from a connected state to an unconnected state, determine whether the input data of the loop system transmission line continues to have a logical value of "1" until it reaches the value of the constant TO. Counter 111 for identification. Acceptable state flip 70 of knob 102 or 202 (constant T1 unless counter 111 detects the value of constant TO when either is on)
Counter 112 continues counting until the value of
A counter 113 that continues counting until it reaches a value of 2. When the connection state flip-flop 110 is on, the counter 123 continues counting until it reaches the value of the constant T3.
Clock signal 315. providing an internal clock. A reset signal line 316 that provides a mask reset signal. Signal lines 317, 319, . NAND circuit 402, OR circuit M40
3. and a receiver 411.

Referring to FIG. 7, it is a general shape of a frame applied to the present invention, and F is a flag pattern '011111
10', DA indicates the destination address, SA indicates the source address, C indicates control information, ■ indicates data information (sometimes abbreviated), and Fe2 indicates the frame This is a cyclic redundancy check bit used to check whether the frame was transferred correctly in the check sequence.

Referring to FIG. 8, in the status information stored in the storage unit 34, bit +01 is connected to the first loop transmission line, bit +11 is connected to the second loop transmission line, and bit 12' is loopback A. (In this embodiment, the receiving side is connected to the first loop-based transmission line, and the transmitting side is connected to the second loop-based transmission line.) Bit +31 is connected as loopback B (in this embodiment, the receiving side is connected to the second loop-based transmission line). The second loop system transmission line, the transmitting side is connected to the first loop system transmission line (・U), bit 14" detects a signal disconnection on the first loop system transmission line and a beep) This shows that a signal disconnection is detected in the loop system transmission line (2).

Next, the operation of one embodiment will be explained in detail. In the normal state, the first loop transmission lines 11 to 14 are used. (·Ma,
Assume that the first loop transmission line is used. In the data transmission device 1, a transmittable flip-flop 101. A receivable flip-flop 102 for the first loop transmission path. A bypass flip-flop 203 for the second loop system transmission line is set, and when the signal on the output signal line 301 of the clock signal disconnection detection circuit 91 is turned on (.
Ru. In addition, the other data transmission devices 2 to 4 in Figure 1 are in the same state as the transmission device 1, and are connected to the first loop system transmission path. ,
If the first loop transmission line 14 is disconnected in this state, the first opto-electric conversion circuit 30 of the first loop transmission line in the data transmission device 1 sets the data lines 52 to all l.

In response to the signal applied via this data line 52,
An interrupt signal is sent from the black/red signal disconnection detection circuit 91 to the signal line 82.
is output to. In response to the interrupt signal applied via the signal line 82, the processor 33 reads the status shown in FIG. 8 stored in the storage section 34. In response to this read operation, it learns that it is connected to the first loop, and sets status bit 4 in FIG. 8 to indicate that the first loop system is down. Processor 33Fi sends data and write pulses via data bus 81 and write pulse line 86. In response to these data and write pulses, the transmittable flip-flop 101 and the receiveable flip-flop 102 for the first loop transmission line are activated.
are turned off, and the data of all O is made to flow to the first loop system transmission path (a pattern different from the pattern caused by the transmission path disconnection is made to flow).

At the same time, the transmittable reserve flop 201 for the second loop transmission path is turned on, and the bypass 7 lip-flop 203 is turned off. At this time, since the signal on the transmission request signal line 87 is in the on state, the transmitting/receiving circuit 92 continuously sends a pattern (a valid signal) in which the clock signal is not interrupted to the loop system transmission line. After a predetermined time has elapsed, the reception enable flip-flop 202 for the second loop system transmission line is turned on, and the processor 33 goes to check the signal on the clock detection signal line 301 that is the output of the clock signal disconnection detection circuit 91. . On the other hand, allo transmitted to the loop-shaped transmission line 11
The pattern is received by the data transmission device 2 and provided to the transmission/reception circuit 92 via the opto-electric conversion circuit 30 in FIG. 1 and the clock interruption detection circuit 91 in FIG. The transmitter/receiver circuit 92 responds to the signal applied via the data line 52 to the clock signal disconnection detection circuit 91 and receives the interrupt signal from the signal line 71.
is output to. The processor 33 learns that a clock interruption has occurred on the loop-shaped transmission path. Furthermore, the processor 33 of the data transmission device 2, in response to the detection of a date interruption in the data transmission device 1, sets bit 4 of the status to If the clock signal is cut off on the transmission line 224-t (the clock signal cutoff detection is set to bit 4 of the status), exactly the same operation is performed. As a result, when the processor 33 of the data transmission device 1 tries to detect the signal output from the clock detection signal line 301, it is in the on state, so the contents of the bypass 7 lip-flop 103 corresponding to the first loop system are in the on state. After that, the first loop system is switched to the second loop system, and the eighth loop system is switched to the second loop system.
By resetting the status pinto O in the figure and setting bit 1, the status indicating that the second loop-shaped transmission line is connected is stored in the storage unit 34. In this way, the clock interruption propagates to allO up to the data transmission device W4, and the process ends with switching to the second loop system transmission line. Referring to FIG. 5, the loop system transmission line 14 is disconnected 1.
-The final status in case of
In order to
It turns out that there was an abnormality. A method for detecting abnormalities in the loop-shaped transmission paths and data transmission devices of the entire system is to use the data transmission device 3 as the device that monitors the loop, and to monitor each data transmission device at predetermined intervals. It is good to set the command frame for reading the status information in the format shown in FIG. 7 (referred to as an R8TS frame in this embodiment). Therefore, when the R8TS frame is transmitted to each data transmission device, the signal on the receiver 6 side of each data transmission device is applied to the reception buffer of the transmission/reception circuit 92 via the clock disconnection detection circuit 91, and
3 by an interrupt signal output from the signal line 89. Therefore, the processor 33 can read the contents of the reception buffer via the data bus 81 and the signal line group 83, and in response to a status read request from the data transmission device 3, the status stored in the storage unit 34 can be read. It will be done.

Destination address information DA in frame format according to Figure 8
, first address information SA, and status information are written to the transmission buffer of the transmitting/receiving circuit 92 in the order of (・control information C, 8 bits of status) I, and the transmission request signal line 87 is input. By turning on the signal, it converts from parallel to serial and outputs the photoelectric conversion circuit 30 or 3.
1, the frame is sent to the data transmission device 3. In the data transmission device 3, when a frame is given to the reception buffer of the transmission/reception circuit 92, the processor 3
3 by an interrupt signal output from signal line 89. As a result, the processor 33 connects the data bus 81 and the signal line group 8
3, the contents of the receive buffer can be read from each data transmission device, and by knowing that a response frame for the 1'CS T S frame has come from each data transmission device, and further reading the status, the loop transmission line and each data transmission device can be read. Know about abnormalities. In addition, the method of detecting an abnormality in the loop-shaped transmission path and data transmission equipment of the entire system is to send the data transmission equipment 3 that monitors the loop money to the data transmission equipment 3 after a predetermined period of time when each data transmission equipment detects a clock disconnection. (Time that takes into account disturbances in the loop-shaped transmission line due to loop switching)
In this method, the processor 33 reads the status stored in the storage unit 34 and sends it to the data transmission device 3 in a frame structure according to FIG. The method in which each data transmission device reads the status stored in the storage unit 34 and notifies the data transmission device 3 that monitors the loop) is the same as the procedure shown in the other method above.

Next, if both transmission lines 14 and 21 are disconnected (in the case where The operation of the data transmission device 4 is due to the transmission line 21 being disconnected.
When the processor 33 detects the signal on the clock detection signal line 301, it is turned off. Therefore, the receivable flip-flop 202 corresponding to the second loop system is turned off, and the first loop system The receivable flip-flop 102 corresponding to the first loop system is turned on and the signal on the clock detection signal line 301 is about to be detected.At this time, the data transmission device Nl~ corresponding to the first loop system
3 is in a bypass state, the clock signal is cut off (. Therefore, if the signal on the clock detection signal line 301 of the data transmission device 4 is off (.) , the processor 33 turns off the transmittable flip-flop 201 for a certain period of time, and returns it to the on state after a certain period of time.
Bit 0 of the status shown in the figure is reset, bit 2 is set, and status information is stored in the storage unit 34. That is, the data transmission device 4 receives the first loop system, and receives the second loop system.
In a loopback state with the loop system on the transmitting side, a clock signal interruption is caused in the transmission line 24 for a certain period of time according to the summer I/O pattern. Then, the processor 33 of the data transmission device 3 detects the on state of the interrupt signal line 88 due to the interruption of the clock signal, sends an all 0(7)' turn to the second loop system transmission line, and transmits the data on the data bus 81. and the pulse of the write pulse line 86, the transmittable 7 rip-flop 201 and the receiveable 7 rip-flop 2 corresponding to the second loop system are activated.
02 is turned off, and all
Let Q pattern data flow. Next, the transmittable flip-flop 101 corresponding to the first loop system is turned on, and the bypass flip-flop 103 is turned off. At this time, since the signal on the transmission request signal line 87 is in the off state, the transmitting/receiving circuit 92 does not have a clock signal cut off (.
Patterns began to be sent continuously over the line (・ru.

After a predetermined period of time has elapsed, the content of the receivable flip-flop corresponding to the first loop system is turned on, and the processor 33 detects the signal on the clock detection signal line 301 that is the output of the clock signal disconnection detection circuit 91. go. However, an allQ pattern flows through the loop transmission line 23 (
・In order to
The same operation is performed. Therefore, the loop system transmission line 12 is not interrupted by the clock signal. Therefore, the processor 33 of the data transmission device 3 uses the clock detection signal line 30
When I went to detect the signal No. 1, it was in the on state, so I turned on the content of the bypass flip-flop 203 corresponding to the second loop system, and transferred the signal from the second loop system to the first loop thread. At the same time, bit 1 of the status shown in FIG. In this way, the clock signal based on the alIQ pattern is sequentially propagated to the data transmission device 1 on the second loop system side as well, and the transmission line is switched to the first loop system transmission line. Since the transmission line 14 was disconnected until the operation of the data transmission device fHi l, when the processor 33 of the take transmission device 1 went to detect the clock detection signal line 3010, it was in the off state (. .therefore,
The receivable flip-flop 102 of the first loop system is turned off, the receivable flip-flop 202 corresponding to the second loop system is turned on, and the signal on the clock detection signal line 301 is detected. At this time, in the data transmission devices 2 and 3, the first loop system is in the connected state, the second loop system is in the bypass state, and the data transmission device 4 is in the loop state. The clock signal is output to the first loop system side, and a pattern in which the clock signal does not break continuously flows in the order of the digital transmission device → 2 → 3 → 4 → l.

As a result, the four detection signal lines 30 of the data transmission device 1
1 signal is turned on (.) Therefore, the processor 33 of the data transmission device 1 resets bit 1 of the status, sets bit 1. bit l-3, stores the status in the storage section 341, and ends the process. That is, data transmission device 1
enters a loopback state in which the second loop system is the receiving side and the first loop system is the transmitting side. Therefore, each status information%
By knowing this, you can find the cut point.

The method of knowing is the same as when the transmission line 14 is disconnected.

FIG. 5 shows the final state when the loop transmission lines 14 and 21 are disconnected. Next, the clock signal disconnection detection circuit 9
1 will be explained in detail. Now, when the receivable flip-flop 102 is set, the signal on the signal line 3'21 is turned on, and the input from the first photoelectric conversion circuit 30 is transmitted via the lines 52, 51° receiver 411 and the Nant gate 402. The counter 111 receives data and an input clock.
works. Counter 111 is photoelectric conversion port 1! g30
The counter continues counting in response to a logic value "1" of the input data from the counter, is reset in response to a logic value "0", and generates a pulse in response to the counter value [TOJ.

On the other hand, the counter 112 starts counting because the signal on the ready state signal line 321 becomes active (・).
When the value of the counter 111 becomes TO or the connection state flip-flop 110 is set, the counter 11
2 is reset. The value of counter 112 is "'1"
When it hits IJ, it generates a pulse. In addition, the connection state flip-flop 110 is connected to the counter 112 (ifjr'l
'lJ. Therefore, by turning on the signal on the clock detection signal line 301, which is the output of the 7-lip-flop 110, the processor 33 is informed of the connection state of the loop system transmission line. When the connection state flip-flop 110 is set and the internal clock 315 is applied, if the input data is a logical value "1", the counter 11
3 counts. The counter 113 is reset in response to the logic value "0" of the input data. Eventually counter 1
In response to the value "T2" of 13, the clock signal off flip-flop 114 is set. That is, after the connection state flip-flop IJ70 is set, all 1
It is determined that the clock signal 1gi has been generated if the pattern continues for a time of "T2x (period of the internal clock)". The input signal turns on and informs the processor 33 of the occurrence of a clock signal disconnection.After the flip-flop 110 is set, the counter 123 counts if the input data is one logical value. Logical value of "1"
is reset in response to Counter 123 is "T3"
If the input data of logical value "1" comes in until the value of "T3" is reached, the clock type flip-pun loop 124 is turned on. After 110 is set, it is determined that a clock signal disconnection has occurred because the pattern of a and IIO is "T3x (period of internal clock)", so it is determined that a clock signal disconnection has occurred.
In response to the setting of 4, the interrupt signal on the signal line 71 is turned on, and the processor 33 is notified of the occurrence of the clock signal disconnection. In the explanation of FIG. 4, the counter 13 counts when the input data is a logical value "1", but if the opto-electrical conversion circuit directly detects a fault and there is a signal that is turned on during that time, If this signal is used as input data and a slight change is made, the counter 113 operates in the same manner as described above.

Next, FIG. 6 shows a block diagram in which the number of successive logic values "l" falls within TO as a pattern (signal is valid) when the clock signal is interrupted, and will be explained below. . Reference numeral 511 is a line for a clock that provides a clock for transmission, reference numeral 501i1 is a count line, reference numeral 513 is a line that outputs 1 bit of the count value,
Reference numeral 502 indicates a selector, and reference numeral 512 indicates a line which transmits a pattern in sequence with the interruption of the clock signal at the output of the sector. Now the senctor 502 is the value of the line 513 "
In response to the count value "l" on the line 513, the output signal line 5 is fully outputted to the output signal line 512.
11' is output to 12. Therefore, if a clock signal is constantly applied to the counter 501 via the clock signal line 511, a continuous pattern can be generated repeatedly.
This is a circuit in which the number of "1" is within a constant TO number.

The operations of each data transmission device described above correspond to the operations shown in the flowchart of FIG. Clock reception in FIG. 7 means that the received signal is valid. However, when considering the opto-electric conversion circuit 30, bypass means that when the signal on the bypass signal line 56 is on, the signal on the transmission clock line 54. This means that the input signal of the opto-electric conversion circuit 30 goes out as an output signal in a loop shape, ignoring the transmission data line 55. Note that in the above example, the reception clock line 51 and reception data line 52 are valid even during bypass. In addition, patterns may occur due to abnormality detection due to failures in opto-electric conversion circuits, and loop switching or loops may occur due to failures in data transmission equipment connected upstream of the transmission line or intentional occurrence of specific patterns other than the above examples. It is clear that back and failure detection is also included in the present invention.

Effects of the Invention The present invention has a feature that when a signal interruption or a specific pattern is detected, a specific pattern different from the signal interruption is sent to the active system, and both input and output are switched to the standby system, and if the signal interruption is detected, the signal interruption is detected. By memorizing this, the entire system can be automatically re-looped and the location of the failure can be automatically detected.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a loop transmission system to which the present invention is applied, FIG. 2 is a diagram showing an embodiment of the present invention, and FIG. 3 is a diagram showing an example of the transmission line control circuit of FIG. 2. FIG. 4 is a diagram showing an example of the clock signal disconnection detection circuit in FIG. 3, FIGS. 5 and 6 are diagrams showing a loop-shaped transmission system after implementing the present invention, and FIG. 7 is a diagram showing an example of the clock signal disconnection detection circuit shown in FIG. FIG. 8 is a diagram showing the format of status information indicating the connection status and failure information of the data transmission device applied to the present invention, and FIG. A diagram showing a part of the circuit and FIG. 10 are diagrams for explaining the operation of an embodiment of the present invention. In Fig. 1 to Fig. 10, 1 to 4... Data transmission device, 11 to 14, 21 to 24... Transmission line, 30° 31...・Photoelectric conversion circuit, 5i,
52.54~56,61°62.64~66.71.8
1~89,301,311,312゜315~319,
321, 322, 511-513...Signal line,
32...Transmission path control circuit, 33--...Processor, 34...Storage section, 91...
Clock disconnection detection circuit, 92...--Transmission/reception circuit, 9
4...Clock generator, 101 to 103, 20
1~203,110,114,124...Flip-flop, 111~113,123,501...
...Counter, 401-403-...Gate,
411...Receiver, 502...Selector. /4 / Zuth / Figure σq Live? Diagram # 5 Live Lips, 5 Diagram Door 5 Otsujishiba 8 Diagram 2 Omyo q Da

Claims (2)

[Claims] (1) In a data transmission system equipped with a pair of loop-shaped transmission paths having an rl, − system and a standby system, and a plurality of data transmission devices connected to this transmission path, identification detection means for at least one of identifying a signal disconnection from a transmission line and detecting a specific pattern indicating that a signal disconnection has been detected; and a switching means for switching to at least one of the reception of the specific pattern, and a means for storing the detection in response to the detection of a signal disconnection in the operational loop transmission line. data transmission equipment. (2) identification and detection means for at least one of identifying a signal disconnection from an active loop transmission line and detecting a specific pattern indicating that a signal disconnection has been detected; In response to at least one of the interruption of the signal and the reception of the erection pattern, the specific pattern is sent to the active loop transmission line, and a loop transmission line is sent to the output side of the standby loop transmission line. The data transmission device connected downstream identifies the disconnection of the signal and transmits a signal, and after an arbitrarily set period of time, responds to the validity of the signal on the standby loop transmission line and disconnects the standby loop. means for switching both the input and output of the loop-shaped transmission line and using the switched transmission line as the loop-shaped transmission line of the active system; connection means for switching the output side to the loop-shaped transmission line and connecting it in a loopback state by switching the output side to the standby loop-shaped transmission line; A data transmission device comprising: sending means for sending out a pattern; and means for storing the detection in response to the detection of a signal disconnection in the operational loop transmission line.