JPS5846099B2 - Common line access control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to data communications, and more particularly to frames (e.g.
The present invention relates to a common line access control method for controlling the addition/dropping of signal sequences constituting a frame in a bilevel data link control procedure (HDLC or a frame similar thereto) onto a common line.

Recent developments in data communication have changed from communication between terminals and between computers using the conventional basic transmission control procedure.
Computer-to-computer communication using a frame format transmission control procedure (HDLC) with a bit transparent range has become more sophisticated and has become a computer network, requiring a different method to access the data lines connecting these. becomes.

That is, the control of contention seen in the conventional branching method between a computer and a plurality of terminals has been performed based on, for example, a basic transmission control procedure (polling method).

On the other hand, in HDLC, for example, a frame structure as shown in FIG. 1 is adopted (F: flag, A: address field, C: control field, ■: information field,
e2; frame check sequence), the address field A in this field contains the destination station address, and since each frame can be sent to a different destination, the line can be used as a highly efficient frame multiplexed line. Available.

Information frames (I frames) that also contain information messages
has a transmitting sequence number and a receiving sequence number in the control field C, and without confirming reception for each frame. For example, if the sequence number follows modulo 8,
The sender can look ahead up to seven frames, and the receive sequence number indicates the next frame number to be received in the frame sent in the opposite direction, so that the previously received frame has been correctly received. You can notify things all at once.

Such continuous transfer can improve transmission efficiency.

Therefore, in HDLC, if the conventional polling method in the basic transmission control procedure in which one polled station occupies the line is used, the transmission efficiency will be reduced and the above-mentioned advantages of continuous transmission will not be utilized.

Another conventional technology is a control station (primary station) as shown in Figure 2.
When connecting a control station and multiple slave stations (secondary stations) with a single circular data line and controlling transmission between the control station and slave stations using 5DLC (or HDLC), a special GA polling method is proposed for line access control. has been done.

As shown in Figure 3, this involves a special polling signal frame (polling frame) from the control station, followed by a special GA pattern (0111111
1) is sent out.

For example, when there is a request for a transmission frame to slave stations 2 and 3 in FIG. 2, FIG. 3 shows a situation in which a polling frame from the control station makes one round through the slave stations.

Since there is no request for a transmission frame in slave station 1, the polling frame + GA pattern passes through ■, and when slave station 2 receives it, it looks at the polling frame and uses the subsequent GA pattern as the HDLC frame flag (F pattern; 01111
110), insert a transmission frame (X), add a GA pattern at the end, and send it to the next slave station 3.
.

Similarly, for slave station 3, change the GA pattern to the visible F pattern and insert the transmission frame after this (Y), and finally
Send it to slave station 4 with pattern A attached (■).

In this way, the control station receives the polling frame at the beginning, the transmission frame from slave station 2, the transmission frame from slave station 3, and the frame sequence with the GA pattern attached at the end.■)
In one round of polling frames, all the slave stations requested by the transmission frame are polled at once.

However, this method has the following drawbacks.

(b) HDLC requires a special polling frame and a special GA pattern.

(b) Each station requires extra control processing or control circuits such as polling frame identification, GA pattern detection and transmission, and changing from GA pattern to F pattern.

(c) For the slave station and line after passing the GA pattern, the polling frame goes through one cycle and the control station receives the frame string. Until the last GA pattern is received, the line is idle and there is no inter-frame inter-frame on the common line. This increases the amount of free space available, reducing line efficiency.

Therefore, the present invention aims to improve the above-mentioned drawbacks of the prior art.The purpose of the present invention is to effectively utilize the line from the HDLC procedure and its frame structure. Another object of the present invention is to provide a common line access control system in which transmission frames are inserted into and sent out on the line without requiring a control circuit for detecting, identifying, and creating them.

A feature of the present invention that is distantly related to this objective is that in a control method when a plurality of devices access a common line,
Each device includes a detection circuit that detects the end of a signal frame on the line or an empty state, and a first-in, first-out type buffer memory that stores transmitted signal frames.
an insertion circuit that sends a transmission signal frame to the line, and the transmission signal frame accumulated in the buffer memory is transmitted through the insertion circuit when the end of the signal frame on the line or an empty state is detected by the detection circuit. A common line access control method is used for signals sent from the line during transmission, except for signals addressed to the own station, which are stored in the buffer memory and then sent to the line.

Examples will be described below with reference to the drawings.

FIG. 4 is a state diagram A for explaining the concept in detail of the present invention.
- Indicated as E.

Here, 1 represents a line, and frames A, B, C, and D are successively sent to the input.

P represents a branch/insertion point for the common line, and 9 is a first, in, first, out mechanism that temporarily stores transmission frames, inserts transmission frames, and sequentially stores frames sent from outside during transmission. −
(in-first-out) stack memory.

5 is a logic circuit that detects the end of the frame flowing from point P to point 1, that is, the end flag (F pattern), or that the data channel is empty; it detects the end flag when the stack memory of 9 is being stored. Sets the transmit frame insertion sign.

11 is the source of the transmission frame.

The operation will be explained according to state diagrams A-E.

A transmission frame (X) occurs in state diagram A;11.

State diagram B: 9 sees the empty state and transmits the frame (X) to 11
~9 and waits for transmission.

State diagram C;5 detects a frame break on the data channel, ie, the end of B frame flag, and sets a transmit frame insertion sign.

State diagram D: When 5 sets the insertion sign, the branch/insertion operation at point P is started, and (X) frames from 9 are inserted into the output of 1 through point P, and frames C and D flow from 1 to point P. are sequentially accumulated in 9 via line t.

In the state diagram E'', 9 transmits frames C and D, and when there is no stored data and the state becomes empty, 5 also resets the insertion sign, and the branching and insertion operations at point P are stopped.

Thus, the present invention provides logic circuitry and a first, in, first, out mechanism for detecting termination patterns or empty conditions without running special frames and bit patterns on the data channel for contention control. An extremely simple device configuration consisting of a memory stack and add/drop circuit makes it possible to send out transmission frames on a data channel.

Next, FIG. 5 shows an example of a configuration for realizing the present invention.

1a is the input of the frame multiplex line, 1b is the output, 2 is the HD
The LC frame receiving circuit performs frame synchronization using the flag pattern on the line, and the data in the frame is
It outputs bits in parallel and deletes "O" from the data.

3 receives parallel data in units of 8 bits in an HDLC frame transmission circuit, inserts tt On into data other than the flag pattern on the line, and transmits the data.

Reference numeral 4 denotes a speed absorption buffer memory that absorbs a slight difference between the data transfer speed within the station and the data reception speed from the line.

Reference numeral 5 denotes a pattern detection circuit which detects the flag pattern and the idle state of the line.

6 is a flip-flop for an insertion flag, and T is a flip-flop for a transmission request flag.

8a. 8b is a selection circuit that switches the input to A-+B based on flag 7; 9 is a stack memory (FIFO) having a first, in, first, out mechanism;

10a, 10b, and 10c are AND gate circuits; 11 is a transmission frame generator that generates a transmission frame; 12 is a logic circuit that detects a local station's lost address from the address field of the received frame; and 13 is a flip-flop for a local station's failed address flag. , 14 is a local station dropped frame receiving device.

The operation in FIG. 5 will be explained.

When the stack memory 9 is empty, the insertion flag 6 is reset, and the selection circuits 8a and 8b are in the A state, so the frame on 1a is received by 2 and transferred to the buffer memory 4 in 8-bit units. , and if the frame is not a frame lost by the own station according to the output of 4, the gate circuit 10b is opened and the frame is passed through the selection circuit of 8a.
The signal is transferred to the transmission circuit of 1b and sent out to the line 1b.

Seeing that the insertion flag of 6 is reset when a transmission frame is generated in the transmission frame generator of 11,
The transmission frame is transferred to the stack memory of 8b.

When the transfer to 9 is completed, 11 sets the transmission request flag of 7.

At this time, since 9 is not in the empty state, the reset of the flags 6 and 7 has been canceled.

When a frame break or empty state is reached on 1a, 5
The detection circuit detects the termination flag or the empty state from the output of 4 and sets the output to 1.

Since the flag 7 is set (1), the flag 6 is set via the gate 10a.

When flag 6 is set, selection circuits 8a and 8b select B.
The data transfer path of 2-4-10b-8a-3 is switched to 2-4-10b-8b-9, and valid signal strings to other devices are sent on 1a. (excluding columns), they are stored in 9 sequentially.

Further, the data stored in 9 is sent out to 1b via the data transfer path 9-8a-3, and the outgoing frame generated in 11 is inserted and sent out on 1a.

When 2 no longer receives frames and all the data stored in 9 has been transmitted, 9 becomes empty, the flags 6 and 7 are reset, and the data transfer path is changed to 2-4-10b.
- Return to 8a3.

In this way, the outgoing frame generated at 11 is
The frame is multiplexed and inserted into the frame.

Further, 12 and 13 detect the address field of the own station dropped frame on 1a from the output of 4, and when it is the own station address, set the output to 1 and set the own station dropped flag of 13.

This forms a path of 2-4-2-4-1O,
The frame dropped by the own station is transferred to 14.

On the other hand, 2-4-10b8a-3 or 2-4-10b-
The transfer path of 8b-9 is inhibited by 10b, and this interframe period is treated as an empty state.

In this empty state, if there is still data to be sent in 9,
It will be absorbed when you leave 1b.

Flag 13 detects the end of frame flag by 5 and is reset.

In this way, the flag and idle detection on the line in the method of the present invention is not a special function for the present invention;
This is an essential function for HDLC data communication, and in addition, it also has first, in, first, and out functions.The memory stack has been highly integrated using current integrated circuit technology, so the present invention This is realized with an extremely simple configuration.

The access control method of the present invention, which is realized with such a simple configuration, provides the following various advantages and usage effects for various data communications using HDLC.

(1) Extra control signals for access control are not sent onto the line, and as soon as a frame break or idle state is detected, access is possible without the need for contention control with other devices, making the line extremely efficient. Can be used for

(2) Only when a frame for another device arrives on the line during frame insertion, the signal string on the line is 9(7)F I
Since the data is drawn into the FO, the frames on the line are closed, increasing line efficiency, and at the same time, the FIFO is quickly made available, thereby shortening the waiting time for requests to send outgoing frames.

(3) Branch type data communication using conventional HDLC and G
In data communication using A-polling, only the unbalanced mode has been used in which the control station always sends commands and the slave station responds after confirming receipt of the commands, but in the present invention , all stations are
A balanced mode can also be used in which commands and responses can be issued equally without distinction between control stations and slave stations.

(4) By using the above balance mode, arbitrary n:n communication (exchange) is possible by using a circular common line for multiple parties as shown in Figure 2 and specifying the destination station address in the address field. It is.

This effect enables all operation modes for data communication using HDLC, and provides a very effective means for packet exchange using HDLC.

As can be seen from the above description, according to the present invention, access control when sending frame-configured information from multiple devices onto a common line is facilitated, and frame multiplexing in data communication using time-division transmission channels is facilitated. It can be applied as an access control method to a common path connecting multiple processors and input/output devices.

[Brief explanation of drawings]

Fig. 1 is an example of the HDLCO frame configuration, Fig. 2 is a block diagram of a system that uses the conventional GA polling method, Fig. 3 is a diagram for explaining the method in Fig. 2, and Fig. 4
E is a diagram for explaining the basic concept of the present invention, and FIG. 5 is a block diagram showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Common line, 2...HDLC frame receiving circuit, 3...HDLC frame transmitting circuit, 4...Buffer for speed absorption, 5...Pattern detection circuit, 6...Flip-flop for insertion flag 7...Flip-flop for transmission request flag, ga, 8b...Selection circuit, 9
... FIFOl 10a, 10b -AND gate, 11... Transmission frame generator, 12... Own station dropped frame detection circuit, 13... Flip-flop for detection flag of own station dropped frame, 14... - Own station dropped frame receiving device.

Claims (1)

[Claims] 1. In a control system when multiple devices access a common line, each device has a detection circuit that detects the end of a signal frame on the line or an empty state, and a first-in, first-out type circuit that accumulates transmitted signal frames. It comprises a buffer memory and an insertion circuit for sending a transmission signal frame to a line, and the transmission signal frame accumulated in the buffer memory is inserted into the transmission signal frame when the end of the signal frame on the line or an empty state is detected by the detection circuit. Common line access, characterized in that signals sent to the line via the insertion circuit and sent from the line during transmission are stored in the buffer memory, excluding signals addressed to the own station, and then sent to the line. control method.