JPH0145261B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a loop transmission method for performing packet communication between terminals in a loop transmission system having a plurality of transmitting/receiving terminals and one control terminal connected in a loop.

Conventionally, a time division multiplexing method that employs a frame structure is known as a communication method for a network in which voice terminals and data terminals coexist. This method is suitable for voice because it guarantees real-time performance, but it is not suitable for data because it cannot easily accommodate data terminals of various speeds and cannot accommodate high-speed data terminals. As another method, a packet multiplexing method focusing on data has been proposed. This method is compatible with various speed terminals for data and allows for flexible system configurations, but for voice there is a delay depending on line activity and real-time performance is not guaranteed. Therefore, it is not very suitable. Note that another type of signal having real-time characteristics is a moving image signal. As a method to improve these two methods, one frame 100 is divided into two subframes by setting a boundary as shown in Fig. 1, and one subframe 101 is used as a time-sharing subframe for audio. However, a method has been proposed in which the other subframe 102 is used as a subframe for packet multiplexing. However, this method has the drawback that efficiency decreases when voice and data traffic is biased to one side. That is, for example, in a situation where voice traffic is high and data traffic is low, even if there is an empty subframe for data, the voice cannot use it, resulting in a decrease in efficiency. In order to eliminate this drawback, the above frame 10
A method of moving the zero boundary when adapting according to traffic conditions was developed in ITriple E Transactions on Communications Volume COM-22, Number 6, Jiyoon, 1981.
(IEEE Tran−sactions on Communications
“Performance Evaluation of a Variable Frame” by B.Maglaris and M.Schwartz published in June 1981 VOL.COM-29 No.6) Multiplexer for Integrated Switched Networks”
(“Performance Evaluation of a Variable
Frame Multiplexer for Intergated Switched
However, the method described in this document requires a central control terminal that monitors the traffic status, which has the disadvantage of making control extremely complex. .

Furthermore, as a method for efficiently transmitting and receiving voice and data signals via a loop-shaped transmission path, I-Triple E Transactions on Communications Volume COM-22, Number 6, June, 1974 (IEEE Transactions
onCommunications VOL.COM−22 No.6
E.R. Hafner (June 1974)
R. “A Digital Loop Communication System” (“A
A register insertion method described in a paper titled "Digital Loop Communication System" is known.Each terminal to which this register insertion method is used has transmitting and receiving registers 202,
It basically consists of a switch 203 and a switch 204. In the figure, the length of the register is assumed to be equal to the packet length. The control method will be explained with reference to FIG. In FIG. 3, a to f indicate states, and in a to f, the flow of data on the switch in each state is shown on the left, and the state of the switch is shown on the right. In the figure, a rectangle written on the left side of the data flow on the switch represents a packet, and the alphabetic characters inside the rectangle are the packet names. 301 in the diagram of the switch status written on the right is the reception register,
302 is a transmission register, and the alphabetic characters in the register are stored packet names. Normally, the switch is down to 1. In other words, it is in a bypass state. Assume that packet A is now passing through the switch, and packet B is following immediately thereafter. At this time, it is assumed that a request to transmit packet D is generated at the terminal and is set in the transmission register 302. This state corresponds to a in FIG. When the last bit of packet A passes,
Switch the switch to terminal 3 (Figure 3b). In this state, the transmission packet D is sent onto the loop (Fig. 3c). When the switch is changed from 3 to 2 when the transmission is completed, packet B is stored in the reception register without being lost (Fig. 3d). From then on, the state in which the receive register is inserted into the loop continues (Fig. 3e). However, if state e continues indefinitely, no new packets can be transmitted, but if the switch is freely switched to terminal 1, the packets passing through the receiving register 301 will be lost. As a method for this switching, if there are only empty packets in the reception register 301, or the simplest and most reliable method is to switch the switch to terminal 1 when the transmission packet D has completed one loop and is stored in the reception register. The state obtained by switching the switch using this latter method is f. The packets are transmitted and passed through the terminal by the control described above. This register insertion method has the characteristics that packet transmission can be performed with almost no waiting time regardless of the degree of loop congestion, and exchange control can be completely distributed. Furthermore, the data transfer time including the waiting time at the terminal is short and the throughput characteristics are good. However, the transfer time of this register insertion method depends on the congestion of the loop and has a drawback that it is not suitable for voice communication because of large variations.

SUMMARY OF THE INVENTION An object of the present invention is to provide a loop transmission method that eliminates the drawbacks of the conventional methods described above and can transmit real-time signals and data with efficient and easy control.

According to the present invention, high priority is given to real-time signal packets, and low priority is given to data packets, and the communication path within the terminal according to the priority is set so that packets with high priority are not delayed when passing through the terminal. control. Furthermore, for real-time signals, in order to realize real-time transmission and bidirectional communication, the sending terminal has a lower priority than real-time signal packets but a higher priority than data packets when requesting real-time signal transmission. A transmission request command packet is sent, and if a response command packet from the receiving terminal is returned within a certain delay time, a real-time signal packet is inserted at the same position as the response command packet and sent. From then on, real-time signal packets are sent at predetermined time intervals until the end of the communication, and the receiving terminal transmits the real-time signal packets generated from the receiving terminal at the same position as the real-time signal packets sent from the calling party. By inserting it, real-time transmission of real-time signals and bidirectional communication are established.

Next, the principle of the present invention will be explained with reference to FIG. In FIG. 4, the transmitting/receiving terminal has an input buffer memory 402 and an output buffer memory 40.
3 and a block 404 having a circuit for decoding packet addresses, a priority determination circuit, and a receiving circuit.
and a switch 405 for selecting a communication path within the terminal. Each terminal of the switch 405 is assigned a number 1, 2, or 3 as shown in the figure. The signal on the signal line 452 is sent to the switch 405
The signal on signal line 450 indicates a transmission signal from the terminal. Further, a signal on a signal line 451 indicates a signal received by the terminal. This terminal is the same for both voice and data terminals. First, a priority control method for data terminals will be described. The control method when a data packet is input to the output buffer memory 403 and a transmission request occurs is as follows.

(1) When a packet with a higher priority than the data packet that has been requested to be transmitted is input from the transmission path 400 or is about to be output from the input buffer memory 402: The data packet that has been requested to be transmitted is sent to the output buffer memory 403. It remains stored and is not output to the transmission path. The switch 405 is the transmission line 4
00 and the packet about to be output from the input buffer memory 402, the packet with the higher priority is passed through. If the priorities of the above two packets are equal, input buffer memory 4
Packets output from 02 are given priority.

(2) When a packet with a priority lower than the data packet requested to be transmitted is input from the input transmission line 400 or is about to be output from the input buffer memory: The data packet requested to be transmitted is sent to the output buffer memory 403. The input packets from the input transmission line 400 are stored and saved in the input buffer memory 402.

Next, the control after the transmission of the transmission data packet is completed is as follows.

(1) When the packets input from the input transmission path 400 have a higher priority than the packets stored in the input buffer memory 402 (packets waiting for output): The packets waiting for output stored in the input buffer memory 402 are Packets input from the transmission line while being stored are sent to the output transmission line 40.
The switch 405 is controlled so that the signal is sent to 1.

(2) When the priority of the next packet input from the transmission path is lower than the priority of the packet waiting for output in the input buffer memory 402: The packet waiting for output stored in the input buffer memory 402 is sent out to the transmission path 401. , input packets input from the transmission path 400 are stored in the input buffer memory 402.

The above control is also applied to input packets from the subsequent transmission path, and in extreme cases, if voice packets (with high priority) continue in succession, the data packets stored in the input buffer memory 402 will be Although voice packets remain stored in the input buffer memory 402, they are not saved in the input buffer memory in the terminal because they have the highest priority.

4 with reference to the two examples of Figures 5 and 6.
The control means of the circuit shown in the figure will be explained.

In FIG. 5, each rectangular box represents one packet, and the alphanumeric characters within the rectangular box represent the packet name. The English letter V indicates a voice packet, and D
indicates a data packet. Here, it is assumed that voice packets have a higher priority than data packets, and all data packets have the same priority. Now, if _a request to send a _D3 packet occurs at the point indicated _{by the} arrow in FIG. (Figure 4)
_D3 packets are evacuated and sent to the transmission path 401 instead.
The switch 405 is selected so that the signal is output to
The state of the output transmission path at the time when one packet time has elapsed from FIG. 5a is shown. In FIG. 5b, the packet _D1 stored in the input buffer memory 402 is the next packet to be input from the transmission path 400, which is the voice packet _{V2 .}
has higher priority, so input buffer memory 4
The switch 40 is set so that the voice packet _V2 is sent to the output transmission line 401 while being stored in the voice packet V2.
5 is controlled. Next, in FIG. 5c after one packet time has elapsed, the input buffer memory 402
The packet _D1 stored in
The packet input from 0 becomes the audio packet again.
Since the voice packet V ₁ is stored in the input buffer memory 407, the switch 405 is controlled so that the voice packet V ₁ is sent to the output transmission path 401. In FIG. 5D, where one packet time has elapsed from FIG.
Switch 405 is controlled so that D ₁ is sent to output transmission line 401 . In Figure 5e,
Packet D ₁ is output to transmission line 401 and transmitted to transmission line 4.
The packet input from 00 is an empty packet, and the transmission request packet is also stored in the input buffer memory 4.
Since there are no packets stored in 02 waiting for output, the switch 405 is controlled to directly connect the input transmission path and the output transmission path.

The control procedure of the circuit shown in FIG. 4 will be explained using the example shown in FIG. Now _, if a request to send packet D ₃ occurs at the _point indicated _by the arrow in FIG. The switch 405 is controlled so that the _D3 packet is output to the transmission line instead. In FIG. 6b, since the packet input from the transmission line 400 is an empty packet, the switch 405 is controlled so that the packet _D1 stored in the input buffer memory 402 is sent to the output transmission line 401. . In FIG. 6c, since the packet input from the transmission path 400 is a voice packet _V1 , the switch is controlled to directly connect the input transmission path 400 and the output transmission path 401, and the data packet is
_D1 and voice packet _V1 are continuous packets as shown in the figure. As is clear from the examples in FIGS. 5 and 6, data packets may be preempted by voice packets, increasing the delay, but voice packets are not delayed at the terminal. In other words, 1
After that, the voice packets sent to the transmission path arrive at the other party's terminal without any delay due to buffer memory. However, in order to guarantee the real-time nature of voice, voice packets must be reliably transmitted from the terminal at certain predetermined time intervals during a call. If this condition is not met, audio packets from other audio terminals may pass through the terminal when transmitting audio packets, and the transmitted audio packets will be in a waiting state within the terminal, resulting in a delay. be.

Furthermore, when considering voice communications such as telephone calls, two-way communications may be established. In the latter two-way communication, the calling side audio terminal secures a time slot for one packet, and the receiving side audio terminal extracts the audio packet from the calling side audio terminal, and the receiving side audio terminal generates the packet at the same packet position. This is done by inserting the audio packets that will be sent and sending them back through the other side of the loop.

FIG. 7 shows a timing chart when two-way voice communication is performed between voice terminals A and B.
Here, voice terminal A is assumed to be the calling side, and voice terminal B is assumed to be the called side. In the figure, the arrows are signals indicating the starting position of each packet generated by the control terminal. The voice packet V _A inserted at terminal A arrives at voice terminal B after receiving a propagation delay on the transmission path. Audio terminal B
Then, audio packet V _A is extracted, audio packet V _B is inserted at the same packet position, and sent to audio terminal A via the opposite side of the loop. At voice terminal A, voice packet _VB is extracted. Bidirectional communication is performed in this way.

Next, a method by which the originating terminal can send voice packets at certain predetermined time intervals will be explained with reference to FIG. It is assumed that voice terminal A and voice terminal B are currently talking, and voice terminal A is the calling party. Further, let V _A be a voice packet from voice terminal A to voice terminal B, and V _B be a voice packet from voice terminal B to voice terminal A. In this state, voice terminal C and voice terminal D
An audio transmission request is made and audio terminal C sends an audio transmission request to audio terminal D.
Assume that an audio transmission request packet (ENQ packet) is sent to In this case, the voice packet V _A and the ENQ packet will collide at voice terminal A, but the priority of the ENQ packet is set to be one level lower than that of the voice packet, but higher than the normal data packet. When set, while audio terminal A is transmitting packet V _A , the ENQ packet is stored and saved in the input buffer memory within terminal A, and passes through audio terminal A after being delayed by one packet. Thereafter, the voice packet V _A is extracted at the voice terminal B, and the voice packet V _B from the voice terminal B is placed on the same packet position and sent to the loop transmission path. In addition, the ENQ packet is also extracted by audio terminal D and the ENQ packet is placed at the same packet position.
An ACK packet indicating that it has the same priority as the packet and can be transmitted is placed on it and sent out onto the loop transmission path. This ACK packet is extracted by voice terminal C, and a voice packet V _C from voice terminal C is inserted into the same packet position as the ACK packet and sent to the loop transmission path. As above,
The packet position of the voice terminal that has issued the transmission request is determined, and thereafter voice packets are sent out at predetermined time intervals, and this packet position never collides with the voice packet position between voice terminals A and B. This means that a fixed channel is secured during the call. Figure 8 shows an example where there are only two voice terminals in use, but the same holds true when there are many voice terminals in use, and the position of the transmitted voice packet can be determined using ENQ and ACK packets. is determined. however,
Although the delay until the ACK packet returns increases (in the example in Figure 8, the transmission path propagation delay +1
This delay corresponds to the number of voice packets during the call, and if the voice activity is determined by this amount of delay, the channel is assumed to be secured and the call is started within a certain predetermined time. As described above, send ENQ and ACK packets to 1
A voice channel is equivalently secured by only exchanging information once at the start of a call, and voice packets can be sent out at regular time intervals.

FIG. 15 is a diagram showing the basic configuration of the system.
In the figure, signals flow in the direction indicated by the arrow on transmission line 1500. The control terminal 1501 periodically transmits a signal indicating the beginning position of a packet when transmitting a packet between each transmitting/receiving terminal 1502 to 1502N, and establishes loop synchronization so that the loop-round transmission path delay is an integral multiple of the packet length. Do the following.
Various devices are connected to each transmitting/receiving terminal.

FIG. 10 shows the packet structure used in the system of FIG. 15. In the figure, M indicates a marker bit, "1" indicates packet use, and "0" indicates packet use.
indicates an empty packet. P indicates priority information;
Allocate the number of bits corresponding to the priority type of the terminal accommodated in the system. AD1 is sending address information and AD2 is receiving address information. ENQ is a 1-bit signal that sets "1" to notify the receiving terminal when a transmission request occurs on the transmitting side.
For ACK and NCK, if the receiving terminal approves the reception of the ENQ signal received from the transmitting side, it will set "1" in the ACK position, and if it rejects the reception, it will set "1" in the ACK position.
Each signal is a 1-bit signal that sets "1" at the NCK position. In the figure, the information indicated by CON is header information, and the information indicated by DAT is data.

FIG. 9 is a block diagram of a transmitter/receiver section of a data terminal used in the system of FIG. 15. In FIG. 9, an input packet from an input transmission line 901 is applied to a shift register 903. The shift register 903 has a serial input terminal and two types of output terminals, serial and parallel, and has the same length as the header length of one packet. The header information of the shift register 903 is output from the parallel output terminal to the signal line 951 as parallel information. The received address of the header information is given to an address matching circuit 905, and the marker bit and priority information are input to a priority selection circuit 904. When the input packet passes through shift register 903, it will be subject to a delay corresponding to the header length. Address verification circuit 905
is easily constituted by an exclusive OR gate, which compares the received address of the input packet with the address of the terminal and outputs a match/mismatch signal to signal line 955. If the receiving address and the terminal address match, the input packet is a packet to be received by the terminal, so the marker bit of the input packet must be erased to make it an empty packet. Therefore, the address matching circuit 905 transmits the marker erase signal to the signal line 95.
Output to 2. A marker erase signal on signal line 952 erases the marker bit in the header information stored in the shift register. The priority selection circuit 904 selects the marker bits and priority information of the input packet given via the signal line 951,
A signal and an input signal for selecting the highest priority packet based on the marker bits and priority information of the output waiting packet accumulated and saved in the input buffer memory 906 and the marker bits and priority information of the sending packet given from the output buffer memory 908. A status signal representing a control signal for the output buffer memory, etc. is output to a signal line 956. Conversion circuit 60
7 converts the packetized signal into an information signal suitable for various devices connected to the terminal. That is, the conversion circuit 907 receives an input packet from the signal line 950, and if the output signal of the address verification circuit on the signal line 955 is a match signal, it sends an information signal to various devices connected to the data terminal via the signal line 957. Send. Information signals from various devices connected to the data terminal are input to the packetization circuit 909 via the signal line 958, where they are given header information and converted into packets of a predetermined size before being sent to the signal line. 959. Signal line 959 signal is output buffer memory 90
8 and waits to be sent out to the transmission line via the signal line 960. Whether or not the transmission path can be transmitted via the signal line 960 is controlled by the status signal of the signal line 956. Of the header information of the outgoing packet stored in the output buffer memory 908 and waiting to be sent out to the transmission path, marker bits,
Priority information is output to signal line 954. The input buffer memory 906 temporarily stores and saves packets that are not sent to the output transmission path by the switch 910 among the input packets from the signal line 950. Whether or not data can be stored and saved in the input buffer memory 906 and whether or not it can be sent from the input buffer memory 906 to the output transmission line 902 is controlled by a state signal on the signal line 956. Of the header information of the delayed packet stored in the input buffer memory 906, marker bits and priority information are output to a signal line 953. The switch 910 selects the packet with the highest priority among the input packet from the signal line 950, the delayed packet from the signal line 961, and the packet sent from the signal line 960.
controlled by status signals from

FIG. 11 shows the priority selection circuit 90 shown in FIG.
4 is a detailed circuit diagram of FIG. In the figure, the signal line 11
50 and 1151 indicate marker bits and priority information expressed by a signal line 954 outputted from the output buffer memory 908 in FIG.
The signal lines 1154 and 1155 show the marker bits and priority information of the input packet from the transmission path. AND gate circuits 1101 and 1102 are
The input marker bit and each bit of priority information are ANDed, and the signal lines 1156 and 1156 are respectively connected.
1157. For example, if the marker bit is "1", the output signal of the AND gate circuit is the same as the input priority information, and if the marker bit is "0", the output signal of the AND gate circuit is all zero. In addition to the marker bit and priority information, the AND gate circuit 1103 receives an address match signal from a signal line 955, and performs a logical product of the address match signal, the marker bit, and each bit of the priority information. For example, if the address match signal on signal line 955 is "1" (that is, the receiving address of the input packet and the terminal address do not match) and the marker bit is "1", the signal on signal line 1158 is the same as the input priority information. , the address match signal is “0” (that is, the receiving address of the input packet and the terminal address match) or the marker bit is “0”
Then, all the signals on the signal line 1158 become 0.
The signals on the signal lines 1156, 1157, and 1158 are input to the highest priority detection circuit 1104, and the signal indicating the highest priority input is output as a 2-bit signal to the signal line 1159 while maintaining the same state for one packet time. The signal on the signal line 1159 is the control signal for the switch 910 in FIG. 9 and the input/output buffer memory 9.
The output control signal is 06,907. Signal line 11
The signal indicating the marker bit of the input packet No. 54 and the signal on the signal line 1159 are input to the gate circuit 1105, and the signal indicating the marker bit of the input packet No. 54 is input to the gate circuit 1105.
If the switch is not selected so that the signal on the signal line 1159 sends the input packet to the output transmission path (marker bit 4 is "1"), the signal on the signal line 1160 for storing input packets in the input buffer memory 906 in FIG. Output. Signal lines 1159 and 1
The signal 160 corresponds to the signal on signal line 956 in FIG.

FIG. 12 is a block diagram showing a transmitting/receiving section of a voice terminal that transmits and receives voice packets. 12th
In the figure, an input packet from an input transmission path 1201 enters a shift register 1203. The shift register 1203 has a serial input, two types of output terminals, serial and parallel, and has the same length as the header length of one packet. The header information of the shift register 1203 is output from the parallel output terminal to the signal line 1251 as parallel information, and the received address of the header information is input to the address matching circuit 1206. The marker bit and priority information are input to a priority selection circuit 1205. On the other hand, ENQ,
The ACK and NCK signals are input to a header decoder 1204. Input packet is transferred to shift register 1203
When passing through the header, there is a delay corresponding to the header length. Address matching circuit 1206 is easily configured with an exclusive OR gate, compares the received address of the input packet with the address of the terminal, and outputs a match/mismatch signal to signal line 1255. If the receiving address and the terminal address match, the input packet is a packet to be received by the terminal, so the marker bit of the input packet must be erased to make it an empty packet, so the address matching circuit 1206
outputs a marker erase signal to signal line 1252. Marker bits of the header information stored in the shift register 1203 are erased by the signal on the signal line 1252. The priority selection circuit 1205 receives the marker bits and priority information of the input packet, the marker bits and priority information of the delayed packets stored and saved in the input buffer memory 1207, and the marker of the audio packet sent from the terminal from the output buffer memory 1208. The bit and priority information ACK, the ACK output from the NCK generator 1212, the marker bit and priority information of the NCK packet, the match/mismatch signal from the signal line 1255, and the control signal from the signal line 1256 are input. A priority selection circuit 1205 selects switch 1 so that the highest priority packet is sent to the output transmission path.
214, control signals for buffer memories 1207 and 1208 for input/output, and control signals for selector 1211 for selecting packets from output buffer memory 1208 and ACK/NCK packet generator 1212. is generated and sent to signal line 1257. When transmitting and receiving voice packets, in order to ensure the real-time nature of the voice packets and to establish two-way communication, when the receiving voice terminal receives an ENQ packet, it is necessary to insert an ACK packet or NCK packet in the position of the packet and send it back to the transmitting terminal. There is. In addition, when the calling side audio terminal receives an ACK packet, it enters a talking state and inserts an audio packet at that packet position, and thereafter transmits voice packets at predetermined time intervals, and the receiving side audio terminal receives the audio packets from the calling side. , inserts an audio packet into that packet position, and sends it back. The header decoder 1204 includes
Header information from shift register 1203, a match/mismatch signal from address verification circuit 1206, and an audio terminal status signal from signal line 1268 are provided. When the decoder 1204 detects an incoming ENQ packet (which can be seen just by looking at the header information), it sends an ACK/NCK packet generator 1212 to the ACK/NCK packet generator 1212.
An activation signal that sets a marker bit of an ACK or NCK packet depending on the state of the voice terminal on the receiving side and address information are sent via the output signal line 1256, and a control signal is also sent to the priority selection circuit 1205 via the signal line 1256. give. In addition, when the voice terminal on the receiving side receives a voice packet during a call, the voice packet reception information is sent to the output buffer memory 1 via the signal line 1256 in order to insert the voice packet in the same packet position as the received voice packet and send it back.
Send to 208. This received information becomes a signal for creating marker bits for voice packets on standby. At the originating voice terminal, the header decoder 1204
When an ACK packet is received, the ACK packet reception information is sent to the output buffer memory 1208 via the signal line 1256, a marker bit of the waiting audio packet is set, and the priority selection circuit 1205
control to send audio packets. A conversion circuit 1209 is a circuit that converts a packetized audio signal into an audio signal suitable for the audio equipment connected to the terminal.Input packets are input from the signal line 1250, and the address matching circuit from the signal line 1255 is input. If the output signal is a matching signal, the audio signal is sent to the audio device via the signal line 1259. An audio signal from an audio device is inputted to a packetization circuit 1210 via a signal line 1260, and is added with header information and is converted into a packet of a predetermined size and inputted to a signal line 1261. The signal on the signal line 1261 is sent to the output buffer memory 120.
8 and waits to be sent out to the transmission line. Of the header information of the sending packet stored in the output buffer memory 1208, marker bits and priority information are output to the signal line 1254. An output line 1262 of the output buffer memory 1208 is connected to the selector 1211. Selector 1211
Is it a packet from the output buffer memory?
The packet from the ACK/NCK generator 1212 is selected by the control signal on the signal line 1256.
Of the packet header information from the ACK/NCK generator 1212, marker bits and priority information are sent to the priority selection circuit 120 via a signal line 1258.
given to 5. Input buffer memory 1207
Of the input packets from the signal line 1250, the packets that are not sent to the output transmission path by the switch 1214 are temporarily stored and saved. Whether or not to store and save data in the input buffer memory 1207, and whether or not to store or save data in the input buffer memory 1207 and the signal line 126 from the input buffer memory 1207.
Whether or not the data can be sent to the transmission line 1202 via the signal line 1257 is controlled by a control signal on the signal line 1257. Of the header information of the delayed packet stored in the input buffer memory 1207, marker bits and priority information are output to a signal line 1253. Switch 1214 selects a communication path within the terminal. This switch 1214 receives input packets from signal line 1250, delayed packets from signal line 1265,
The signal line 12 is configured to select the packet with the highest priority among the packets sent from the signal line 1264.
It is controlled by a control signal from 57. The timer 1213 is connected to the signal line 12 in the case of a calling voice terminal.
The time from when a signal indicating the time when the ENQ packet is sent is input from signal line 1256 to when a signal indicating the time when the ACK packet is returned is input from signal line 1256 is measured, and when a certain predetermined time is exceeded, a timeout signal is output. is sent to the audio equipment side via the signal line 1267.

FIG. 13 shows the priority selection circuit 1205 of FIG.
FIG. In the figure, signal line 135
1 and 1352 are ACK/NCK generator 1 in Figure 12
The signal lines 1353 and 1354 show the marker bits and priority information output from the output buffer memory 1208 in FIG. Further, signal lines 1355 and 1356 indicate the marker bits and priority information output from the input buffer memory 1207 in FIG. 12, and signal lines 1357 and 1358 indicate the marker bits of the input packet input from the signal line 1251 in FIG. and priority information. AND gate circuits 1301, 1302, 1303
calculates the AND of the input marker bit and each bit of the priority information, and connects each bit to the signal line 135.
Output to 9, 1360, 1361. For example, if the marker bit is "1", the output signal of the AND gate circuit is the same as the input priority information, and if the marker bit is "0", the output signal of the AND gate circuit is all zero. AND gate circuit 1
In addition to marker bits and priority information, an address match signal is inputted to 304 from a signal line 1255.
The address match signal, marker bit, and each bit of priority information are ANDed. For example, if the address match signal on signal line 1255 is "1" (that is, the receiving address of the input packet and the terminal address do not match) and the marker bit is "1", the signal on signal line 1362 is the same as the input priority information. It is. On the other hand, the address match signal is “0” (that is, the receiving address of the input packet and the terminal address match)
Alternatively, if the marker bit is "0", all signals on signal line 1362 are zero. The signals on the signal lines 1359, 1360, 1361, and 1362 are input to the highest priority detection circuit 1306, and the code indicating the highest priority input is output as a 2-bit signal to the signal line 1363 while keeping the same state for one packet time. Ru. The signal on the signal line 1363 becomes a control signal for the switch 1214 in FIG. 12 and an output control signal for the input/output buffer memories 1207 and 1208. A signal indicating the marker bit of the input packet on the signal line 1357 is input to the signal gate circuit 1307 on the signal line 1363, and if the input packet exists (that is, the marker bit on the signal line 1357 is "1"), the signal on the signal line 1363 is input. If the switch is not selected to send the packet to the output transmission path, the input buffer memory 1207 in FIG.
Signal line 1 is used to store and save input packets.
365. Also, from the signal line 1256
The ENQ packet reception signal and the signal on the signal line 1363 are input to the gate circuit 1305, and when the ENQ packet is received and the packet from the ACK/NCK generator 1212 is the highest priority packet, the signal on the signal line 1263 is input to the selector 1211. Signal line 12
The control signal to be output to 64 is connected to signal line 1.
364. Signal lines 1363, 1364,
The signal 1365 corresponds to the signal on the signal line 1257 in FIG.

FIG. 14 is a circuit diagram showing details of the header decoder 1204 of FIG. 12. In the figure, signal line 1
Among the header information from 251, marker bits are sent to AND gates 1401 to 140 via signal lines.
4 is input. And gate 1401 has
The ENQ signal is input via the signal line 1450,
The AND of both is taken and output to signal line 1454. The output of this AND gate 1401 becomes a signal for setting the marker bit of the packet from the ACK/NCK generator 1212 in FIG. 12 and a signal supplied to the priority selection circuit 1205 in FIG. 1405 is input. Among the voice terminal status signals given via the signal line 1268, the terminal busy signal is sent to the signal line 14.
58 to the AND gate 1405,
A logical AND is performed with the output of AND gate 1401 and output to signal line 1460. and gate 140
The output of No. 5 is supplied to the ACK/NCK generator 1212 in FIG. 12 as a selection signal of the ACK/NCK packet for the ENQ packet at the receiving terminal. For example, if the called terminal is not busy, it will respond with ACK to the ENQ packet from the calling terminal.
ACK/NCK generator 1 to send back packets
212 control is performed. and gate 140
2 is provided to detect the arrival of a voice packet, and this AND gate 1402 receives a polarity inverted signal of the ENQ signal from the signal line 1450,
A polarity inversion signal of the ACK signal from the signal line 1452,
The polarity inverted signal of the NCK signal from the signal line 1453 and the marker bit from the signal line 1451 are inputted, and the logical product thereof is taken and outputted to the signal line 1455. The output signal of AND gate 1402 and the signal indicating that it is an incoming voice terminal in the voice terminal status signal given via signal line 1459 are input to AND gate 1406, and the logical product of these signals is calculated. is output to signal line 1461. The signal from the AND gate 1406 is used as the voice packet arrival signal at the receiving terminal.
This signal is applied to the output buffer memory 1208 in the figure and sets the marker bit of the audio packet waiting in this memory. Signal line 145
The ACK signal from signal line 1451 and the marker bit from signal line 1451 are ANDed by AND gate 1403 and output to signal line 1456. The output signal of AND gate 1403 is
The ACK signal reception information is sent to the output buffer memory 1208 in FIG. 12, and becomes a signal that sets a marker bit of a voice packet on standby. NCK signal from signal line 1453 and signal line 1451
The marker bits from are ANDed by an AND gate 1404 and output to a signal line 1457.
The output signal of the AND gate 1404 is a signal indicating that the called side is in a busy state, and is notified to the audio equipment side. In the figure, signal lines 1454,
Signals 1460, 1461, 1456, and 1457 correspond to the signal on signal line 1256 in FIG.

As described above, in the present invention, by giving a high priority to voice packets and a low priority to data packets, voice packets having a high priority can be sent without delay. Further, according to the present invention, control is decentralized, and real-time audio and bidirectional communication can be easily established.

Note that in the above explanation, three types of packets are used: voice packets, data packets, and voice communication communication procedure packets.
Although packets with different priorities are used, it is also possible to further divide the priorities depending on the nature of the information source.

[Brief explanation of drawings]

Figure 1 is a frame configuration diagram in which one frame is divided into a time division subframe and a packet multiplexing subframe, Figure 2 is a basic block diagram of a terminal using the register insertion method, and Figure 3 shows the control method for the register insertion method. The timing chart shown in FIG. 4 is a basic block diagram of the transmitting/receiving terminal of the present invention, and FIGS.
The figure is a timing chart for explaining the transmission method of the present invention, Figure 7 is a timing chart when performing full-duplex voice communication according to the present invention, and Figure 8 is a timing chart for explaining the transmission method of voice packets even when voice packets are being transmitted. FIG. 9 is a block diagram showing a transmitting/receiving section of a data terminal which is an embodiment of the present invention, and FIG. 10 is a diagram showing an example of the configuration of a packet used in the present invention. ,
FIG. 11 is a diagram showing an embodiment of the priority selection circuit used in FIG. 9, and FIG. 12 is a block diagram showing a transmitting/receiving section of a voice terminal which is an embodiment of the present invention.
13 is a diagram showing an embodiment of the priority selection circuit used in FIG. 12, FIG. 14 is a diagram showing an embodiment of the header decoder used in FIG. 12, and FIG. 15 is a diagram showing an embodiment of the priority selection circuit used in FIG. 1 is a block diagram showing a system configuration to which the present invention is applied. In the figure, 200...input transmission line, 201...
...Output transmission line, 202...Reception register, 203
...Transmission register, 204 ...Switch, 400
...Input transmission line, 401...Switch, 402...
...Input buffer memory, 403...Output buffer memory, 404...Priority determination circuit, 90
1,1201...Input transmission line, 902,1202
... Output transmission line, 903, 1203 ... Shift register, 905, 1206 ... Address verification circuit, 904, 1205 ... Priority selection circuit, 90
6,1207...Input buffer memory, 90
7,1209...Conversion circuit, 908,1208...
...Output buffer memory, 909, 1210...
Packetization circuit, 910, 1214...Switch, 1204...Header decoder, 1211...Selector, 1212...ACK/NCK generator, 12
13...Timer, 1101, 1102, 110
3,1301,1302,1303,1304,
...And gate circuit, 1104, 1306...
Maximum value detection circuit, 1105, 1305, 1307
...Gate circuit, 1401, 1402, 140
3, 1404, 1405, 1406...AND gate, 1500...Transmission line, 1501...Control terminal, 1502(1) to 1502(N)...Transmission/reception terminal.

Claims (1)

[Scope of Claims] 1. In a loop transmission system in which a plurality of transmitting/receiving terminals and one control terminal are connected in a loop and packet communication is performed between each transmitting/receiving terminal, the control terminal is capable of transmitting packets. A signal indicating the tip position is periodically sent out, and the loop synchronization is established so that the transmission path delay when going around the loop is an integral multiple of the length of the packet, and the transmitting/receiving terminal transmits the transmission information signal. a first storage means that gives priority to the information signal according to its type and stores and saves input packets from the input transmission path in each of the transmission and reception terminals; a second storage means for storing the packet, and compares the priorities of the input packet, the packet stored in the first storage means, and the outgoing packet, and selects the packet having the highest priority. A loop transmission method characterized by transmitting. 2. In a loop transmission system in which a plurality of transmitting/receiving terminals and one control terminal are connected in a loop and packet communication is performed between each transmitting/receiving terminal, the control terminal transmits a signal indicating the leading position of the packet. The loop synchronization is established so that the transmission path delay when transmitting periodically and going around the loop is an integral multiple of the length of the packet, and the input packets from the input transmission path are transmitted to each of the transmitting and receiving terminals. A first storage means for storing and saving packets and a second storage means for storing packets sent from an information generating device connected to the transmitting/receiving terminal are provided,
The transmitting/receiving terminal gives a first priority to the real-time signal among the transmitted information signals, gives a second priority to the command packet used at the start of the real-time signal communication, and gives a third or lower priority to the data. The transmitting terminal among the transmitting and receiving terminals sends a transmission request command packet when the real-time signal transmission request occurs, and the receiving terminal receives the transmission request command packet and sends a response command packet. The transmission request command packet is inserted into the same packet position as the transmission request command packet and sent back, and at intermediate terminals other than the originating and terminating terminals among the transmitting and receiving terminals, the transmission having the second priority circulates through the loop. Comparing the priorities of the request command packet or the response command packet and the intermediate transmission packet from the second storage means of the intermediate terminal, and if the intermediate transmission packet has the first priority; The transmission request or response command packet is stored and saved in the first storage means of the intermediate terminal, and the intermediate transmission packet is stored in the third storage means.
If the transmission request or response command packet has a priority of If received within a predetermined time from the time of transmission, a real-time signal packet is inserted at the same packet position as the response command packet, and the receiving terminal compares the real-time signal packet transmitted from the originating terminal with the real-time signal packet. A loop transmission system characterized in that two-way communication of the real-time signal is established by inserting and returning the real-time signal packet at the same position. 3. In a data transmitting/receiving device for a loop transmission method, which has a plurality of transmitting/receiving terminals and one control terminal, and connects these terminals in a loop to perform packet communication between each transmitting/receiving terminal, means for extracting header information; address matching means for comparing the reception address of the input packet in the header information with the address assigned to the terminal; and means for extracting the input packet from various devices connected to the terminal. an input storage means for storing and saving the input packets; a packetization means for packetizing information signals from various devices connected to the terminal; An output storage means to which the output of the packetization means is connected, and a priority check that compares the priorities of the input packet, delayed packets stored and saved in the input storage means, and packets sent out from the output storage means. degree selection means;
It has a switch that sends out any one of the input packet, the delayed packet, and the outgoing packet to an output transmission path, and
A transmitting/receiving device for a loop transmission system, characterized in that evacuation control, output control of accumulated/saved delayed packets, output control of the sending packets, and selection of the switch are performed by signals from the priority selection means. 4. In a real-time signal transmitting/receiving device for a loop transmission method, which has a plurality of transmitting/receiving terminals and one control terminal and connects these terminals in a loop to perform packet communication between each transmitting/receiving terminal, input from an input transmission path means for extracting header information of a packet; address matching means for comparing the reception address of the input packet in the header information with an address assigned to the terminal; a conversion means for converting the information signal into an information signal suitable for the real-time signal generating device connected to the terminal; an input storage means for accumulating and saving the input packets; packetization means for packetizing the time information signal; output storage means for accumulating the output of the packetization means; command packet generation means for generating transmission request and response command packets; a priority selection circuit that compares the priorities of the delayed packets stored and saved in the output storage means, the output packets from the output storage means, and the transmission request and response command packets; and the header information. means for determining the type of the command packet from the input; a timer for calculating the time from when the transmission request command packet is sent to when the response command packet is received and transmitting a timeout signal to the real-time signal device; A switch for transmitting one of the delayed packets, the transmitted packets, and the command packets to an output transmission path, and controls accumulation and saving of the input packets, and controls the accumulated and saved delayed packets. output control,
A real-time signal for a loop transmission system, characterized in that output control of the sending packet, output control of the command packet, and selection of the switch are performed by output signals of the priority selection means and the command packet determination means. Transmitting/receiving device.