FR2629972A1 - Device and method for managing priority - Google Patents

Abstract

The invention relates mainly to a device and method for managing priority. The invention relates to priority management using two stacks 1, 2 of first-in, first-out type, a multiplexer, two comparators 7, 23, a counter 6 and a register 3. In an instantaneous phase the comparator 7 stores in the register 3, by way of the multiplexer 4, the information to be forwarded. During the analysis phase which looks for the highest priority and oldest information item, the information items arriving in instantaneous mode are also compared and if they are of higher priority, they are stored in the register 3 until the oldest information item having the highest priority in the register is obtained. The invention applies to the management of priorities. The invention applies mainly to the management of priorities in television transmissions and to the carrying out of television transmissions using priority management.

Description

 PRIORITY MANAGEMENT DEVICE AND METHOD.

 The invention relates to the priority management device and method.

 It is known to establish transmission standards making it possible to obtain very high data rates.

Some of these standards require the transmission of information at predetermined times. Such standards are used, in particular, in television transmission such as for example the
D2 MAC Packets, or data transmissions on the synchronous bus. To comply with such a standard, it is imperative to determine the information to be transmitted. In a given standard, the information to be sent, for example, will be among the information with the highest priority the oldest information. Standards may impose additional selection criteria. For example, we may want to avoid the interlacing of groups of information to be sent. Thus, during the transmission of information belonging to a group, information belonging to another group cannot be inserted even if it is no longer priority. On the other hand, isolated information with higher priority may be inserted in the group.

 The device according to the present invention comprises a first in, first out type stack (FIFO in English terminology) dedicated to determining the information having the highest priority and available for the longest time. The content of the stack is compared by a comparator, the value to be transmitted being for example loaded in a register. By successively scanning all the data stored in the stack, one is sure at the end of the analysis period to find in the register the data to be sent.

 The use of the device according to the present invention makes it possible to simultaneously process a plurality of sources of the data to be transmitted. The number of sources is limited only by the speed of calculation of the device according to the present invention and by the depth of the batteries used. By stack depth is meant the number of stages or registers between the input and the output of the stack. In addition, even for insufficient computing power, there is information to be transmitted at the output of the device according to the present invention. The probability of having the right information, i.e. the one with the highest priority and. the longest duration in this priority depends on the part of the stack that has been checked by the comparator.

 The main object of the invention is a device for priority management in the transmission of information as described in claims 1 to 8.

 The subject of the invention is also a transmitter of television programs as described in claim 9.

 The invention also relates to a priority management method as described in claims 10 and 11.

The invention will be better understood by means of the description below and the appended figures given as nonlimiting examples among which
- Figure 1 is a diagram of a first embodiment of a priority management device according to the present invention
- Figure 2 is a diagram of an exemplary embodiment of a television transmission device according to the present invention
- Figure 3 is a diagram of the preferred embodiment of the priority management device according to the present invention.

 In FIGS. 1 to 3, the same references have been used to designate the same elements.

 In FIG. 1, an exemplary embodiment of a priority management device according to the present invention can be seen.

 The device comprises a first battery 1 of the first in first out type, a second battery 2 of the first in first out type, a counter 6, a control device 5, a first comparator 7, a second comparator 23, a multiplexer 4 and a register 3.

 A bus 8 is connected to the input of battery 1, of comparator 7 and of multiplexer 4. A bus 9 connects the output of battery 1 to the input of battery 2, on the other hand the output of battery 2 is connected to the bus 9 and by the same to the input of the stack 2. Likewise the output of the stack 2 is connected on the one hand to the comparator 23 and on the other hand to a second input of the multiplexer 4. The output of multiplexer 4 is connected by a bus 11 on register 3. The output of register 3 is connected, by a bus 10, on the one hand to the second input of comparator 23 and on the other hand to the output of the device according to the present invention.

 The battery 1 is connected by a line to the counter 6. The counter 6 is connected by a line to the control device 5.

The comparator 23 is connected by a line to the control device 5. The control device 5 is connected by lines to the comparator 3, to the battery 1, to the battery 2, as well as to the multiplexer 4. The comparator 7 is connected by a command line to the multiplexer 4. The register 3 receives a command line causing the transmission of the data contained in this register, this line comes from outside the device of FIG. 1.

 The data which must be transmitted by the bus 10 arrives by the bus 8. Each data item includes at least the information concerning the priority level of the transmission.

 The first datum is stored on the one hand in the stack 1 and on the other hand, via the multiplexer 4 and the bus 11 in the register 3. This corresponds to the initiation of the system. Theltlallsstion is obtained by a command from the control device 5 on the multiplexer 4. The control device 5 will proceed to initialization insofar as the counter 6 indicates that the battery 1 is empty. From initialization, register 3 is capable of providing, on external command, data on bus 10 on request.

 When the following data arrive on the bus 8 they are stored on the one hand in the stack 1 and on the other hand are compared in the comparator 7 with the content of the register 3.

If the priority of the information contained in the register 3 is lower than that of the data transmitted by the bus 8, the comparator 7 sends a signal to the control unit 5 celul-cl aiguflle the data from the bus 8 to the bus 11 via the multiplexer 4 on the one hand and orders the storage of this new data in the register 3. It should be noted that the old data of the register 3 is not lost insofar as it is still stored in the stack 1. On the other hand, the content of register 3 is not modified sl the priority of the data which is stored is greater than or equal to that of the data present on the bus 8. The process is continued until a request for transmission.

 After a transmission, new data must be loaded into register 3 again. It is therefore necessary to determine the data item having the highest priority and for this priority the oldest arrival date. This determination is obtained in a phase of analysis of the content of the stack 1. In order to be able to process new data arriving in the device according to the present invention, the stack 1 is copied into the stack 2. However, the stack 1 still contains the information that has been issued. This information is erased by means not shown in FIG. 1. This erasure is carried out in stack 1, in stack 2 or during the transfer from stack 1 to stack 2. From the moment when register 3 contains new data which can be sent comparator 23 compares if the priority of the data present in stack 2 is strictly higher than that present in register 3. During the analysis phase all the information present in stack 2 is successively compared to those already present in register 3. At each comparison the compared value of stack 2 is rewritten at the entry of stack 2. If the value is strictly greater the value is entered in register 3. At the end from the analysis phase we have in register 3 the oldest information corresponding to the highest priority. This information is ready to be sent on request.

 Advantageously, if new information arrives on the bus 8 during an analysis phase, it is firstly stored in the stack 1 and secondly compared via the comparator 7 to the value contained in the register 10. In the case where the priority of the information arriving on the bus 8 would be higher than that contained in the register 3, the new value is written via the multiplexer 4 and the bus 11 in the register 3 then the phase of analysis is continued. The use of two batteries 1 and 2 is advantageous because it allows treatment during. the analysis phase of new information. Advantageously, the information contained in the stack 1 will be transmitted in the stack 2 via the bus 9 at the end of the analysis phase.

 During the transmission request the content of register 3 is put on the bus 10. From this moment the identity of the information transmitted is recorded in an erasure register (not shown in 1) and this information will be by the comparator 23 detected during the next analysis, then the information will be destroyed (not rewritten in stack 2).

 After the transmission, any information received by the bus 8 is transferred to the stack 1 during the previous analysis phase, to the stack 2.

 The analysis phase is resumed to determine the new information to be stored in the register 3 for transmission on the bus 10.

 The information to be transmitted on the bus 10 varies - depending on the application of the device according to the present invention.

The information can for example be digital data. It is possible in this case not to transmit if this is not necessary the priority level of this datum. In another use of the device according to the present invention, the information present in the register 3 can be an address.

The address can correspond for example to the address of information present in a table, for example in a memory or the physical address of a device. It is for example possible to use the address transmitted on the bus 10 to determine which physical device will carry out the transmission of information, such as for example sound information in the television broadcast standard D2 MAC Packets.

 In FIG. 2, an exemplary embodiment of a transmission device can be seen, for example according to the D2 MAC Packets standard according to the present invention. It is understood that the use of other television program standards does not depart from the scope of the present invention.

 The device of FIG. 2 comprises a multiplexer 17 intended to transmit video information and sound information or alphanumeric data alternately. The video information is supplied to the multiplexer 17 from a video source 12 via a video coder 16.

The video source 12 is for example a television camera, a video recorder or a control room. The video encoder 16 is known as such.

 The television standard D2 MAC Packets allows the simultaneous transmission of several sound channels and alphanumeric data; the number of channels depends on the quality desired for each channel. The information transmitted is multiplexed. The information is multiplexed by the multiplexer 18. At the request of the multiplexer 17 the multiplexer 18 must be able to provide sound information belonging to one of the transmitted channels.

 The multiplexer 18. receives the sound information from a plurality of sound sources 13 or 14 via sound coders 15. The sound sources 13 are for example microphones. The sound sources 14 are for example tape recorders, record players or sound synthesis devices.

 The encoder 15 as well as the sound sources 13 and 14 are known as such.

 Each encoder 15 corresponds to a physical address.

When an encoder 15 has formed information to be transmitted called
Packet in the standard, it informs the multiplexer 18. Each coder 15 is associated with a priority level. For example a coder intended to put a high-fidelity stereophonic channel, will have a higher priority å a coder intended for the emission of sound in low quality.

 The multiplexer 18 comprises the priority management device as illustrated in FIG. 1. The multiplexer 18 supplies the device of FIG. 1 with the address of the coder 15 capable of transmitting as well as its priority level.

The age and availability of a sound package are determined by the time of its arrival in a priority management device. During a transmission request sent by the multiplexer 17 to the multiplexer 18 which arrives at the register 3 of the device of FIG. 1, the device of FIG. 1 transmits the address of the coder 15 which must carry out the transmission of a packet to the multiplexer 17, for example through the multiplexer 18. The device of FIG. 1 incorporated in the multiplexer 18 allows the management of data streams coming from various coders 15 while respecting their priority and the date of availability of Packets The sound multiplexer of the transmission device according to the D2 MAC standard of known type comprises a priority management decision logic comprising at least one first in, first out type stack by associated coder. The multiplexer 18 according to the present invention comprises two batteries 1 and 2 of FIG. 1 making it possible to manage 4,8,16,32,64 or for example 128 sound channels simultaneously. Thus the device according to the present invention is simpler and more economical while retaining the performance of devices of known type.

 The multiplexer 17 is connected to a transmission device comprising a high power and high frequency stage 120 and a transmitting antenna 121. The stage 120 comprises for example high frequency amplifiers and modulators. The emission can be either direct, or directed towards a relay or an antenna of reception of satellite, the retransmission will be made in this case by the satellite itself.

 In FIG. 3, one can see the preferred example of embodiment of a priority management device according to the invention intended for a multiplexer 18 of FIG. 2 intended to multiply the sound in the emissions according to the television standard D2 MAC Packages.

 The device of FIG. 3 comprises a first stack 1 of the first in, first out type, a second stack 2 of the first in, first out type, a multiplexer with two inputs 4, a control device 5, a first register 3, a second register 103, a third register 26, a fourth register 27, a first counter 6, a second counter A9, a third counter 29, a first comparator 7, a second comparator 23, a third comparator 25, a fourth comparator 28, a first detector 21, a second detector 24, a flip-flop 22 and an output interface 20.

 The priority information arrives at the device in FIG. 3 via a bus 57. The bus 57 is connected to the input of the register 103. The output of the register 103 is connected to the bus 8.

The bus 8 is connected to the input of the battery 1, to the input of the detector 21, to a first input of the comparator 7, and to a first input of the multiplexer 4. The output of the battery 1 is connected to a bus 9. Bus 9 is connected to the input of battery 2. The output of battery 2 is connected to a bus 104. Bus 104 is connected to bus 9, to a second input of multiplexer 4, 9 to a first input of the comparator 23, at the input of the detector 24, to a first input of the comparator 25, and to a first input of the comparator 28. The multiplexer 4 is connected by a bus to the input of the register 3. The output of the register 3 is connected to a bus 10. The bus 10 is connected to an output interface 20, to a second input of comparator 7, to a second input of comparator 23, to the input of register 26, to the input of register 27 and at the input of the counter 29. The output of the register 26 is connected by a bus to the second input of the comparator 25. The output of the register 27 is connected to a bus at the s second comparator input 28.

 The exit. 35 of comparator 7 is connected to a flip-flop 22. The output of flip-flop 22 is connected by a control line to comparator 23. Comparator 25 is connected to register 26 by a control line.

 For clarity of the figure, all the control lines have not been shown in FIG. 3. The direction of the arrows give the direction of the control, the same references represent the same control lines.

 The counter 6 is the counter for the number of pieces of information present in the stack 1. The counter 6 receives the control signals 49, 60 and 46. The counter 6 sends the control signal 61. The counter 6 is connected to the counter 19 by a bus 30. The stack 1 receives the control signals 45, 60, 46. The stack 1 transmits the control signal 31. The counter 19 counts the number of information present in the stack 2. The counter 19 receives the signals 50 and 62. The counter 19 transmits the signal 33. The stack 2 receives the signals 47 , 61 and 48. The register 103 receives the signals 59 and 48. The register 103 sends the signal 32. The multiplexer 4 receives the control signal 32. The register 3 receives the control signals 51 and 62. The interface 20 receives the control signal 34. The comparator 7 receives the signal 43 and transmits the signal 35. The flip-flop 22 receives the signals 35 and 62. The flip-flop transmits a signal 51 as well as a signal to the outside of the device of FIG. 3. The comparator 23 transmits the signal 36. The detector 24 transmits the signal 40. The comparator 25 transmits the signal 38. The register 26 receives the signals 55 and 54. The comparator 38 transmits the signal 37. The register 27 receives the signal 52. The counter 29 receives signals 56, 61 and 52. Comparator 29 transmits signal 39. The control device 5 receives signals 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43 and 44. The control device 5 transmits signals 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56 and 43. The control device 5 is for example programmable logic (PAL in English terminology). The device of Figure 3 also includes clocks not shown.

 When a polling device of the multiplexer 18 of FIG. 2 detects the availability of a packet at the output of one of the coders 15 it transmits on a bus 57 the information concerning the address and the priority assigned to this coder. This information is stored in the register 103. The register 103 allows good synchronization of the device of FIG. 3 with the rest of the multiplexer 18 (the scanning device is not shown in FIG. 3). The register 103 also receives a signal 58 indicating the instant of reception on the bus 57. The information 59 comes from a clock for recording the input data (clock not shown in FIG. 3). The register 103 transmits the synchronization signal 32 allowing the synchronization of the scanning on the bus 57.

 During the initialization of the device of Figure 3, the register 3 is empty. Comparator 7 is informed of this by signal 43. As long as register 3 is empty, comparator 7 is of the lower or equal type. When the register 103 transmits on the bus 8 the first information available, this information arrives in particular at the comparator 7. The comparator 7 emits a signal 35 for instantaneous comparison comparison which informs the control device 5 that the multiplexer 4 must be switched over to allow recording of the first information in the register 3. On the other hand the first information was recorded in the stack 1, the counter 6 of the stack 1 was incremented by one. The information present on the bus 8 has also been transmitted to the detector 21. The detector 21 detects whether the information present on the bus belongs to a group and / or is Isolated information. If the information present on the bus 8 belongs to a group, the detector 21 emits the signal 41 for the presence of an instantaneous group.

 Insofar as information is present in the register 3, the signal 43 switches the comparator 7 to the strictly upper position. Thus, when the register 103 delivers the second information, the comparator 7 does not deliver the signal 35 except in the case where the priority of the information present in the register 103 is higher than that present in the register 3 the information is entered in battery 1.

 Battery 1 receives an erase signal 60, a write signal 45 from the input register of battery 1, a read signal 46 from the input register of battery 1. Battery 1 emits a signal 31 signaling that the battery is empty.

 The stack 2 receives a signal 47 for writing the input register of the stack 2, a signal 61 for erasing the stack 2 and a signal 48 for reading the input register for the stack 2.

 The multiplexer 4 receives the synchronization signal 32 of 11 scanning moments synchronized by the signal 59.

 Register 3 receives a signal 51 for recording clock from register 3 and a signal 62 for erasing register 3.

 The interface 20 receives the order 34 to transmit the content of the register 3.

 The detector 21 emits the signal 41 as soon as a group of information A to be emitted arrives.

 The comparator 7 receives the signal 43 indicating that the register 3 contains information. Comparator 7 delivers a signal 35 indicating the result of the comparison between the priority level of register 103 and the priority level of the content of register 3.

 The flip-flop 22 receives the reset signal 62 from the register 3. The flip-flop 22 sends the signal 51 allowing the clock synchronization of a recording in the register 3.

 The comparator 23 emits a signal 36 indicating the result of the comparison, during the phase of analysis of the priority level of the value leaving the stack 2 and of the priority level of the information contained in the register 3.

 The detector 24 emits a signal 40 indicating the presence of a group on the bus 104. The comparator 25 emits a signal 38 indicating the identity of the content leaving the stack 2 and of the signal which has just been emitted by the interface 20. The signal 38 allows the erasure, for example by non-rewriting at the entry of the stack 2 of the information already transmitted.

 Register 26 receives a reset signal 55 from register 26 and a recording clock synchronization signal 54 from register 26.

 The comparator 28 emits a signal 37 result of the comparison between the address of a group in analysis and a group in shipment.

 The counter 29 receives a reset signal 61, a signal 56 indicating the pulses allowing the accounting of packets sent from a group> as well as a signal 52 for memorizing the number of packets of a group and the address of the group of the counter 29 in the register 27. The register 27 also receives the signal 52.

 In the preferred embodiment illustrated in FIG. 3, the device according to the invention receives on the bus 57 the information coming from the encoders 15 of FIG. 2.

The information includes the address of the coder 15, the priority of the packet to be sent and the type of packet. The age of the information is determined from the information of the time of arrival of the information in the device of FIG. 3 and / or from its position in the stack 1 and / or in the stack 2.

 On initialization. counters 6 and 19 are reset. At this time, there is no information in the register 3. In such a case, the instant comparator 7 systematically determines that the priority of the first information is higher than that stored in the register 3.

This information is stored in the register 3 via the multiplexer 4.

 From this moment the and Until the first transmission of a packet requested by the multiplexer 17 of FIG. 2, in the register 3 must be found the oldest information having the highest priority. In fact, each time that information is available on the bus 57, its priority will be compared by the comparator 7 to that of the information found in the register 3. If the priority of a processed packet is higher than that of the packet corresponding to the information in register 3, this information is entered by means of the multiplexer 4 in register 3. However, insofar as more priority information risks being available on bus 57, and therefore being entered in the register 3 the information received in the stack 1 is written. Thus, in the event of a new entry in the register 3, the loss of information concerning the packet corresponding to the information previously stored in the register 3 is avoided. Thus, at the time of transmission, it is certain to have in the register 3 information containing the address of the coder 15 having the information of highest priority available for the longest time. After transmission it is imperative to determine which is the new packet to be transmitted.

We are entering the analysis phase.

 The flip-flop 22 makes it possible to switch the comparator 7 to an initialization mode or to an instantaneous mode.

 In the initialization mode, the first available information is placed in register 3.

 In the instant mode, information available on the bus 57 is placed in the register 3 only if its priority is higher than that of the information contained in the register 3.

 The counter 6 indicates the sum of the number of pieces of information stored in stack 1 and the number of pieces of information stored in stack 2.

 At the start of the analysis phase, after sending data, the contents of stack 1 are transferred to stack 2.

 The value of counter 6 is stored in counter 19. Counter 6 is not deleted. If during the analysis phase a new value is stored in the stack 1 the counter 6 is incremented. As the analysis phase takes place the counter 19 is decremented. In the exemplary embodiment illustrated in FIG. 3, the content of register 3 is recorded at the time of transmission in register 26.

Then, before each transfer between the stack 1 and the stack 2, it is checked in the comparator 25 that the information to be transferred is not equal to the content of the register 26 corresponding to a transmission which has already been carried out. The deletion is carried out during the analysis following a transmission. The information in stack 2 which is equal to the information previously transmitted is no longer rewritten in stack 2 and the counter 6 which totals the number of information contained in stack 2 and in stack 1 is decremented by 1. During the analysis phase the comparator 23 compares for all the information stored in the stack 2 the priority level with the priority level of the information s stored in the register 3. In all cases the information is rewritten at the input of the stack 2. In the case where the information has a strictly higher priority, it is entered via the multiplexer 4 in the register 3.

 If during the analysis phase information arrives on the bus 57, this information is processed in instant mode by the comparator 7. If the priority of the information present on the bus 57 which is stored in the register 103 is higher than that contained in register 3 it is stored in register 3 in place of the previous information. In all cases the new information received is stored in stack 1. The new information contained in stack 1 is transferred at the end of the analysis phase in stack 2. In all cases the new information contained in stack 1 are transferred to the end of the analysis in the stack 2. At this time the content of the counter 6 is loaded into the counter 19 which then indicates the number of total items of information to be analyzed in the stack 2. At each item of information analyzed the counter 19 is decremented and when it reaches zero, the analysis phase is completed. If during this analysis an item of information is compared identical to that contained in the register 26 by the comparator 26, the latter is erased, not rewritten in stack 2 and the counter 6 is decremented.

Advantageously, the device according to the present
The invention makes it possible to process groups of successive packets.

 The transition from analysis to instantaneous phase is activated by signal 32.

 Shipping and erasure cause the corresponding counters to be updated.

 The detector 21 detects the presence of a group in instant phase. If there is a group, the detector 21 emits a signal 41. The counter 29 counts the elements of the group treated.

The detector 24 detects the presence of a group in the analysis phase. In the case where a group is in the analysis phase, the detector 24 transmits the signal 40. The address of the group being processed is stored in a register 27. The comparator 28 compares to a processed packet belongs or not to the group in Classes. If yes it emits a signal 37. For example if we are in the presence of a standard using the rule of non-interlacing of packets belonging to the group that is to say that if a group is in forwarding and that packets coming from another group cannot be inserted even if they have higher priority. On the other hand, the higher priority single packets can be inserted in the group.

 Advantageously, when an encoder 15 in FIG. 2 has a group of packets to be sent, it presents only one piece of information to the device in FIG. 3. It is the rattle of the counter 29 to determine whether the group has been entirely dispatched or not. . During the dispatch of a group, the address of the coder 15 of FIG. 2 is stored as smoothly in the register 27 as in the register 26 to allow its erasure. The information concerning the group in transmission is kept in stack 2 Until the last packet sent. Each transmission of a packet decrements the counter 29 by one unit which thus reaches zero at the last packet, deactivates the signal 39 and allows the erasure of the information concerning the group emitted from the stack 2. This erasure will take place during the next analysis phase. During all the dispatch of a group all the information concerning a higher priority group will be blocked by signals 41 and 40.

 It is understood that the invention is not limited to the management of the priorities of the sound packets in a transmission device according to the D2 MAC Packets standard. It covers the entire transmission of information with priority management.

The architecture of the priority management system could be reorganized according to the adapted priority criteria. The device according to the present invention allows for example transmissions on a synchronous or asynchronous bus, transmissions on a local network on the transmission device such as for example telephone lines or radio-relay systems.

 The device of Figure 3 is made with commercial components. The control device 5 is for example made with two programmable logic boxes (PAL in English terminology), the first in, first out type batteries use two boxes each. The device of FIG. 3 is for example produced in the form of a printed circult occupying half of a map in Europe format.

In an exemplary embodiment, it is capable of processing 4,096 events, each priority being processed in 100 ns, the analysis calls for around 410 Clos.

 The invention applies to priority management.

The invention mainly applies to the management of priorities in television programs and to the production of television programs using priority management.

Claims (11)

 1. Priority management device in the transmission of information, characterized in that it comprises a first stack (1) of first in, first out (FIFO) type connected to a second pfle (2) of first in, first type output (FIFO), the second stack being connected to a first input of a multiplexer (4), the input of the first stack (1) being connected to a. firstly to a comparator (7) and secondly to a second input of the multiplexer (4).  2. Device according to claim 1, characterized in that it comprises a counter (6) capable of indicating the number of data stored in the first stack (1) and the second stack (2).  3. Device according to claim 1 or 2> characterized in that it comprises a logic control device.  4. Device according to claim 1,2 or 3, characterized in that it comprises a register (3) connected to the output of the multiplexer (4).  5. Device according to claim 1,2,3 or 4, characterized in that it comprises a comparator (25) of which a first input is connected to the output of the first battery (1) and the second output is connected either directly either through a register (26) to the register (3) connected to the output of the multiplexer (4), the comparator (25) emitting a control signal (38) inhibiting the transfer of data already processed from the first stack (1) On the second battery (2).  6. Priority management device according to any one of the preceding claims, characterized in that said device is a device for priority management of information transmission for a television broadcast.  7. Device according to claim 6, characterized in that the priorities of the information processed relate to sound and / or data in television broadcasts carried out according to MAC standard.  8. Device according to claim 1,2,3,4 or 5, characterized in that said device is a device for managing priority of data transmission on a bus of a computer or on a local network connecting a plurality of computers.  9. Transmitter of television programs, characterized in that it comprises a priority management device according to claim 1,2,3,4,5,6 or 7.  10. Method for managing the priority of information to be sent, the information being sent according to their priority level, and for the same priority according to their order of availability, characterized in that it comprises a first step of instantaneous storage of information concerning the data to be sent, this storage being carried out in a first stack (1) of the first in, first out (FIFO) type, a second analysis step making it possible to determine which information is to be sent and a step of transmission of the information determined during the analysis step.  11. Method according to claim 10, characterized in that the information to be transmitted is presented in a group, the emission of a group having a lower priority level is not interrupted by the availability of information belonging to a group having a higher priority level, but is interrupted by isolated information having a higher priority level.