JPH0523096B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a loop transmission method for performing packet communication between terminals in a loop transmission system having a plurality of transmitting/receiving terminals and one control terminal connected in a loop.

Conventionally, a time division multiplexing method that employs a frame structure is known as a communication method for a network in which voice terminals and data terminals coexist. This method is suitable for voice because it guarantees real-time performance, but it is not suitable for data because it cannot easily accommodate data terminals with various speeds and cannot accommodate high-speed data terminals. Not suitable.
As another method, a packet multiplexing method focusing on data has been proposed. This method allows for a flexible system configuration suitable for various speed terminals for data, but for voice there is a delay depending on the line activity.
It is not very suitable because real-time performance is not guaranteed. Note that another type of signal having real-time characteristics is a moving image signal. In the following explanation, unless otherwise specified, real-time signal packets and voice packets will be treated as synonyms. As a method to improve these two methods, as shown in FIG.
is divided into two subframes by setting a boundary to
One subframe 101 is used as a time-division subframe for audio, and the other subframe 102
A method has been proposed in which the subframe is used as a subframe for packet multiplexing. However, this method has the drawback that efficiency decreases when voice and data traffic is biased to one side. That is, for example, in a situation where voice traffic is high and data traffic is low, even if there is an empty subframe for data, voice cannot use it, resulting in a decrease in efficiency. In order to eliminate this drawback,
A method of adaptively moving the boundary of the frame 100 according to the traffic condition is proposed by ITriple E Transactions on Communications Volume COM-29, Number 6,
John, 1981 (IEEE Transactions on
Communicatinos June 1981 VOL.COM−29
No. 6) B. Maglaris (B.
Maglaris) and M.Schwartz
“Performance Evaluation of a Variable Frame Multiplexer for Integrated Switched Networks” by “Performance Evaluation of a Variable Frame Multiplexer for Integrated Switched Networks”
Evaluation of a Variabla Frame
Multiplexer for Integrated Switched
However, the method described in this document requires a central control terminal that monitors the traffic status, which has the drawback of making control extremely complex. .

Furthermore, as a method for efficiently transmitting and receiving voice and data signals via a loop-shaped transmission path, the IEEE Transactions on Communications Volume COM-22, No. 6, John, 1974 (IEEE Transactions on
Communications VOL.COM−22 No.6 June
E.R. Hafner (1974)
“A Digital Loop Communication System” (“A Digital Loop Communication System”) by Hafer et al.
A register insertion method described in a paper titled "Loop Communication System" is known.

FIG. 2 is a basic block diagram of a transmitting/receiving terminal using this register insertion method. This is transmit register 20
3. Receive register 202 and switch 204
The basic structure consists of the following. This register insertion method has the characteristics that packet transmission can be performed with almost no waiting time regardless of the degree of loop congestion, and exchange control can be completely distributed.
Furthermore, the data transfer time including the waiting time at the terminal is short and the throughput characteristics are good. However, the transfer time of this register insertion method depends on the degree of loop congestion and has a large variation, making it unsuitable for voice communication.

SUMMARY OF THE INVENTION An object of the present invention is to provide a loop transmission system capable of transmitting real-time signals and data with good consistency through efficient and easy control by eliminating the drawbacks of the conventional system described above.

According to the present invention, high priority is given to real-time signal packets and low priority is given to data packets, and packets with high priority are processed within the transmitting and receiving terminals according to the priority so that there is no delay when passing through the transmitting and receiving terminals. Performs communication path control. In this way, since real-time signal packets do not experience any delay when passing through the transmitting and receiving terminals, as the traffic of real-time signal packets increases, the amount of delay in data packets increases. In order to reduce the amount of delay in this data packet, the transmission of real-time signal packets is controlled according to system activity detected using control packets that are exchanged prior to the transmission of real-time signals. A multi-information complex loop transmission system including activity control that efficiently accommodates real-time signal packets and data packets in a system is obtained.

Next, the principle of the present invention will be explained with reference to FIG. In FIG. 3, the transmitting/receiving terminal has an input buffer memory 302 and an output buffer memory 30.
3 and a block 304 having a circuit for decoding packet addresses, a priority determination circuit, and a receiving circuit.
and a switch 305 for selecting a communication path within the terminal.
Detector 30 for detecting system activity
It consists of 6. Each terminal of the switch 305 is assigned a number 1, 2, or 3 as shown in the figure. The signal on signal line 352 is sent to switch 3
05, and the signal line 350 signal indicates a transmission signal from the terminal. Also, signal line 351
The signal indicates the received signal of the terminal. Reference numeral 306 denotes an activity control circuit, which outputs system activity to the signal line 353 and performs control during real-time signal transmission. First, a priority control method for data terminals will be described. The control method when a data packet is input to the output buffer memory 303 and a transmission request occurs is as follows.

(1) When a packet with a higher priority than the data packet that has been requested to be transmitted is input from the transmission path 300 or is about to be output from the input buffer memory 302: The data packet that has been requested to be transmitted is sent to the output buffer memory 303. It remains stored and is not output to the transmission path. Switch 305 is transmission line 3
It operates to pass the packet with higher priority between the packet input from 00 and the packet about to be output from the input buffer memory 302. If the priorities of the above two packets are equal, input buffer memory 3
Packets output from 02 are given priority.

(2) When a packet with a priority lower than the data packet for which a transmission request has been made is input from the input transmission line 300 or is about to be output from the input buffer memory: The data packet for which a transmission request has been made is sent to the output buffer memory 303. The input packets from the input transmission line 300 are stored and saved in the input buffer memory 302.

Next, the control after the transmission of the transmission data packet is completed is as follows.

(1) When the packet input from the input transmission path 300 has a higher priority than the packet stored in the input buffer memory 302 (packet waiting for output): The packet waiting for output stored in the input buffer memory 302 is Packets input from the transmission line while being stored are sent to the output transmission line 30.
The switch 305 is controlled so that the signal is sent to 1.

(2) When the priority of the next packet input from the transmission path is lower than the priority of the packet waiting for output in the input buffer memory 302: The packet waiting for output stored in the input buffer memory 302 is sent to the transmission path 301. The input packets input from the transmission path 300 are stored in the input buffer memory 302.

The above control is also applied to input packets from subsequent transmission paths, and in extreme cases, if audio packets (with high priority) continue in succession, the data packets stored in the input buffer memory 302 will be Although voice packets remain stored in the input buffer memory 302, they are not saved in the input buffer memory in the terminal because they have the highest priority. In this way, voice packets are not saved in the input buffer memory within the terminal, so when the activity of voice packets increases, the delay of data packets increases, resulting in unfairness between different types of packets. In order to eliminate this problem and accommodate voice packets and data packets with good consistency, the transmission of voice signals is controlled by system activity. The method for detecting this system activity will be explained next. Prior to sending the audio packet,
Transmission request packets (REQ packets) and acknowledgment/denial packets (ACK/ACK) are exchanged for communication procedures between the sending terminal and the receiving terminal.
Two types of fields are provided in the NCK packet: a data packet activity field and an audio packet activity field. When a REQ packet sent from the sending terminal to the receiving terminal passes through the transmitting/receiving terminal between the transmitting terminal and the receiving terminal, an active transmitting/receiving terminal (transmitting/receiving terminal that is transmitting a data packet or a voice packet) ) increases the value of the data packet activity field by 1 if a data packet is being sent, and increases the value of the voice packet activity field by 1 if a voice packet is being sent. When the REQ packet arrives at the receiving terminal, the receiving terminal sends an ACK packet and an NCK packet to the transmitting terminal depending on the state of the receiving terminal at that time.
At this time, the data packet activity field and voice packet activity field of the REQ packet are copied into the ACK/NCK packet. When an ACK/NCK packet passes through the transmitting/receiving terminal between the receiving terminal and the transmitting terminal, the active transmitting/receiving terminal changes the data packet activity field to the voice packet activity field, just as in the case of the REQ packet above. This increases the value of the field by 1. In this way, when an ACK/NCK packet is returned to the transmitting terminal, the activity of all transmitting and receiving terminals accommodated in the loop can be seen in the data packet activity field and voice packet activity field. . An activity detection circuit 306 detects this activity, and informs the information source via a signal line 353 whether audio packets can be transmitted.

3 with reference to the two examples in Figures 4 and 5.
The control means of the circuit shown in the figure will be explained.

In FIG. 4, each rectangular box represents one packet, and the alphanumeric characters within the rectangular box represent the packet name. The English letter V indicates a voice packet, and D
indicates a data packet. Here, it is assumed that voice packets have a higher priority than data packets, and all data packets have the same priority. Now, if _a request to send a _D3 packet occurs at the point indicated _{by the} arrow in FIG. The switch 305 is selected so that the _D3 packet is output to the transmission line 301 instead. Fourth
FIG. 4B is a diagram showing the state of the output transmission path at the time when one packet time has elapsed from FIG.
_The next packet to be input from the transmission line 300 is the voice packet _V2 , and since the voice packet _V2 has a higher priority, D1 is stored in the input buffer memory 30.
The switch 305 is activated so that the voice packet _V2 is sent to the output transmission line 301 while being stored in the voice packet V2.
is controlled. Next, in FIG. 4c after one packet time has elapsed, the packet _D1 stored in the input buffer memory 302 is transferred to the transmission path 300.
The input packet from V ₁ is again a voice packet.
Therefore, the voice packet V ₁ remains stored in the input buffer memory 302 and is transferred to the output transmission path 3.
The switch 305 is controlled so that the signal is sent to 01. In FIG. 4D, where _one packet time has elapsed from FIG. switch 3 to be
05 is controlled. In FIG. 4e, packet D ₁ is output to the transmission line 301 and the packet input from the transmission line 300 is an empty packet, and there are no transmission request packets or packets stored in the input buffer memory 302 waiting to be output. So,
A switch 305 is controlled to directly connect the input transmission line and the output transmission line.

The control procedure of the circuit shown in FIG. 3 will be explained using the example shown in FIG. Now _, if a request to transmit packet D ₃ occurs at the point indicated _{by the} arrow in FIG. The switch 305 is controlled so that the _D3 packet is output to the transmission path instead. In FIG. 5b, since the packet input from the transmission line 300 is an empty packet, the switch 305 is controlled so that the packet _D1 stored in the input buffer memory 302 is sent to the output transmission line 301. Ru. In FIG. 5c, since the packet input from the transmission path 300 is a voice packet _V1 , the switch is controlled to directly connect the input transmission path 300 and the output transmission path 301, and the data packet _D1 and the voice packet V ₁ means continuous packets as shown in the figure. As is clear from the examples in FIGS. 4 and 5, data packets may be preempted by voice packets, increasing the delay, but voice packets are not delayed at the terminal. That is 1
After that, the voice packets sent to the transmission path arrive at the other party's terminal without any delay due to buffer memory.

Next, the transmission control based on the system activity of voice packets will be explained. Let us now assume that the total number of transmitting and receiving terminals in the system is N, and that the transmission path speed is C packets/second. Further, the transmission rate of voice packets is assumed to be V packets/second, and the transmission rate of data packets is assumed to be D packets/second. (For simplicity,
The rates of data packets and voice packets sent from each transmitting and receiving terminal are all constant. ) Now, if the number of active transmitting/receiving terminals transmitting data is N _D and the number of active transmitting/receiving terminals transmitting voice is N _V , the system activity A _S is A _S = N _D・D + N _V・It becomes V/C. At this time, as an example, if the following conditions are met, audio transmission is possible.

When A _S <1.

When A _S ≧1, when N _D・D/C<1/2.

The above example is just an example; the number of voice terminals,
Conditions may vary depending on the number of data terminals, the call loss rate required of voice terminals, the maximum amount of data delay, etc. Changes in conditions due to these external factors are included in this method.

An embodiment for implementing the method of the present invention will be described below with reference to the drawings.

FIG. 10 is a diagram showing the basic configuration of the system.
In the figure, signals flow in the direction indicated by the arrow on transmission line 1000. The control terminal 1001 periodically sends out a signal indicating the starting position of a packet when transmitting a packet between each transmitting/receiving terminal 1002(1) to 1002(N), and also so that the loop transmission delay is an integral multiple of the packet length. Establish loop synchronization. Each transmitting/receiving terminal is connected to various devices.

FIG. 6 shows an example of a packet structure used in the system of FIG. 10. FIG. 6a shows an information data packet, and FIG. 6b shows an example of the structure of a control packet. In the figure, M indicates a marker bit; "1" indicates a used packet, and "0" indicates an empty packet. I is a bit representing the type of packet; "1" represents an information data packet, and "0" represents a control packet. P indicates priority information;
Assign a numerical value corresponding to the type of priority of the information source to be accommodated in the system. AD1 is sending address information and AD2 is receiving address information. The field indicated by D indicates an information field. Also, K
is the type of control packet (for example, REQ packet,
ACK packet, NCK packet, etc.), DF indicates data packet activity field, and VF indicates voice packet activity field. As shown in AX, the remaining portion of the control packet can also be used as an auxiliary information field.

FIG. 7 shows an embodiment of a transmitting/receiving terminal used in the system of FIG. 10. In FIG. 7, an input packet from an input transmission line 701 is applied to a shift register 703. The shift register 703 has a serial input terminal and two types of output terminals, serial and parallel, and has the same length as the header length of one packet. The header information of the shift register 703 is output from the parallel output terminal to the signal line 751 as parallel information. The received address of the header information is given to an address matching circuit 705, and the marker bit and priority information are input to a priority selection circuit 704. When the input packet passes through shift register 703, it will be subject to a delay corresponding to the header length. The address matching circuit 705 is easily constituted by an exclusive OR gate, and compares the received address of the input packet with the address of the terminal, and outputs a match/mismatch signal to the signal line 755. The address match/mismatch signal on the signal line 755 is supplied to the activity control circuit 711 and the return circuit 707, and is also notified to the information source generating terminal. If the receiving address and the terminal address match, the input packet is a packet to be received by the terminal, so the marker bit of the input packet is erased,
It must be an empty packet. Therefore, the address matching circuit 705 sends the marker erase signal to the signal line 7.
52. A marker erase signal on signal line 752 erases the marker bit in the header information stored in the shift register. The priority selection circuit 704 selects the marker bits and priority information of the input packet given via the signal line 751, the marker bits and priority information of the output waiting packet accumulated and saved in the input buffer memory 706, and the output buffer memory 708. A signal for selecting a priority packet based on the marker bits and priority information of the sending packet given from the input/output buffer memory and a status signal representing a control signal for the input/output buffer memory are output to the signal line 756. A conversion circuit 707 converts the packetized signal into an information signal suitable for various devices connected to the terminal.
That is, the conversion circuit 707 receives an input packet from the signal line 750, and if the output signal of the address matching circuit on the signal line 755 is a match signal, it sends an information signal to various devices connected to the data terminal via the signal line 757. Send. Reference numeral 711 is an activity control circuit that detects a control packet from the bit representing the type of packet of header information coming from the signal line 751, and detects a control packet addressed to a terminal other than the transmitting/receiving terminal from the address matching information coming from the signal line 755.
Based on the signal input from the signal line 763 indicating the status of the transmitting/receiving terminal, if the transmitting/receiving terminal is sending data, the value of the data packet activity field in the header information is increased by 1, and the audio is output. If it is being sent, increase the value of the audio packet activity field by 1 and connect the signal line 764.
Return via. Furthermore, if the control packet has gone through the loop addressed to the transmitting/receiving terminal based on the address matching information coming from the signal line 755, the system activity can be determined from the data packet activity field and voice packet activity field of the control packet. A signal indicating whether the audio signal can be transmitted or not is output to the signal line 762. Information signals from various devices connected to this transmitting/receiving terminal are inputted to the packetization circuit 709 via a signal line 758, where they are given header information and converted into packets of a predetermined size. It is output on line 759. The signal on the signal line 759 is stored in the output buffer memory 708 and waits to be sent to the transmission line via the signal line 760. Whether or not the transmission line can be transmitted via the signal line 760 is controlled by the status signal of the signal line 756. Of the header information of the outgoing packet stored in the output buffer memory 708 and waiting to be sent out to the transmission line next, marker bits and priority information are output to the signal line 754.
The input buffer memory 706 temporarily stores and saves packets that are not sent to the output transmission path by the switch 710 among the input packets from the signal line 750. Whether data can be stored or saved in the input buffer memory 706 and whether it can be transmitted from the input buffer memory 706 to the output transmission path 702 is controlled by a state signal on the signal line 756. Among the header information of delayed packets stored in the input buffer memory 706, marker bits and priority information are transferred to the signal line 753.
is output to. The switch 710 is configured to select the packet with the highest priority among the input packet from the signal line 750, the delayed packet from the signal line 761, and the outgoing packet from the signal line 760, using a status signal from the signal line 756. controlled.

FIG. 8 shows the priority selection circuit 704 shown in FIG.
FIG. In the figure, signal line 850
and 851 are the output buffer memory 708 in FIG.
Marker bits and priority information are shown on signal line 754 outputted from signal line 85.
2 and 853 indicate marker bits and priority information output from the input buffer memory 706, and signal lines 854 and 855 indicate marker bits and priority information of input packets from the transmission path. AND gate circuits 801 and 802 input the marker bit and each bit of the priority information are ANDed and output to signal lines 856 and 857, respectively. For example, if the marker bit is "1", the output signal of the AND gate circuit is the same as the input priority information, and if the marker bit is "0", the output signal of the AND gate circuit is all zero. In addition to the marker bit and the priority information, the AND gate circuit 803 receives an address match signal from the signal line 755, and performs a logical product of the address match signal, the marker bit, and each bit of the priority information. For example, the address match signal on the signal line 755 is “1”
(i.e., the received address of the input packet and the terminal address do not match) and the marker bit is "1", the signal on the signal line 858 is the same as the input priority information, and the address match signal is "0" (i.e., the terminal address of the input packet does not match). If the receiving address and terminal address match) or the marker bit is “0”, the signal line 858
All signals become 0. Signal lines 856, 857,
Each signal 858 is input to the highest priority detection circuit 804, and the code indicating the highest priority input is output as a 2-bit signal to the signal line 859 while maintaining the same state for one packet time. The signal on the signal line 859 becomes a control signal for the switch 710 in FIG. 7 and an output control signal for the input/output buffer memories 706 and 707.
The signal indicating the marker bit of the input packet on the signal line 854 and the signal on the signal line 859 are sent to the gate circuit 80.
5 and an input packet exists (signal line 8
If the switch is not selected so that the signal on the signal line 859 sends the input packet to the output transmission line (marker bit 54 is "1"), the signal on the signal line 859 instructs the input packet to be stored in the input buffer memory 706 in FIG. Output. Signal lines 859 and 860
The signal corresponds to the signal on signal line 756 in FIG.

FIG. 9 shows an example of the circuit configuration of the activity detection circuit shown at 711 in FIG. signal line 9
The data packet sending bit input from 55, the control packet bit indicating that the input packet from the transmission line input from signal line 956 is a control packet, and the address match bit input from signal line 957 are inverted by inverter 909. The three address mismatch bits on signal line 958 are logically ANDed by AND gate 907 and output to signal line 960.
It is output to the counter 901 and becomes one input of the counter 901.
Further, the data packet activity field in the header information of the input packet coming from signal line 951 becomes the other input of counter 901, and the sum of the two is calculated and output to signal line 953. That is, if the signal on signal line 960 is 1, the signal on signal line 953 will be the value of the data packet activity field in the header information increased by 1. Both the data packet activity field signal changed depending on the input packet or terminal state on the signal line 953 and the original data packet activity field signal on the signal line 951 are input to the selector 903. The selector 903 operates to select the signal on the signal line 953 when the signal on the signal line 960 is 1, and selects the signal on the signal line 951 when the signal on the signal line 960 is 0. Output on line 964. The signal on signal line 964 is returned as the data packet activity field of the new header information of the input packet. The signal on signal line 959 is the audio packet sending bit, and the signal on signal line 952 is the audio packet activity field in the header information of the input packet, and is similar to changing the data packet activity field described above. A counter 902 and a selector 904 operate. Therefore, the audio bucket activity field of the new header information of the input bucket is output to the signal line 965 and returned to the input bucket. The latch 905 latches the data bucket active field signal and the audio bucket active field signal on the signal line 951 and signal line 952 when the address match bit on the signal line 957 comes.
Output to signal line 962. The signal on the signal line 962 indicates the activity of all the transmitting and receiving terminals detected after going around the loop, and is input to the determination circuit 906, which determines whether the audio signal can be transmitted or not, and sends it to the signal line 963. Output.

As described above, in the present invention, by giving a high priority to voice buckets and a low priority to data buckets, voice buckets having a high priority can be sent without delay. Also, according to the invention, control is completely decentralized. In addition, system activity can be set to REQ, ACK/
It is detected during the communication procedure when transmitting audio signals using the NCK bucket, and the system status can be observed efficiently. By controlling the transmission of audio signals based on such system activity, both data packets and audio packets can be accommodated in the system with good consistency.

Note that although the above explanation has been made for buckets with two types of priorities: audio buckets and data buckets, the present invention includes further subdivision of priorities depending on the nature of the information source. Of course.

[Brief explanation of the drawing]

Fig. 1 is a frame configuration diagram in which one frame is divided into a time division subframe and a bucket multiplexing subframe, Fig. 2 is a basic block diagram of a transmitting/receiving terminal using the register insertion method, and Fig. 3 is a basic transmitting/receiving terminal of the present invention. Block diagrams, Figures 4a-e and 5a-c
is a timing chart for explaining the transmission method of the present invention, FIG. 6 is a conceptual diagram showing a configuration example of a bucket used in the present invention, and FIG. 7 is a configuration diagram showing a transmitting/receiving terminal according to an embodiment of the present invention. , FIG. 8 is a block diagram showing an embodiment of the priority selection circuit used in FIG. 7, FIG. 9 is a block diagram showing an activity control circuit used in FIG. 7, and FIG. 10 is a block diagram showing an embodiment of the priority selection circuit used in FIG. 1 is a block diagram showing a system configuration to which the invention is applied. In the figure, 200...input transmission line, 201...
...Output transmission line, 202...Reception register, 203
...Transmission register, 204 ...Switch, 300
...Input transmission line, 301...Output transmission line, 302
...Input buffer memory, 303...Output buffer memory, 304...Priority determination circuit, 30
5... Switch, 306... Activity control circuit, 701... Input transmission line, 702... Output transmission line, 703... Shift register, 704...
Priority selection circuit, 705...address verification circuit,
706...Input buffer memory, 707...Conversion circuit, 708...Output buffer memory, 709
... Bucket conversion circuit, 710 ... Switch, 71
1...Activity control circuit, 801, 80
2,803...AND circuit, 804...Top priority detection circuit, 805...Gate circuit, 901,90
2...Counter, 903,904...Selector,
905... Latch, 906... Judgment circuit, 90
7,908...AND gate, 909...Inverter, 1000...Transmission line, 1001...Control terminal, 1002(1) to 1002(N)...Transmitting/receiving terminal.

Claims (1)

[Claims] 1. In a loop transmission method that has multiple transmitting/receiving terminals and one control terminal and connects these terminals in a loop to perform packet communication between each transmitting/receiving terminal, the former control terminal transmits a signal indicating the leading device of the packet. Loop synchronization is established so that the transmission path delay when transmitting periodically and going around the loop is an integral multiple of the length of the packet, and real-time information is required among the information packets from the transmitting and receiving terminals. A high priority is given to the first information packet that requires real-time performance, a low priority is given to the second information packet that does not require real-time performance, and the input packets from the input transmission path are stored and saved in each transmitting/receiving terminal. and a second storage means for storing packets sent from an information generating device connected to the transmitting/receiving terminal; A priority comparison is made between the delayed packet and the sending packet, and the packet with the highest priority is sent to the output transmission path, and the packet is sent from the first transmitting/receiving terminal to the first sending packet.
When transmitting a real-time information message consisting of a plurality of information packets to a second transmitting/receiving terminal, a first control packet is transmitted to the second transmitting/receiving terminal prior to transmitting the real-time information message. When the second transmitting/receiving terminal receives the first control packet, it copies the first and second control fields in the packet to the corresponding control fields of the second control packet, and transfers the second control packet to the second control packet. The control packet is sent back to the first transmitting/receiving terminal through the opposite side of the loop, and among the transmitting/receiving terminals on the loop, the transmitting/receiving terminal that is transmitting the first information packet passes the first or second control packet. When the value of the first control field in the control packet is set to 1.
The transmitting/receiving terminal that is sending the second information packet increases the value of the second control field in the control packet by 1 when the first or second control packet passes, and the loop The respective activities of the real-time information packet and the data packet are detected from the first and second control fields of the second control packet that has returned to the first transmitting/receiving terminal after completing one cycle, and the detected activity is determined in advance. A multiple information complex loop transmission system including activity control, wherein the first transmitting/receiving terminal starts transmitting the real-time information message when a predetermined condition is satisfied.