JPH0442860B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a loop transmission method for performing packet communication between terminals in a loop transmission system having a plurality of transmitting/receiving terminals and one control terminal connected in a loop.

Conventionally, a time division multiplexing method that employs a frame structure is known as a communication method for a network in which voice terminals and data terminals coexist. This method is suitable for voice because it guarantees real-time performance, but it is not suitable for data because it cannot easily accommodate data terminals with various speeds and cannot accommodate high-speed data terminals. do not have. As another method, a packet multiplexing method focusing on data has been proposed. This method is compatible with various speed terminals for data and allows for flexible system configurations, but for voice there is a delay depending on line activity and real-time performance is not guaranteed. Therefore, it is not very suitable. Note that another type of signal having real-time characteristics is a moving image signal. In the following explanation, unless otherwise specified, real-time signal packets and voice packets will be treated as synonyms. As a method to improve these two methods, one frame 100 is divided into two subframes by setting a boundary as shown in Fig. 1, and one subframe 101 is used as a time-sharing subframe for audio. However, a method has been proposed in which the other subframe 102 is used as a subframe for packet multiplexing. However, this method
It has the disadvantage that efficiency decreases when data traffic is biased to one side. That is, for example, in a situation where voice traffic is high and data traffic is low, even if there is an empty subframe for data, voice cannot use it, resulting in a decrease in efficiency. In order to eliminate this drawback, a method of adaptively moving the boundary of the frame 100 according to the traffic condition is proposed by ITRIB Transactions on Communications Volume COM-29, Number 6, June,
1981 (IEEE Transactions on Communi−
“Performance Evaluation of a Variable Frame Multiplexer” by B. Maglaris and M. Schwartz published in June 1981VOL.COM-29No.6) Performance Evaluation of a
Variable Frame Multiplexer for Integrated
However, the method described in this document requires a central control terminal that monitors the traffic status, so it has the disadvantage that control becomes extremely complex. There is.

Furthermore, as a method for efficiently transmitting and receiving voice and data signals via a loop-shaped transmission path, the IEEE Transactions on Communications Volume COM-22, No. 6, John, 1974 (IEEE Transactions
on Communications VOL.COM−22No.
6June1974) E.R. Hafner (E.
“A Digital Loop Communication System” by R. Hafer) et al.
The register insertion method described in the paper titled "Communication System" is known.Each terminal to which this register insertion method is used consists of transmitting/receiving registers 202, 203 and a switch 204, as shown in FIG. This register insertion method is
It has the characteristics of being able to transmit packets with almost no waiting time and completely distributing exchange control. Furthermore, the data transfer time including the waiting time at the terminal is short and the throughput characteristics are good. However, the transfer time of this register insertion method depends on the congestion of the loop and has a drawback that it is not suitable for voice communication because of large variations.

SUMMARY OF THE INVENTION An object of the present invention is to provide a loop transmission system capable of transmitting real-time signals and data with good consistency through efficient and easy control by eliminating the drawbacks of the conventional system described above.

According to the present invention, real-time signal packets are given high priority, data packets are given low priority, and packets with high priority are sent to transmitting and receiving terminals according to their priority so that there is no delay when passing through each transmitting and receiving terminal. Controls communication channels within the network. Furthermore, when transmitting real-time signals so that the delay amount of data packets does not increase excessively, the amount of traffic that passes through the terminal during the repeated transmission period of high-priority real-time signal packets must be reduced prior to transmission. By controlling the transmission of real-time signals based on the observed and obtained amount of passing traffic, a multi-information complex loop transmission system including traffic control that transmits real-time signal packets and data packets with good consistency can be obtained.

Next, the principle of the present invention will be explained with reference to FIG. In FIG. 3, the transmitting/receiving terminal has an input buffer memory 302 and an output buffer memory 30.
3 and a block 304 having a circuit for decoding packet addresses, a priority determination circuit, and a receiving circuit.
and a switch 305 that selects the communication path within the terminal.
and a detector 306 that detects the amount of passing traffic. Each terminal of the switch 305 is assigned a number 1, 2, or 3 as shown in the figure. The signal on the signal line 352 is sent to the switch 305
The signal on signal line 350 indicates a transmission signal from the terminal. Further, a signal on a signal line 351 indicates a received signal of the terminal. First, a priority control method for data terminals will be described. The control method when a data packet is input to the output buffer memory 303 and a transmission request occurs is as follows.

1) When a packet with a higher priority than the data packet for which the transmission request was made is input from the transmission line 300 or is about to be output from the input buffer memory 302: The data packet for which the transmission request was made is accumulated in the output buffer memory 303. It remains unchanged and is not output to the transmission path. Switch 305 is transmission line 3
It operates to pass the packet with higher priority between the packet input from 00 and the packet about to be output from the input buffer memory 302. If the priorities of the above two packets are equal, input buffer memory 3
Packets output from 02 are given priority.

2) When a packet with a priority lower than the data packet requested to be transmitted is input from the input transmission line 300 or is about to be output from the input buffer memory: The data packet requested to be transmitted is sent from the output buffer memory 303. The input packets are sent to the output transmission path 301 and input from the input transmission path 300 are stored and saved in the input buffer memory 302.

Next, the control after the transmission of the transmission data packet is completed is as follows.

1) When the packets input from the input transmission path 300 have a higher priority than the packets stored in the input buffer memory 302 (packets waiting for output): The packets stored in the input buffer memory 302 and waiting for output are The switch 305 is controlled so that the packets input from the transmission path are sent to the output transmission path 301 while the transmission path remains unchanged.

2) When the priority of the next packet input from the transmission path is lower than the priority of the packet waiting for output in the input buffer memory 302: The packet waiting for output stored in the input buffer memory 302 is sent to the transmission path 301, Input packets input from the transmission line 300 are stored in the input buffer memory 302.

The above control is also applied to input packets from subsequent transmission paths, and in extreme cases, if audio packets (with high priority) continue in succession, the data packets stored in the input buffer memory 302 will be Although voice packets remain stored in the input buffer memory 302, they are not saved in the input buffer memory in the terminal because they have the highest priority. In this way, voice packets are not saved in the input buffer memory within the terminal, so when the activity of voice packets increases, the delay of data packets increases, resulting in unfairness between different types of packets. In order to eliminate this problem and accommodate voice packets and data packets with good consistency, a passing traffic amount detection circuit 306 is provided. The passing traffic amount detection circuit 306 detects the number of voice packets and data packets that pass during the voice packet transmission repetition period, and notifies the information source via the signal line 353 whether or not the voice packets can be transmitted.

3 with reference to the two examples in Figures 4 and 5.
The control means for the switch 305 in the circuit shown in the figure will be explained.

In FIG. 4, each rectangular box represents one packet, and the alphanumeric characters within the rectangular box represent the packet name. The English letter V indicates a voice packet, and D
indicates a data packet. Here, it is assumed that voice packets have a higher priority than data packets, and all data packets have the same priority. Now, if _a request to send a _D3 packet occurs at the point indicated _{by the} arrow in FIG. The switch 305 is selected so that the _D3 packet is output to the transmission line 301 instead. FIG. 4b is a diagram showing the state of the output transmission path at the time when _one packet time has elapsed from FIG. The packet to be sent is a voice packet _V2 , and a voice packet _V2 is a voice packet V2.
has higher priority, so input buffer memory 3
The switch 30 is set so that the voice packet _V2 is sent out to the output transmission line 301 while being stored in the voice packet V2.
5 is controlled. Next, in FIG. 4c after one packet time has elapsed, the input buffer memory 302
The packet _D1 stored in
The packet input from 0 becomes the audio packet again.
Since the voice packet V ₁ is stored in the input buffer memory 302, the switch 305 is controlled so that the voice packet V ₁ is sent to the output transmission path 301. In FIG. 4D, where one packet time has elapsed from FIG.
Switch 305 is controlled so that D ₁ is sent to output transmission path 301 . In Figure 4e,
Packet D ₁ is output to transmission line 301 and transmitted to transmission line 3.
The packet input from 00 is an empty packet, and the transmission request packet is also stored in the input buffer memory 3.
Since there are no packets stored in 02 waiting for output, the switch 305 is controlled to directly connect the input transmission path and the output transmission path.

The control procedure of the circuit shown in FIG. 3 will be explained using the example shown in FIG. Now _, if a request to transmit packet D ₃ occurs at the point indicated _{by the} arrow in FIG. The switch 305 is controlled so that the _D3 packet is output to the transmission path instead. In FIG. 5b, since the packet input from the transmission line 300 is an empty packet, the switch 305 is controlled so that the packet _D1 stored in the input buffer memory 302 is sent to the output transmission line 301. . In FIG. 5c, since the packet input from the transmission path 300 is a voice packet _V1 , the switch is controlled to directly connect the input transmission path 300 and the output transmission path 301, and the data packet is
_D1 and voice packet _V1 are continuous packets as shown in the figure. As is clear from the examples in FIGS. 4 and 5, data packets may be preempted by voice packets, increasing the delay, but voice packets are not delayed at the terminal. In other words, 1
After that, the voice packets sent to the transmission path arrive at the other party's terminal without any delay due to buffer memory.

Next, transmission control based on the amount of traffic of voice packets passing through the transmitting and receiving terminals will be explained. Now, assume that the transmission path speed is C packets/second. If the transmission repetition period of voice packets is T seconds, the transmission path has the ability to transmit CT packets for T seconds. Let N _D be the number of data packets passing through the sending and receiving terminals in T seconds,
Let N _V be the number of voice packets. In this case, as an example, it is assumed that audio transmission is possible when the following conditions are met.

When N _D , N _V < CT.

When N _D + N _V = CT, when N _D < 1/2 CT, the above condition example is just an example, and the number of voice terminals, the number of data terminals, the call loss rate required of the voice terminals, and the maximum amount of data delay. Conditions will change depending on etc. Changes in conditions due to these external factors are included in this method.

An embodiment for implementing the method of the present invention will be described below with reference to the drawings.

FIG. 10 is a diagram showing the basic configuration of the system.
In the figure, signals flow in the direction indicated by the arrow on transmission line 1000. The control terminal 1001 periodically transmits a signal indicating the starting position of a packet when transmitting a packet between each transmitting/receiving terminal 1002(1) to 1002N, and also controls the loop so that the loop-round transmission path delay is an integral multiple of the packet length. Establish synchronization. Various devices are connected to each transmitting/receiving terminal.

FIG. 6 shows an example of a packet structure used in the system of FIG. 10. In the figure, M indicates a marker bit, and when it is "1", the packet is used.
“0” indicates an empty packet. P indicates priority information, and a numerical value corresponding to the priority type of the information source accommodated in the system is assigned. V is a bit indicating whether it is a voice packet or a data packet; "1" indicates a voice packet, and "0" indicates a data packet. In this example, a bit indicating whether a packet is a voice packet or a data packet is provided separately from the priority information, but it is also possible to determine whether it is a voice packet or a data packet from the priority information. AD1 is the sending address information
AD2 is receiving address information. The field indicated by D indicates an information field.

FIG. 7 shows an embodiment of a transmitting/receiving terminal used in the system of FIG. 10. In FIG. 7, an input packet from an input transmission line 701 is applied to a shift register 703. The shift register 703 has a serial input terminal and two types of output terminals, serial and parallel, and has a length equal to the head length of one packet. The header information of the shift register 703 is output from the parallel output terminal to the signal line 751 as parallel information. The received address of the header information is given to an address matching circuit 705, and the marker bit and priority information are input to a priority selection circuit 704. When the input packet passes through shift register 703, it will be subject to a delay corresponding to the header length. The address matching circuit 705 is easily constituted by an exclusive OR gate, and compares the received address of the input packet with the address of the terminal, and outputs a match/mismatch signal to the signal line 755. If the receiving address and the terminal address match, the input packet is a packet to be received by the terminal, so the marker bit of the input packet must be erased to make it an empty packet. For this reason, the address verification circuit 70
5 outputs a marker erase signal to the signal line 752. A marker erase signal on signal line 752 erases the marker bit in the header information stored in the shift register. Priority selection circuit 70
4 are the marker bits and priority information of the input packet given via the signal line 751, the marker bits and priority information of the output waiting packet accumulated and saved in the input buffer memory 706, and the output buffer memory 708. A signal for selecting the highest priority packet based on the marker bit and priority information of the sending packet and a status signal representing a control signal for the input/output buffer memory are outputted to the signal line 756. A conversion circuit 707 converts the packetized signal into an information signal suitable for various devices connected to the terminal. That is, the conversion circuit 707 receives an input packet from the signal line 705, and if the output signal of the address verification circuit on the signal line 755 is a match signal, it sends an information signal to various devices connected to the data terminal via the signal line 757. Send. 711 is a passing traffic amount detection circuit that counts the number of data packets and voice packets during the voice packet transmission cycle from the header information coming from the signal line 751, detects the amount of traffic passing through the transmitting and receiving terminal, and sends the detection result to the signal line 762. Output and notify the audio terminal. Information signals from various devices connected to this transmitting/receiving terminal are inputted to the packetization circuit 709 via a signal line 758, where they are given header information and converted into packets of a predetermined size. It is output on line 759. The signal on the signal line 759 is stored in the output buffer memory 708 and waits to be sent to the transmission line via the signal line 706. Whether or not the transmission line can be transmitted via the signal line 760 is controlled by the status signal of the signal line 756. Of the header information of the outgoing packet stored in the output buffer memory 708 and waiting to be sent out to the transmission line next, marker bits and priority information are output to the signal line 754. The output buffer memory 706 temporarily stores and saves packets that are not sent to the output transmission path by the switch 710 among the input packets from the signal line 750.
Whether data can be stored or saved in the input buffer memory 706 and whether it can be transmitted from the output buffer memory 706 to the output transmission line 702 is controlled by a status signal on the signal line 756. Output buffer memory 70
Marker bits and priority information among the header information of the delayed packets stored in the packet 6 are output to the signal line 753. The switch 710 selects the packet with the highest priority among the input packet from the signal line 750, the delayed packet from the signal line 761, and the output packet from the signal line 760.
56.

FIG. 8 shows the priority selection circuit 704 shown in FIG.
FIG. In the figure, signal line 850
and 851 are the output buffer memory 708 in FIG.
Marker bits and priority information are shown on signal line 754 outputted from signal line 85.
2 and 853 indicate marker bits and priority information output from the input buffer memory 706, and signal lines 854 and 855 indicate marker bits and priority information of input packets from the transmission line. AND gate circuits 801 and 802 perform a logical product of the input marker bit and each bit of priority information, and output the result to signal lines 856 and 857, respectively. For example, if the marker bit is "1", the output signal of the AND gate circuit is the same as the input priority information, and if the marker bit is "0", the output signal of the AND gate circuit is all zero. The AND gate circuit 803 receives the address match signal from the signal line 755 in addition to the marker bit and priority information, and inputs the address match signal and the marker bit.
It is ANDed with each bit of priority information. For example, the address match signal on the signal line 755 is “1”
(i.e., the received address of the input packet and the terminal address do not match) and the marker bit is "1", the signal on the signal line 858 is the same as the input priority information, and the address match signal is "0" (i.e., the terminal address of the input packet does not match). If the receiving address and terminal address match) or the marker bit is “0”, the signal line 858
All signals become 0. Signal lines 856, 857,
Each signal 858 is input to the highest priority detection circuit 804, and the code indicating the highest priority input is output as a 2-bit signal to the signal line 859 while maintaining the same state for one packet time. The signal on the signal line 859 becomes a control signal for the switch 710 in FIG. 7 and an output control signal for the input/output buffer memories 706 and 707.
The signal indicating the marker bit of the input packet on the signal line 854 and the signal on the signal line 859 are sent to the gate circuit 80.
5 and an input packet exists (signal line 8
If the switch is not selected so that the signal on the signal line 859 sends the input packet to the output transmission line (marker bit 54 is "1"), the signal on the signal line 859 instructs the input packet to be stored in the input buffer memory 706 in FIG. Output. Signal lines 859 and 860
The signal corresponds to the signal on signal line 756 in FIG.

FIG. 9 shows an example of the circuit configuration of the passing traffic amount detection circuit shown at 711 in FIG. signal line 9
The marker bits in the header information input from 50 are ANDed with the audio packet bits in the header information input from signal line 951 by AND gate 901 and output to signal line 954. A signal line 952 is a clock signal having a packet period, and the signal on a signal line 954 is ANDed by an AND gate 903 and outputted to a signal line 956. That is, the signal on signal line 956 becomes 1 when a voice packet arrives.
This means that four clocks are output. Similarly,
The audio packet bits on signal line 951 are inverted by inverter 900 and output to signal line 953. Furthermore, the signal on the signal line 953 and the signal line 950
The signals are ANDed by an AND gate 902 and output to a signal line 957. That is, signal line 9
57 signal becomes 1 when a data packet arrives.
This means that four clocks are output. signal line 9
56 and 957 signals are 905 and 906 respectively
becomes the clock input for the counter 90.
In the counter 906, the counter value increases each time a voice packet arrives, and in the counter 906, the counter value increases each time a data packet arrives, and the counter values are output to signal lines 959 and 960, respectively. Further, a signal from a signal line 958 is input as a reset input for the counters 905 and 906. The signal on the signal line 958 generates a pulse every voice packet transmission period, and the counters 905 and 906 count the number of voice packets and data packets passing through the terminal during the voice packet transmission period. The signals on signal lines 959 and 960 are
The signal is input to the latch 907, the value is held during the audio packet transmission cycle, and is output to the signal line 961. The signal representing the amount of traffic passing through the signal line 961 is 9.
08, and it is determined whether the audio signal can be transmitted based on the detected amount of passing traffic, and the determination result is output to the signal line 762 and notified to the connected audio terminal.

As described above, in the present invention, by giving a high priority to voice packets and a low priority to data packets, voice packets having a high priority can be sent without delay. Also, according to the invention, control is completely decentralized. Furthermore, by controlling the transmission of audio signals based on the amount of traffic passing through the terminal, both the traffic amount and audio packets can be accommodated in the system with good consistency.

Note that although the above explanation has focused on packets with two types of priorities, voice packets and data packets, it goes without saying that the present invention also includes further subdivision of priorities depending on the nature of the information source. It is.

[Brief explanation of the drawing]

Fig. 1 is a frame configuration diagram in which one frame is divided into a time-division subframe and a packet multiplexing subframe, Fig. 2 is a basic block diagram of a transmitting/receiving terminal using the register insertion method, and Fig. 3 is a diagram of a transmitting/receiving terminal according to the present invention. Basic block diagram, Figures 4 a-e and Figure 5 a
~c is a timing chart for explaining the transmission method of the present invention, FIG. 6 is a diagram showing an example of the structure of a packet used in the present invention, and FIG. 7 is a structure showing a transmitting/receiving terminal according to an embodiment of the present invention. 8 is a diagram showing an embodiment of the priority selection circuit used in FIG. 7,
FIG. 9 is a diagram showing an embodiment of the passing traffic amount detection circuit used in FIG. 7, and FIG. 10 is a block diagram showing the system configuration to which the present invention is applied. In the figure, 200...input transmission line, 201...output transmission line, 202...reception register, 203...transmission register, 204...switch, 300...input transmission line, 301...output transmission line, 302...input buffer memory, 303...output Buffer memory for 30
4...Priority determination circuit, 305...Switch, 306
...passing traffic amount detection circuit, 701...input transmission line, 702...output transmission line, 703...shift register, 704...priority selection circuit, 705...address verification circuit, 706...input buffer memory, 707
...Conversion circuit, 708...Output buffer memory, 7
09...Packetization circuit, 710...Switch, 71
1... Passing traffic amount detection circuit, 801, 80
2,803...AND circuit, 805...gate circuit,
804...Top priority detection circuit, 901, 902, 9
03,904...AND gate, 900...Inverter, 905,906...Counter, 907...Latch, 908...Judgment circuit, 1001...Control terminal, 1
000...Transmission line, 1002(1) to 1002(N)...
Sending/receiving terminal.

Claims (1)

[Claims] 1. In a loop transmission system that has a plurality of transmitting/receiving terminals and one control terminal and connects these terminals in a loop to perform packet communication between each transmitting/receiving terminal, the control terminal transmits a signal indicating the leading position of a packet. Loop synchronization is established so that the transmission path delay when transmitting periodically and going around the loop is an integral multiple of the length of the packet, and real-time information is required among the information packets from the transmitting and receiving terminals. A first high priority is given to real-time information packets that do not require real-time performance, and a second low priority is given to information packets that do not require real-time performance. A first storage means for evacuating and a second storage means for storing output packets from an information generating device connected to the transmitting/receiving terminal is provided, and the input packet and the output packet from the first storage means are provided. The priorities of the delayed packet and the sent packet are compared, and the packet with the highest priority is sent to the output transmission path, and the real-time information with the first highest priority is transmitted from the first transmitting/receiving terminal. When transmitting a real-time information message composed of a plurality of packets, prior to transmitting the real-time information message, the real-time information that passes through the first transmitting/receiving terminal during the repetition period of transmitting the real-time information packets is transmitted. Detecting traffic amounts of real-time information packets and data packets from the numbers of information packets and data packets, and starting to transmit the real-time information message when the detected traffic amounts satisfy a predetermined condition. A multi-information complex loop transmission system including traffic control characterized by: