JPS63290038A - Data transmission system - Google Patents

Abstract

PURPOSE:To improve the transmission efficiency of data information by removing a slot protocol control signal except of a first and a last slots, when the data is transmitted as putting plural slots in a row. CONSTITUTION:When the length of the data to be transmitted is longer than the length of a data area in the single slot of the plural slots, a communication node transmits the data to be transmitted by using the plural slots, as using n-pieces (n is 2 or larger integer) of the continuous slots in a single frame, and in addition, as considering the slot except a first and a n-th slot of the continuous slots to be the signal that the slot protocol control signal is removed from the slot. Thus, when the plural continuous slots are used, the number of bytes, which can be assigned to the data information, is increased, and the slot protocol control signal is extremely lightened, and the transmission efficiency of the data is improved.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a data transmission system, more specifically, a system for transmitting and receiving data between a plurality of terminals via a common communication line, especially a slot access section. It's about configuration.

[Conventional technology]

In the data transmission system as described above, a slot access method is known as one method for preventing data from multiple terminals from colliding on the line.

The slot access method is a method in which data is transmitted using a type of time division multiplex transmission method in which the time domain of data transmission is composed of frames with a constant period. One frame consists of a frame protocol control area such as a frame header representing the beginning of the frame, and a plurality of slot areas. When using the slot to transmit data packets, etc., the configuration of the slot is as follows: It consists of a slot protocol control area such as a slot header indicating the beginning of the slot, and a data transmission area.

The slot access method is based on IEEE 80, an international standardization committee for local area networks (LAN).
2 Committee Proposal Traft of Proposed, I.E.E. Standard 802-6
(10, 1985) “Draft of Propos
ed IEEE 5 standard 802, 6''.

[Problem that the invention seeks to solve]

When transmitting data using the conventionally known slot access method described above, the slot configuration -2'3 is determined, and as shown in Figure 1, 64 bytes of upper transmission information and 4 bytes of upper transmission information. Data header consisting of packet division/assembly information ■, slot header (S) before and after it
One slot consists of a total of 77 bytes, including 9 bytes of slot protocol control area such as 1 byte of H).

Therefore, when transmitting data such as packet data currently handled in packet switching networks, which has an average size of about 100 bytes (up to about 4000 bytes) or more, using the slot access method, the transmission efficiency decreases for the reasons described above.

For example, a 140-byte service data unit (SD
When transferring U), three slots are occupied in the conventional slot configuration. On the other hand, if there is no limit on the packet length,
140 bytes of data, 9 bytes of slot protocol control, and 4 bytes of information for packet division/assembly, totaling 153 bytes.
Byte, which is less than two slots long.

In other words, in the conventional slot access method, when transmitting data with a data area of 64 bytes or more, it is necessary to divide the data into multiple packets, and the slot protocol control information increases according to the number of divisions, resulting in overhead. Therefore, there was a problem that the transmission efficiency decreased.

[Means for solving problems]

In order to solve the above-mentioned problem, the present invention has the above-mentioned slot configuration, in addition to the conventionally known slot configuration, ``concatenation'' indicating that a subsequent slot is concatenated to form one packet; A “last” slot header indicating that this is the last slot in a series of slots forming one packet is added to the frame header ( This is solved by arranging it in the area following FH).

[Effect]

With the adoption of a new slot head and new allocation within slots, when transmitting data by connecting multiple slots, the above-mentioned slot protocol control signals (frame check code, response area) are transmitted in the first connected slot. bits), segmentation/assembly information, and data information; subsequent "successive" slots contain slot headers (
The "last" slot includes a slot header, data information, check code, and end-of-slot signal.

With these slot configurations, when multiple slots are used consecutively, the number of bytes allocated to data information increases, and slot protocol control signal 9 division/assembly information, etc. is significantly reduced, improving data information transmission efficiency. I will do it.

Furthermore, in the frame configuration, the above-mentioned used/unused indication (Av) bit is received before the slot, so it is used to determine the usage status of the subsequent slot header for the purpose of "detecting the final slot transmission timing". This eliminates the need for intra-node delays.

〔Example〕

Before describing the present invention in detail, the configuration of a loop transmission system in which the present invention is implemented will be described to facilitate understanding of the invention.

As shown in FIG. 2, the loop transmission system includes a plurality of communication control bags e1 (hereinafter also referred to as nodes) 202°203.2.
04 and 205 are connected in a loop by a transmission line 201.

The host computers 242 and 243 have communication processing bags [2
22, 223, and communication nodes 202 and 203,
They communicate with each other using a packet switching method.

232 and 233 are video conferencing devices, specifically, consisting of a television camera and a monitor device. The data transferred between the video conference devices is moving image information, and instant communication is required, so a line-switched communication format is adopted.

The communication terminals 224, 225, 234, and 235 are connected via respective bus-type subnetworks 214 and 215, and communicate with each other through the communication nodes 204 and 205 using a packet exchange method.

The management node 200 performs channel allocation, transmission path failure monitoring, and loop synchronization monitoring and control in the circuit switching system described above.

FIG. 1 shows a frame format used in an embodiment of a transmission system according to the present invention. In this embodiment, an independent synchronization method is adopted in which each communication node operates with its own clock, and the clock frequency deviation is recorded in a 1-byte invalid field (T
Absorb with F). Frame header (FH) is C0NN
ECT10N, BID, INDEX.

Represents four types of FOLLOIJING frames.

These signal types are the same as those described in the draft of 802.6, so a detailed explanation will be omitted.9 The frame header FH during normal data transfer is INDEX or FOLLOW.
ING, and the management node sends multiple frames within the intra-loop transmission delay time, the first frame header F
H is INDEX, FH after 2nd is FOLLOυIN
It becomes G.

In the slot areas 81-S8, information is transferred in various slot formats 122-127. Synchronous thrower I-1
22 is a slot for transmitting synchronous information such as video conference images, and provides line switching (allocation for each channel).

This slot 122 consists of a slot header SH and 76 1-byte channels (CHI to CH2C).

The channels CH1 to CH76 are allocated by the management node in response to a request from each communication node. The above slot 122
The use of is the same as conventionally known.

Single slot 123. First connection slot 124°Subsequent connection slot 125. The final connection slot 126° is a packet transfer slot and has a packet exchange function.

The signal configuration of the single slot 123 is the same as that conventionally known, and includes a slot header S, a slot controller S, and a slot controller S.
C9 destination address field DA.

It consists of a slot protocol control field of 5 pci consisting of a source address field SA, a frame check field FC8, and a response field R3, and an information field of 68 bytes or less. Information field 1 includes 4 bytes of division/assembly information (order of division of data, etc.). The number enclosed in parentheses (,) in FIG. 1 indicates the number of bytes.

The slots 124, 125, and 12'6 described below have a configuration unique to the present invention.

The first connection slot 124, one or more subsequent connection slots 125 and the final connection slot 126 are used sequentially in the above order. The configuration field types of the above three slots are the same as in the case of the single slot 123.

Empty slot 127 is an unused slot.

The header SH of each slot is an identifiable button of the slot type.

Furthermore, there is a slot information area (SIX) in the frame.
The slot information area (SI2) consists of a bit string indicating the usage status and attributes of the subsequent slot, and is a signal unique to the present invention. Area SII is a used/unused display bit Av (1 byte).

Management station recognition bit Od (1 byte), slot reservation bit Re (1 byte), synchronous/asynchronous indication bit sy
The area SI2 consists of a concatenated slot display bit MO (1 byte), a concatenated slot final display bit Ls (1 byte), and reserved bits (2 bytes).

To explain in more detail, used/unused bits (AV) are:
Indicates the usage status of multiple slots in the frame, and when indicating unused slots, the slot header S of the corresponding slot
H is set in the SH of slot 127 and indicates use when other headers SH are used.

The management station recognition bit Od is set by the management node.

For the purpose of failure or error monitoring, this bit applies and is set only to the used slots that pass through. When the 0 bit is set, the header SH of slots other than the empty slot 127 is also changed to a single recognized SH. Bit Od and recognition S H
is changed to reset 1- or a predetermined SH by the sending note, so the management node never receives the recognized slot.

The slot reservation bit Re is a bit set by the management node, and indicates that this slot will be allocated as a synchronous slot from the next round.

The synchronous/asynchronous indicator bit Sy is a bit that distinguishes the synchronous slot 122 from the other slots 123 to 127, and is set by the management node.

The connected slot display bit Mo indicates that the corresponding slot is
First connection slot 124 or subsequent connection slot 125
The concatenated slot final indication bit Ls is set by the communication node when the corresponding slot is the final concatenated slot 126.

If the data (SDU) communicated by the communication node is less than 64 bytes, for example, a single slot 123 is used, and if the SDU is more than 64 bytes, it is determined by the display bit AV and reservation Re. Depending on the number of usable slots to be connected, the first connected slot 124°, the subsequent consecutive slots 125. The final concatenated slot 126 combination transmits the data packet. However, the maximum packet length was set to 77 bytes x 8 = 616 bytes, which is limited by the frame length.

FIG. 3 shows the transmission and reception processing of the management node 200.

When receiving a slot where the display bit AV is (0), the slot header SH is set to indicate that the slot is empty.
The 0 display bit AV sent as ty J is 111
When the recognition bit Od is "O" in I+, that is, when an unconfirmed used slot is received, Od is set to "1" and SH is set to "Old" and sent. On the other hand, bit Od is I1”
At the time of slot reception, regardless of the reception indication bit Av, AV and Od as well as "0" header SH and "E m p
ty" and sends it out. In this case, it indicates that an error has occurred in the communication node, and is collected as failure occurrence information.

FIG. 4, FIG. 5, and FIG. 6 show the transmission and reception processing of the communication node.

FIG. 7 is a diagram showing the main part of an embodiment of a communication node, and in FIG. 11, medium-sized lines indicate data flow, single lines indicate control signal lines, and timing signal supply lines are omitted for the sake of clarity.

In FIG. 7, 7-1 and 7-2 represent a terminal receiving section and a terminal transmitting section in a communication terminal, and a terminal interface 7
-3 through the asynchronous data receiving memory 7-4 and the synchronous data receiving memory 7-5. asynchronous data transmission memory 7-6;
It is coupled to a synchronous data transmission memory 7-8. Each of the above memories has a control circuit 7-9.7-10.7-11
Writing and reading are controlled by and 7-12.

Received data received from the transmission line 201, that is, a signal having a frame structure, is converted into a parallel signal (e.g., 8 bits) by a serial/parallel converter 7-20.

Frame synchronization circuit 7-21. Flot counter 7-22
．． The byte counter 7-23 uses the time fill TF of the frame signal to identify frames and generate necessary timing signals.

The determination circuits 7-24 and 7-25 determine the frame headers FBI, SI 1. A determination of SI2 and a determination of slot head SH are made.

The reception determination circuit 7-26 receives the determined signals FH and S.
II, SI2 and SH generate and control control signals as will be described in detail later.

The switching circuit 7-27 switches the data destination according to the synchronous/asynchronous indicator bit sy in the SII. The address determination circuit 7-28 determines whether the survey data is addressed to the own node using the destination address DA in the slot. Also, F
The C8 determination circuit 7-29 examines the FSC of the slot and performs error detection and the like.

The reception control circuit 7-30 activates the memory read/write control circuits 7-9, 7-10 based on the address DA and the control signal from the reception determination circuit 7-26.

Transmission control unit 7-31. Signal R indicating the presence or absence of a transmission request from own terminal
q, determines the transmission data type using the signal Tr (stored in the register as a table) representing the slot usage status of the frame, the signal from the reception determining section 7-26, and the slot header generation circuit 7-32. Generates a generation instruction signal for frame protocol control signal Slj generation 7-33.

The data switching circuit 7-34 performs switching between synchronous and non-synchronized data, that is, selection of transmission data and generation of address information, in accordance with the type of transmission data.

The transmission data selected by the switching circuit 7-34 is converted into a slot signal by a slot assembly circuit 7-36.

In the case of an asynchronous signal, a signal from the FCS bit generation circuit 3-35 is also added.

The frame assembly circuit 7-39 creates a transmission frame signal using the timing signal from the transmission counter 7-37, the slot signal from the slot assembly circuit 36, and the signal from the frame protocol control signal SIi generation circuit, -40 to the transmission line 201.

Note that the buffer memory 7-41 is a buffer that only the management node has, and is an error stick buffer for guaranteeing frame cycles.

Hereinafter, specific cases will be explained separately. As shown in FIG. 4, in the case of #4-1, that is, Ay of the received frame is O2, transmission request bit Rq is 0 (when the flot is not used and there is no transmission data), Av, M of the output frame
o, Ls, and SH are not changed. However, when the spontaneous transmission slot indication bit (that is, the bit indicating that the slot was used by the own node one frame ago) is "1" and the Od of the received frame is "1", this is 110 +
#, and leave it as is when Tr is 110 Pj.

In the case of #4-2, that is, when Av is 'O' (slot is unused) and R(1 is '1' (there is data to be transmitted to the own node), the Od of the output frame is 'Q'
A v , M o , L s , and S H become as shown in FIG. 5 depending on Re and Sy of the received frame. T3 in FIG. 4 indicates this. To put it more precisely, #5-1, that is, Re is "1".

If sy is "0" (when the slot is not reserved and is an asynchronous slot), Av is "1".

Mo, Ls are slot types (123 to 126 in Figure 1)
), SH is F” u 11 (used). #5-2 and #5-3, that is, Re is “O”
+ When S y is "1" or Re is "1", Av, Mo, Ls, and SH of the output frame are unchanged.

34-3 (Av="1", Tr="O"), that is,
If the slot is in use and not used by the own node, in this case, Av, ○d, Mo,
Although there is no need to consider Ls and SF, there is a possibility that the frame is addressed to the own node. Therefore, in this case, the input conditions shown in FIG. 6 are satisfied, and the frame matches the corresponding reception slot type. In the case of #6-1 to #6-3, if the destination address DA of the slot indicates the own node, the receiving operation is performed.In addition, for reception, the information in the slot is copied to the own internal memory, and the response field is This is achieved by setting the field to a predetermined value.The slot white information other than the response field is not changed by the receiving communication node.#6-
Case 4 is a case of synchronous communication.

#4-4, that is, when Av is “1” and Tr is “1” (when the slot is in use and is used by the own node)
, send it out with an empty slot. In other words, Av is “0”,
Let Od be “O” and SH be Empty.

Note that in this embodiment, the SH was changed to correspond to the area Si, but this was done because emphasis was placed on compatibility with the 802.6 proposal, and there is no problem even if the SH is the same button.

〔Effect of the invention〕

In order to show the improvement in transmission efficiency according to this embodiment, FIG. 8 shows the transmission efficiency with respect to the transmission data unit length using the slot length and slot type as parameters.

The dotted line 812 is the maximum value of efficiency when the packet length is 25 bytes (of which the effective DT is 16 bytes), the dotted line 813 is the minimum value, and the efficiency varies within the area surrounded by both dotted lines. solid line 80
1,802,803 is a packet length of 73 bytes (effective D
T 64 bytes), and can take the efficiency on 801 or in the area surrounded by 802 and 803. The cases of dotted lines 821, 822, and 823 are also similar to the above two examples. All three examples above are cases where only a single slot is used, whereas solid line 804 is a case where three types of connected slots are used, and the maximum efficiency is improved over 802.

Furthermore, according to this embodiment, intra-frame SII.

The byte length of each area and slot area of SI2 is a multiple of 4, which enables parallel processing of 2 bytes, 4 bytes, or more, and is effective in speeding up communication nodes.

[Brief explanation of drawings]

1 shows a frame format used in an embodiment of a transmission system according to the present invention, FIG. 2 shows a configuration diagram of a loop transmission system, FIG. 3 shows a management node transmission/reception process, and FIG.
5.6 is a transmission/reception processing diagram of one communication node, FIG. 7 is a block diagram of an embodiment of the communication node of the system according to the present invention, and FIG. 8 is a diagram of transmission efficiency with respect to transmission message length. SII...Slot information area 1, SI2...Slot information area 2.122...Synchronization slot, 123...
- Single slot, 124...first consecutive slot, 12
5... Subsequent connection slot, 126... Last slot, 201... Transmission line, 202, 203, 204, 20
5... Communication node, 214, 215... Sub network, 224, 225, 234, 235... Communication terminal, 242.243... Communication processing device.

Claims (1)

[Claims] 1. Consisting of a loop transmission path and a plurality of terminals coupled to the loop transmission path via a communication node, the signal configuration transmitted via the communication node is divided into a fixed interval by a slot header. The communication node consists of a frame signal with a constant cycle including a plurality of slots divided into slots and a frame header indicating the frame type, and each of the communication nodes determines the usage status of the slot included in the slot header and determines whether the slot is available or not. In a data transmission system in which data to be transmitted is transmitted using slots of , using n consecutive slots (n is an integer of 2 or more) in a single frame, and using the first and nth slots of the consecutive slots.
A data transmission system using a slot access method, in which the data to be transmitted is transmitted using a plurality of slots as signals excluding slot protocol control signals in slots other than the slot number. 2. The data transmission system according to item 1, wherein the slot headers of the first to (n-1) slots and the slot header of the n-th slot have different bit configurations. 3. In the data transmission system described in item 1, a bit string indicating the usage status of each slot in one frame is
Arranged after the frame header of the frame, the communication node having the data to be transmitted is configured to determine the slot to which the data to be transmitted is allocated based on the bit string indicating the usage status when receiving the frame. A data transmission system characterized by: