JPS62261250A - Mechanism for facilitating exchange of data and non-encoded information in communication network - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Industrial Application Field The present invention connects both pure data terminals and intelligent workstations capable of exchanging data and non-coded information NCI such as audio or images. can. Relating to switching mechanisms used in communication networks including multiple nodes.

B. Prior Art Intelligent workstations are capable of receiving and transmitting data and unencoded information, such as packetized and compressed audio or images.

US Pat. No. 4,535,448 describes a system with terminals capable of transmitting and receiving both voice data and packetized pure data. This system provides various types of interfaces that allow terminals to access either a packet bus, dedicated to the exchange of packetized data, or a time-division multiplexed bus, dedicated to the exchange of voice data. It is being

Problems to be Solved by the C0 Invention The systems described in the above patents do not take advantage of the functions of current communication networks, since they require dedicated means for pure data and voice and data processing.6 Objects of the Invention The object of the present invention is to provide an improved switching mechanism that can be incorporated into a line scanner of a future communication control unit or an external adapter that can be added to a line adapter of an existing communication control unit, the mechanism comprising:
Data resources of a communications controller are made available for routing uncoded information within a communications network.

Means for Solving the D0 Problem The mechanism according to the invention allows data and packetized uncoded information NN CI to be exchanged between workstations connected to nodes of one communications network. Said node includes data processing means for establishing a session between any source workstation and any destination workstation and for routing data exchanged between said workstations.

Each workstation is equipped with transmitting means (FIG. 8) and receiving means (FIG. 9). The transmitting means separates the data bits and NCI bits to be sent by using a delimiter flag (F
1, F2), with each slot containing bits representing data only, bits representing MCI only, or MCI bits and data bits. The data-only slot starts with the first delimiter flag (F2). N.C.I.
Dedicated slots and dual-purpose data/MCI slots begin with a second delimiter flag (Fl) followed by at least one NCI packet containing the addresses of the originating and destination workstations participating in the session, and have a data portion. If so, the data follows the NCI packet starting with the first flag (F2). In addition, the receiving means responds to the detection of the one-interval flag,
Search for data bits and MCI bits in the received bit stream.

Network nodes include:

Fast path (26) on which NCI packets are exchanged.

the address of the node outbound link selected by the data processing means as a result of a session initialization phase consisting of sending routing data comprising the addresses of the originating and destination workstations and the addresses of said workstations; marking means (46, 42) for recording.

NC sent once when session initial settings are completed
selection means (40) responsive to the address of the workstation contained in I, taking from the marking means the address of the selected outbound link for the session and generating a selection signal therefrom;

Each node inbound link includes:

N CI receiving means (38).

It receives the bit stream sent from the origin workstation and responds to its flag configuration to
bits to the data processing means and the NCI packet to N
Separating means (34) for sending to CI receiving means.

Scheduling means (39) for sending MCI packets from the NCI receiving means to the high speed bus.

Each network outbound link includes:

NCI sending means (48).

gate means (50 ).

Formatting means (52) for receiving data bits from the data processing means (1o) and NCI packets from the output storage means (48) and arranging them in a workstation bit stream format.

E. EXAMPLE FIG. 1 schematically depicts a communication network in which the arrangement according to the invention can be incorporated. Although this network consists of several nodes, only nodes 1.2 and 3 are shown in the figure. Components within each node are indicated by a number followed by a suffix indicating the node in which they are incorporated.

Each node has one communication control unit 10 and a higher-level central processing unit CP.
It is equipped with tJ42. Communication control bag @10 is IBM37
25 communication control device may be used. This communication controller is connected to a data path 14, which is a bidirectional link dedicated to the transfer of data traffic. According to the invention, external adapter 16 connects the data path to user and intermediate node links 20. The user may consist of an intelligent workstation IW318. For example, intermediate node link 20-1-2 connects node 1 to node 2. These intermediate node links are fast time division multiplexed links and are used to transfer user information from one origin node to one destination node. The operation of external adapter 16 is controlled by service processor 22.

A particular embodiment of the invention will be described assuming that the network is of the system network architecture SNA type. The format of messages that can be exchanged on this type of network is described in the "IBM System Network Architecture Overview Manual" (IBM System Network Architecture Overview Manual).
M Systems Network Architecture
Reference Summary)
GA 27-3136-4.

In accordance with the present invention, data and NCI information from or to workstation 18 are transmitted over workstation link 24 on the same channel.
, thus ensuring good channel utilization. M CI information packets are transported transparently between communicating nodes on intermediate node links using the same path as the data. Therefore,
Data and N C related to the same workstation
I information is said to be a companion. The route is established by normal network resources. Typical network resources include, in the particular environment described herein, a communication controller IBM 3725, a network control program NCP, and an IBM 370 central processing unit (CPU).

This use of companion transport will be dynamic.

That is, the data session is opened first. This data session is established as if the workstation were a regular data terminal, using conventional data communications networks and resources to perform routing and network management. An NCI transfer is then performed with or without data. To close a session, a data-only transfer is performed.

At each node, the NCI information is M
It is transported by the CI path 26. The implementation of these buses will be explained in more detail later.

This prevents the MCI information from being affected by various delays introduced by the data path.

Assume that source workstation 18-1 is connected to destination workstation 18-3. Each external adapter 16 at border nodes 1 and 3 and intermediate node 2
can send MCI packets from a particular inbound link to that outbound link. For example, at node 1, the inbound link is workstation link 18-1 and the outbound link is intermediate node link 20-1-2.

The frame format is shown in FIG.

An MCI packet related to a workstation is
For example, 8 kilobits per second voice packets and the intermediate link 2o is, for example, a 64 kilobits per second link. Several voice packets from different workstations are multiplexed on the same intermediate link.

The sending workstation mixes the bundle of NC packets or MCI packets with the data at regular time intervals, e.g., 20 milliseconds, to minimize delay distortion for a particular source workstation and destination workstation pair. do. NCI packet has start flag F1
followed by the source workstation address WSA○ and the destination workstation address WSAD, followed by the contents of the MCI.

Data packets are delimited by a start flag F2 followed by a user data stream. On the workstation link.

In the preferred embodiment of the invention, where there is only one NCI packet associated with the origin and destination workstations sent every 20 milliseconds, Fl is chosen equal to the hexadecimal flag of 7E (01111110 in binary representation). , F2 is the hexadecimal flag 7F (0111
1111). To avoid false recognition of the Fl and F2 flags, NCI packets and data packets are sent and received by the workstation using conventional zero insertion/deletion techniques.

During the first phase, the origin workstation, e.g.
18-1 transmits only data organized in frames delimited by flag F2 as shown in FIG. 2C, containing routing information in the data field. External adapter 16-1 recognizes the F2 flag, deletes it, and performs zero deletion so that the workstation appears as if it were a terminal connected directly to communications controller 10 without external adapter 16. to play the actual data bit stream sent by the workstation.

During this first phase, the workstation acts exactly as a data-only terminal, transmitting the data to a destination terminal that processes the data only within the network.

Once this normal network routing procedure is complete, destination workstation 18-3 can communicate with the origin workstation. The origin and destination workstations can now exchange messages containing only data.

Next, enter phase 2.

The origin workstation sends certain data information to the destination workstation as shown in Figure 2-B. This specific data information undergoes the following processing.

Normal data request/response unit RU depending on node resources
and then sent to the destination workstation.

It is called marking frame bit MF.

Due to the specific coding of the reserved bits belonging to the TH field when transmitting a data frame, the frame is recognized by the external adapter as NCI marking information. This particular bit has no effect on normal SNA resources. The general format of the transmission header TH in the SNA architecture appears in the document GA27-3136 referenced above. They consist of six transmission headers, with a format identifier of type FT
Change according to D. FID type 4 is the most commonly used identifier type. This is used for traffic between adjacent subarea nodes when both nodes support both explicit and virtual routes. FI
A D4 type transmission header consists of 25 bytes. The first 4 bits of byte 0 are encoded as 010o and F
Identifies the ID4 format, byte 1 has 8 reserved bits, byte 16 has 1 reserved bit, and byte 1
7 has 8 reserved bits.

On all links 14 coming from a communications controller 1o, the external adapter 16 must identify NC emerging frames among all data frames received from one communications controller. To do so, an external adapter 16
The FID consists of the first four bits of byte 0, since the originating workstation uses this format for the exchange of NCI marking frames and other pure data.
4 identification bit 0100 and also recognizes the marking frame bit MF.

If this marking frame bit MF is on,
The origin workstation that is part of the user data
address WSA○ and destination workstation address WSAD are associated outbound links 20
-1-2 is stored in the external adapter.

Next, enter phase 3.

At this time, the external adapter 16 includes NCI marking information, and when decoding the pair of WSAO and WSAD,
By performing circuit switching within the adapter, MCI
Packets can be sent from the originating workstation to the outbound link of interest.

During this phase, the format for the workstation link is as shown in Figure 2-A.

To ensure full-duplex communication, the destination workstation responds with a data response unit RU to the operations performed in phases 2 and 3 to direct the route from the origin workstation to the destination workstation.
Run to direct the route from the destination workstation to the origin workstation.

To close a session, enter the data-only phase and clear the NCI marking information.

Next, while referring to Figure 3, connect the external adapter block and
Explain the diagram. For easy understanding,
Although only the means associated with communication from the originating workstation to the outbound links are shown, to implement full-duplex communication each link must be equipped with suitable receiving or transmitting means, as described below. It won't happen.

In FIG. 3, only the transmission interface 30-T of the workstation link of FIG. 1 is shown.

Two such interfaces, namely the interface 3O-Tl associated with the two workstations.
and 3O-T2 are represented here. The address of the first workstation is WSAOI, and the address of the second workstation is WSA○2. These workstations each have a WSADI address.
and a destination workstation that is WSAD2. These connections are.

Established by receiving interfaces 32-R1 and 32-R2 of outbound intermediate link 20 using the procedure described above. These outbound links are
It is selected using normal network procedures during the data-only phase transfer (Phase 1) and has outbound link addresses 0LAI and 0LA2.

In this diagram, a component interface is identified by a generic reference number and whether this component has an address WSA○1 or WS
It has a suffix 1 or 2 to indicate that it is included in the connection initiated by the originating workstation with A○2.

Interface 30-T is connected to input circuit 34. Input circuit 34 separates the data and MCI information received from the workstation and removes the F2 delimiter flag inserted into the information flow by the workstation as shown in FIGS. 2-A through 2-C; Remove inserted zeros from data packets and NCI packets.

Data bits at link clock speed.

It is sent to the communication control device via the data input line 36. Separator flag F1. Contains the addresses WSA○ and WSAD of the origin and destination workstations,
The MCI packet is stored in a large first-in, first-out (FIFO) memory 38. Information read from memory 38 on bus 54 is sent to outbound link selector 40.
supplied to

Fl read from memory 38, WSA〇-WSAD
Fields and MCI packets are provided to the MCI hash 26 under control of the bus scheduler 39 and sent to the relevant outbound receive interface 32-R. Selecting the outbound receiving interface is
This is done by outbound link selector 40.

During the second phase of the session, marking output table 42 is loaded with the address pair WSAO-WSAD and its corresponding outbound link address OLA. Table 42 is a content addressable memory addressed by WSA○-WSAD pairs.

The output data a44 is sent to the marking frame detector 46
It is connected to the. Marking frame detector 46 searches in the data stream for an address field containing the address pair WSA○-WSAD from communications controller 10. Thus, during the twenty-seventh aid of the above process, the detector 44 associated with each data output line 44 loads the table into memory 42. The NCI packets on bus 26 are provided to a first-in, first-out (FIFO) memory 48 via an AND gate 50.

Output circuit 52 receives the data stream from data line 44 and the information read from memory 48 under control of a 20 millisecond clock. The circuit 52 provides a second-A signal on the receiving interface of the outbound intermediate link.
A data/NCI packet stream as shown in Figures 2-C is provided. To accomplish this, circuit 52 adds the appropriate flag and performs a zero insertion function.

Input FIF○Address pair W read from memory 38
SA○-WSAD is provided to outbound link selector 40 via bus 54. Selector 40 addresses the marking output table via bus 56. The corresponding outbound link address LA read from table 42 is
is supplied to the selector 40 via line 60, and is used to supply an adjustment signal to the corresponding A N D gate 50 via line 60.

As shown in FIG. 3, input FIFO memory 38 is used by only one workstation and therefore
During each 20 millisecond period, the output FIFO memory 48 contains only one NCI packet, but because the intermediate links are multiple links as described above, the output FIFO memory 48 contains NCI packets associated with multiple origin/destination workstation pairs. be able to.

To ensure full-duplex communication, each workstation link 24 in FIG.
34.36.38 and 46, 50.48.52. Each outbound link 2o in FIG. 3 includes receiving interface means 46, 50.48.52 and 30.34.36.
It is equipped with transmission interface means similar to 38.

Next, the marking frame detector 46 will be explained with reference to FIG. Marking frame detector 46 operates under the control of a data link bit clock signal provided on line 70 by output circuit 52 (as described below in connection with FIG. 6). The data bits on output data line 44 are input to one counter 72 at the data bit clock rate. The contents of counter 72 are compared with the value "6" by comparison mechanism 74.

The data bits received on line 44 are sent to inverter 7.
Inverted by 6. The output of inverter 76 and the output of comparator 74 are supplied to AND gate 78 . Thus, when six ones followed by one zero are detected in the data stream, AND gate 78 provides an active output signal. The active output signal on line 8o from AND gate 78 sets flag detect latch 82;
Used as a general reset signal.

An output line 84 of latch 82 and data bit clock line 70 are connected to an input of AND gate 86. The output of AND gate 86 is provided to counter 88 .

Therefore, when latch 82 is set to indicate that the 5DLCf flag is detected in the input data stream, color counter 88 begins counting data bit periods. A comparison mechanism 90 compares the contents of the counter with the parameter NTH.

This parameter NTH indicates the beginning of the transmission header TH with reference to the end of the flag f (see Figure 2-C). The value of the parameter NTH is determined by the external service processor 22
is loaded into register 92 by.

The data bits on line 44 are input to a 16-bit shift register 94. The contents of register 94 are compared with the FIFD4 type bit configuration by comparison mechanism 96. Output line 98 of comparison mechanism 96 and output line 100 of comparison mechanism 90 are connected to AND gate 102 . AN
When the output signal on output line 104 of D-gate 102 is active, ie, when a FID4 configuration is detected in the transmitted header, FID4 detection latch 106 is set. The signal on output line 108 of latch 106 is connected to the reset input of f flag detection latch 82 and to A N D gate 1.
10 inputs.

The other input of AND gate 110 is the data bit.
connected to clock line 7o and therefore AND gate 11
0 provides a data bit clock pulse on its output line 112 from the time the FID4 configuration is detected. Output line 112 is connected to counter 114, which begins counting data bit clock periods.

The contents of counter 114 are compared with parameter NMF. This parameter NMF indicates the position of the marking bit MF relative to the end of the FID4 configuration. This parameter is loaded into register 116 by service processor 22 and provided to comparator 118 along with the contents of counter 114.

The contents of register 94 are compared with a mask mechanism by comparator 120 to enable detection of the MF bit.

Output line 112 of comparator 118 and output line 124 of comparator 120 are connected to an AND gate 126, which provides an active signal on its output line 128 when the MF bit is detected. . This signal sets the MF detection latch 130. The output line 132 of latch 130 and data clock line 44 are connected to AND gate 134.
Therefore, AND gate 134 is connected to counter 1
The data bit clock signal for M38 is provided on its output m136. From the time the MF bit is detected, counter 138 begins counting data bit clock periods. The contents of counter 138 are compared with parameter NWSA by comparison mechanism 142. This parameter NWSA is loaded into register 140 by service processor 22.

Parameter NWSA indicates the address field relative to the position of the MF bit. Therefore, comparison mechanism 142
When equality is detected by , a load control signal is provided on output line 144 . This pulse causes the contents of register 94 to be loaded into WSAO-WSAD register 146 and its corresponding outbound link address LA to be loaded into register 148.

o LA parameters are contained in registers 150 and are loaded into registers 150 by the service processor.

The latch 82 is connected to the output line 10 of the FID4 detection latch 106.
It is reset by the output signal on 8.

Latch 106 is reset by a general reset signal on output line 8° of AND gate 78 or by a signal on output line 132 of latch 130. To do this, line 8o and line 132 are connected to OR gate 15
The output line of OR gate 152 is connected to the reset input of latch 106. latch 130
is reset by a general reset signal on line 80 or by a signal on output line 144 of comparator 142. To accomplish this, lines 80 and 144 are connected to the inputs of OR gate 154 and
The output line of 4 is connected to the reset input of latch 130.

Next, while referring to FIG. 5, mark output table 4
2 and its peripheral circuits will be explained.

Conflict resolution circuit 180 receives the load signal generated on a144 of marking frame detector 46 of the external adapter.

Conflict resolution circuit 180, on one output line 182 thereof,
A selection signal is generated which, when active, causes an update of the output marking table 42 for a particular interface 32.

AND gate 184 is conditioned by a select signal on line 182 to gate the contents of WSAO-WSAD register 146 provided from bus 156 shown in FIG. An output bus 186 of AND gate 184 is connected to an OR gate 188, which
The WSAO-WSAD information stored in table 42 is provided on its output bus 190.

AND gates 192 are also conditioned by a select signal on line 182 to gate the contents of LA registers 148 provided from bus 160 (FIG. 4) to their output bus 194. Output bus 194 is OR
Connected to gate 196, OR gate 196 transfers the contents of the selected OLA register 148 to marking output table 42 for updating.

The select signal on line 182 is connected to OR gate 2oO, and the output signal of OR gate 202 activates counter address sequencer 204.

The counter address sequencer has its output bus 20
6 provides the address of the location in table 42 where the WSAO-WSAD and its corresponding LA information should be written.

Table 42 is read under the control of circuit 40 (FIG. 3). This circuit 4o receives information from an input FIFO memory 38. Information on bus 54 read from these memories is provided to addressing circuitry 208 .

This addressing circuit 208 is WSAO-WSAD4
: Recognize the preceding F1 flag.

As shown schematically in FIG.
is input register 2 for each inbound link 30.
10, and information read from the FIFO memory 38 is input to the input register 210 from the bus 54. The circuit 212 is.

It is detected whether register 210 contains flag F1. If yes, next field WS AO-WSAD
A latch is set to condition AND gate 216 while .

During this time, the contents of register 210 change to address
The signal is supplied to selector 218.

Address selector 218 selects one of the address pairs WSAO-WSAD provided by the AND gate, which is input to memory address register 220 by bus 222. Accordingly, an input address register provides on bus 56 the address of the memory location to be read.

The corresponding LA address is supplied to the register 224 and decoded by the decoder 226. Decoder 226 provides a signal on one of its output lines 60 that, when active, conditions the respective AND gate 50 (FIG. 3).

Next, the input circuit 34 will be explained with reference to FIG. This circuit performs the data and MCI separation function and removes the F2 flag and the zeros that follow the five ones.

The bit stream received from inbound link 30 is input to shift register 240 . The contents of register 240 are transferred to Fl in circuits 242 and 244.
and the F2 flag pattern. line 246
The bits shifted out of register 240 above
stream.

A zero deletion circuit 248 is provided. The function of this zero deletion circuit is to delete the zero following five ones. This operation is inhibited when the Fl and F2 flags are detected by the OR circuit.

This OR circuit receives the output signals from one circuit 242 and 244 and provides an inhibit signal on its output line which, when active, inhibits the zero deletion function.

The active output signal from circuit 242 on line 254 is applied to latch 2.
56 and thus the latch 256 provides an active signal at its output 258 for a period corresponding to the bit received by the NCI.

The active output signal on output line 245 from circuit 244 is provided to latch 260, which therefore provides an active signal on its output 262 during the period corresponding to the data received bit.

The bit stream on line 264 from the zero removal circuit is provided to AND gates 266 and 268 to
Gates 266 and 268 are conditioned by the NCI and data period signals on lines 258 and 262, respectively.

Latch 256 is reset by an active signal on line 245 and latch 260 is reset by an active signal on line 254.

An active output signal from circuit 244 sets latch 270. Latch 270 is reset after 8 bits,
A signal that is active during the F2 flag period is connected to its output line 2.
72. This signal is inverted in inverter 274.

A link clock is provided to AND gate 278.

This AND gate 278 is conditioned by an active signal on data period line 262 and an active signal on output line 280 of inverter 274.

AND gate 278 provides a data clock bit signal on its output line 282 during data only periods.

This signal controls the sending of data bits to communication controller 10.

The F1 flag, WSA○ and WSAD fields, and the NCI packet are provided to FIF○ memory 38 by AND gate 266. The data bits are provided to communication controller 10 by AND gate 278.

Next, the output circuit 52 will be explained with reference to FIG. This circuit generates data and NCI bits on outbound link 32-R.

Information read from FIFO memory 48 is provided to input register 300, and the contents of input register 300 are shifted at the outbound link clock speed to line 3.
02 to one input of AND gate 304. AND gate 304 has its second input line 306
1 conditioned when there is an active signal on. This signal is generated by the NC packet control circuit 308.

This control circuit 308 controls unloading of the output FIF◯ memory 48. For each 20 ms period, N
CI packet control circuit 308 causes the contents of the memory to be unloaded and then initiates the data period. Therefore, N.C.
I-packet control circuit 308 provides a signal on line 306 that is active during the NCI period and a signal on line 310 that is active during the data period.

When the signal on line 310 goes active, latch 312 is set for an 8-bit period and provides an active output signal on its output line 314, which output line 314 is connected to F2 insertion circuit 316.
Start.

Data period signal on line 310, link clock signal on line 318, latch 31 inverted with inverter 320
The output signal from 2 is provided to AND gate 322.

Therefore, AND gate 322 provides a data bit clock signal on its output line 70. This data bit read signal controls the transmission of data bits from the communication control device 10 and the operation of the frame filter E24G. Control table 10 empty line 4
- The data bit stream on 1. At the speed of the data bit clock on ll70, OR games 1-3
24. The other input of OR gate 324 is connected to output line 326 of AND 304. Therefore, OR gate 32.1.

The data and contents of memory 48 are transferred to zero insertion circuit 328 during the period in question.

Output line 33Q of circuit 328 is connected to one input of OR gate 332.

When latch 312 is set to indicate that a data period has begun, flag F2 is activated by flag insertion circuit 316.
on the second input line 334 of the OR gate 332. Accordingly, OR gate 332 provides data and NC output as described in connection with FIGS.
The I-stream is provided on outbound link 32-R.

The F1 flag configuration in the information read from memory 48 is detected by circuit 334. The output signal from circuit 334 sets latch 335. Latch 335 provides an inhibit signal on its output line 336. This inhibit signal is applied to one circuit 328 when flag F1 is read from memory 48 and sent to outbound link 32-R.
Prevent zeros from being inserted by .

In addition to the normal data and NCI processing means, the workstation includes transmitting means (shown in FIG. 8) for generating a bit stream to be sent to the transmitting interface 30-T of the node inbound link;
Data bits and M from the bit stream on the receive interface of outbound ring 30-R
Receiving means for retrieving CI bits (shown in Figure 9)
It is equipped with Typical data and NCI processing means are:
Not shown in FIGS. 8 and 9.

The transmitting means shown in FIG. 8 and the circuit 52 shown in FIG. 7 are similar because they perform substantially the same function, and the receiving means shown in FIG. 9 and the circuit 34 shown in FIG. 6 perform substantially the same function. They are similar because they execute.

The transmitting means shown in FIG. 8 includes a data line 400 receiving the data bit stream and MCI packets to be arranged into the streams shown in FIGS. 2-A to 2-C.
and N CI 402.

The data bit is connected to output line 406 of AND gate 404.
line 40 at the rate of the link clock signal generated above.
0.

NCI packets are provided to one circuit 408 .

When there is an NCI packet that can be transmitted, the circuit 408
generates a signal on output line 410 that goes active and
A signal is generated on output line 412 that is active when a packet is not ready for transmission, ie, during data periods.

During the next 20 milliseconds, the AN''D gate 414
conditioned by an active signal on output line 410. An active signal on output line 416 sets latch 418, which remains set for eight bits and then is reset.

The active signal on output line 419 of latch 418 activates F1 insertion circuit 420 which causes the F1 flag to be sent to input fi 422 of OR circuit 424.

Output line 419 of latch 418 is connected to inverter 426 , and output line 428 of inverter 426 is connected to one input of AND gate 430 . Therefore, AND gate 430 is conditioned when an MCI packet must be sent after the insertion of flag F1. AND
The second input line of gate 430 is line 402. Thus, AND gate 430 provides on its output line 432 the MCI packet to be sent to interface 30-T at the link clock rate. To do so, the link clock signal is provided to AND gate 431;
AND gate 431 is conditioned by the output signal from latch 426 and provides the MCI clock signal on its output line 433.

When the signal on line 412 is active during the data period,
Latch 434 is set and remains set for eight bit periods. An output line 436 of latch 434 is connected to one input of OR gate 438. OR gate 43
The second input of 8 is the output line 440 of AND gate 442.
connected to.

AND gate 442 is conditioned to output an active signal to its output line 4 every 20 millisecond period during data only time.
40. Therefore, the OR gate provides an active output signal on line 444 when the F2 flag should be inserted as shown in FIGS. 2-A through 2-C.

This signal activates the F2 flag insertion circuit 446,
Flag insertion circuit 446 causes the F2 flag to be sent to input line 448 of OR gate 424.

The output signal from latch 434 is inverted by inverter 450, and the output line 452 of inverter 450 is connected to one input of AND gate 404. Therefore, AND
Gate 404 is conditioned to provide on its output line 406 a link clock signal at the rate at which data bits are sent on line 400, conditioned during data periods when flag F2 is not inserted.

Denit bit on line 400 and MCI on line 432
The packet passes through the OR gate 454 to the zero insertion circuit 4.
56, zero insertion circuit 456 provides on its output line the data packet and the MCI packet to input line 458 of OR gate 424.

1 when Fl and F2 flags must be sent
Circuit 456 zero insertion function is inhibited.

This is accomplished by an inhibit signal provided on line 462 by OR gate 460. OR gate 46
．． 0's input lines are lines 419 and 444, which provide active signals to be sent to interface 30-T when a flag must be inserted into the bit stream.

Accordingly, OR gate 424 provides on its output line 30-T the bit stream shown in FIGS. 2-A through 2-C.

As shown in FIG. 9, the bit stream received by the workstation on interface 30-R is provided to an input shift register 500. The contents of register 500 are compared in circuits 5Q2 and 504 with the Fl and F2 flag patterns. register 5
The bit stream shifted out from 0o onto line 5o6 is provided to zero removal circuit 508. The function of the zero deletion circuit 508 is to delete the zero following five ones. This operation is performed when the Fl and F2 flags are ORed.
If detected by circuit 510, it is inhibited. OR circuit 510 receives the output signals of 502 and 504;
When active, it provides an inhibit signal on its output line that inhibits the zero deletion function.

An active output signal from circuit 502 on B514 sets latch 516. Therefore, latch 516
It provides an active signal on its output line during the period corresponding to the received bit.

The active output signal from circuit 504 on its output line 515 is provided to latch 520. Therefore, the latch 520 is
line 5 from zero deletion circuit 508 which provides an active signal on its output 522 during the period corresponding to the data received bit.
The bit stream on 24 is fed to AND gates 526 and 528;
are conditioned by the NCI and data period signals on glands 518 and 522, respectively.

Latch 516 is reset by an active signal on line 515 and latch 520 is reset by an active signal on line 514.

An active output signal from circuit 504 sets latch 530. Latch 530 is reset after 8 bits and
A signal that is active during the F2 flag is sent to its output line 5.
32. This signal is inverted by inverter 534.

A bit clock is provided to AND gate 538.

AND gate 538 is conditioned by an active signal on data period line 522 and an active signal on output line 540 of inverter 534.

AND gate 538 provides a data clock bit signal on its output line 542. This signal is AND
Controls the transmission of data bits from output line 544 of gate 528 to the data processing means of the workstation.

AND gate 526 has a third input line 546.

This line is activated when the F1 flag is detected by circuit 502. To do this, latch 5
48 is set when the F1 flag is detected;
Reset after a bit period. Latch 548 provides an output signal that is inverted at inverter 550. Inverter 550 provides an inhibit signal for AND gate 526 on its output line 546.

Therefore, AND gate 536 has on its output line 552,
MCI sent to the workstation's NCI processing means
Supply packets.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram showing three nodes of a communications network in which the mechanism according to the invention may be incorporated; FIG. 2A is an illustration showing the MCI bits and data bit exchange format on a workstation link; FIG. 2B FIG. 2C is an illustration showing the MCI bit and data bit exchange format on the intermediate link; FIG. 2C is an illustration showing the marking frame data structure on the workstation link;
3 is a block diagram of an external adapter incorporating a mechanism according to the present invention; FIG. 4 is a block diagram of the marking frame detector 46 of FIG. 3; and FIG.
The diagram shows the blocks of the marking output table 42 in Figure 3.
6 is a block diagram of the input circuit 34 of FIG. 3, FIG. 7 is a block diagram of the output circuit 52 of FIG. 3, and FIG. 8 is a block diagram of the input circuit 34 of FIG.
FIG. 9 is a block diagram of the transmission means within the workstation that generates the bit stream described in FIG. C; FIG. 9 is capable of retrieving data and NCI information from the bit stream described in FIGS. 1 is a block diagram of a receiving means within a workstation; 10...Communication control device, 12...Upper central processing unit, 16...External adapter, 18...Workstation, 20...Intermediate node/link, 22
...Service processor, 30-T...Transmission interface, 32-R...Reception interface, 34...Input circuit, 38. ...Large cutting edge first-in first-out memory, 40...Outbound link...
Selector, 42... Marking output table, 46
... Marking frame detector, 48 ... First-in first-out memory, 52 ... Output circuit. Applicant International Business Machines Corporation Representative Patent Attorney Takashi Tonmiya - (1 other person) Age 2B, F2 flag, 7iL/10, blind, 11, AraF: Erotsu frame, 7 years old 2C cycle 61 years old 4 mouths

Claims (1)

Claims: A mechanism for enabling data and packetized uncoded information to be exchanged between workstations connected to nodes of a communications network, the nodes being able to comprising data processing means for establishing a session between a workstation and a destination workstation and for routing data exchanged between said workstations, comprising a number of slots separated by delimiter flags;
Each slot is used to transmit a bit of data only, or a bit of uncoded information only, or a bit of uncoded information and data, said data-only slot starting with a first delimiter flag, and said data-only slot starting with a first delimiter flag; at least one uncoded information packet, in which the uncoded information only slot and the uncoded information and data slot begin with a second delimiter flag and include the addresses of the originating workstation and the destination workstation associated with the session; a transmitter for arranging the data bits and uncoded information bits to be transmitted in a workstation bit stream format, followed by a data portion starting with the first flag; the workstation includes a receiver for retrieving data bits and uncoded information bits in the received bit stream in response to detection of the flag; a high-speed bus on which information packets are exchanged; marking means for recording the addresses of the originating workstation and the destination workstation and the address of the node outbound link selected by the data processing means as a result of an initialization phase of the session; a selection for obtaining the address of the selected outbound link for the session from the marking means and generating a selection signal in response to the address of the workstation contained in the unencoded information packet transmitted at the end of the initialization of the session; means for receiving unencoded information; and means for receiving the bit stream to be transmitted by the originating workstation and transmitting the data bits to the data processing means in response to the flag configuration. an outbound link of said network, comprising separating means for transmitting the transmitted uncoded information packets to the uncoded information receiving means and scheduling means for transmitting the uncoded information packets from the uncoded information receiving means to the high speed bus; means for transmitting non-coded information from the express bus in response to a selection signal activated when said outbound link is used to connect said means for transmitting non-coded information and a workstation involved in the session; gating means for transmitting uncoded information packets to the workstation bits; and receiving the data bits from the data processing means and the uncoded information packets from the uncoded information transmitting means;
and formatting means for arranging in a stream format.