JPS61280140A - Shared channel access control circuit - Google Patents

Abstract

PURPOSE:To simplify the titled circuit and to reduce the scale in comparison with control in bit unit by applying buffering for retransmission in shared channel access control functions before the framing such as flag addition or zero bit insertion for ensuring transmittance is executed. CONSTITUTION:A call signal or user information inputted to a data transmission circuit 13 via a selector 15 by a CPU 7 to be sent to a shared channel via a terminal DT are subjected to buffering by a retransmission buffer 14 at the same time and the buffer 14 informs line request to a transmission control circuit 12. The circuit 12 uses ANDing between a line request and an idle detection notice (SACK) informed from an idle detection circuit 6 to inform that the frame is during sending to a collision detection circuit 5 to supervise generation of collision. When the collision detection is informed rom the circuit 5, the stop of frame sending is commanded to a data transmission circuit 13.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a plurality of home devices connected to a home bus connected to a subscriber line via a network termination device, and each home device connected to the bus. When transmitting and receiving information to and from the network terminating device by sharing the upper channel, each in-home device is provided with a controller in case a conflict occurs due to contention in access to the shared channel from each in-home device. The present invention relates to a shared channel access control circuit.

In general, telephone, data, and facsimile communications services,
A network that provides a variety of services such as various communication processing services that process communication information in a single digital communication network is called integrated digital service 1iI (ISDN). In addition, it is necessary to connect a wide variety of home equipment to the home system connected to the network via a network termination device, and in this case, it is possible to economically connect multiple home equipment with one subscriber line. In some cases, a 1-to-n (multipoint) connection such as a bus connection is used.

The present invention relates to a shared channel access control circuit in, for example, such multi-point connected home equipment.

[Conventional technology]

FIG. 4 is a circuit diagram showing the connection status of a plurality of household devices employing the above-mentioned multi-point connection.

In the same figure, TEI and TEi are home equipment and N
T is a home control device as a network terminal device, BuR, B, T
is the receiving and transmitting bus from the home controller NT,
L is a subscriber line. The subscriber line is connected to the in-house control device N.
Connect T to a digital exchange or the like (not shown).

The configuration of only one of the in-home devices TEI to TE is shown in detail, but all the others have similar configurations. In the home equipment TE=, CNT is a shared channel (Dt, DI) access control circuit that transmits call control information, etc.
PXT and DMPXT are multiplexing and demultiplexing circuits, respectively.
Dll is received call control information, D is transmitted call control information, B,
indicates received user information consisting of digitized call signals, data signals to data terminals, etc., and its receiving terminal, and B7 similarly indicates transmitted user information and its transmitting terminal, and terminals B* and By The system transmits and receives digitized user information to and from in-home equipment such as telephones and data terminals.

E is an echo bit, that is, the value of each bit of the upstream channel (transmission bus B, T) where contention may occur is transmitted to the home control device N.
Determined by T, the downstream echo channel (receiving bus BuR)
This is the bit that is sent back. Each home device monitors this echo bit E, and a certain number of “1” bits (
For example, 8 or more), it is determined that the uplink shared channel is empty. If it is empty, the transmission information is sent bit by bit to the shared channel, and if it matches the value of the echo bit, the transmission continues; if it does not match, it is determined that there is a collision, and the transmission is immediately stopped, and the time when it is determined to be empty again. The image will be retransmitted from the first focus.

Also, IN, , IN are negative circuits. Note that all the home devices TE and -TE operate in synchronization with the clock supplied from the network side.

FIG. 5 is a block diagram showing a conventional example of the shared channel access control circuit CNT in FIG. 4.゛In the figure, 1 is a data transmission circuit (1) having HDLC procedure control.
data transmission/reception LSI), R and D are data reception terminals,
T and D are data transmission terminals, R and C are data reception clock input terminals, and TxC is a data transmission clock input terminal. In the data transmitting circuit 1 described above, transmission and reception are performed independently depending on whether each clock is supplied or not.

By stopping the clock supply to the data transmission clock input terminal TXD, the data transmission circuit 1 described above does not stop reception, but interrupts transmission and maintains the data polarity (0 or l) when the clock is stopped. , the subsequent data is transmitted by restarting the clock supply. The transmitting circuit 1 is also a DMA
between the main memory 8 and the processor CP.
It has a function that allows data to be sent and received without going through U7.

It is assumed that the transmitting circuit 1 always transmits a flag sequence (01111110) by being supplied with a clock, except when transmitting a frame. A transmission buffer 2 stores transmission data and retransmits the data only when a collision occurs due to contention for shared channel access.

3 is a frame transmission start/end identification circuit, which detects the beginning position of the data frame sent from the transmission circuit 1;
Detects the end of frame transmission.

4 is a transmission control circuit, which performs transmission waiting control for the transmission circuit 1;
Performs retransmission control to the transmission buffer 2, etc.

Reference numeral 5 denotes a collision detection circuit, which, as mentioned earlier, compares the transmitted data bit and the echo bit (E above) returned from the network terminal equipment bit by bit, and when they do not match, it is determined that there is a collision. Reference numeral 6 denotes a line empty detection circuit, which detects whether the shared channel 1 is empty by counting the number of "1"s in the echo bit E.

Reference numeral 9 denotes a first selector (SELL), which selects whether the transmission data is direct transmission data from the transmission circuit 1 or retransmission data from the transmission buffer 2 at the time of transmission. 10 is the second
This selector (SEL2) is a circuit that sends all "1"s to the shared channel when waiting for transmission or when detecting a collision. Note that 11 is a CPU bus. Terminals Di and E are connected to terminals with the same name of a separation circuit DMPXT shown in FIG. 4, and terminal Dr is connected to terminals with the same name of a multiplexing circuit MPXT also shown in FIG.

Next, we will explain the operation of this access control circuit CNT, but before that, for convenience of explanation, we will explain the high-level data link control procedure (HDLC) taken by the data transmission circuit.
In this section, the format of a frame, which is a unit for transferring arbitrary bit string information and link control information, will be explained.

FIG. 6 is an explanatory diagram showing a frame format in such an HDLC procedure.

As seen in the figure, in the HDLC procedure, arbitrary bit string information and link control information are transmitted using frames, which are transfer units. The start and end of a frame is indicated by a flag sequence F (01111110). The flag sequence F is a signal for frame synchronization, and a frame is formed by transmitting and receiving one or more flag sequences F.
Synchronize frames.

If the same bit string as the flag sequence appears in the information transferred in a frame, the receiving side will consider this to be the end of the frame, which is inconvenient. In order to prevent this, when a pattern of five consecutive bits "1" appears in the frame information, the transmitting side forcibly inserts one bit "0" immediately after it and transmits it, and the receiving side Then 5 consecutive bits “
Transparency of data to be transferred is guaranteed by using a method (zero bit insertion method) of removing one bit "0" received following the pattern "l".

Address field A indicates, in binary code, the address assigned to the station that transmits and receives the frame.

A frame that has the address of the station that receives the frame is a command frame, and a frame that has the address of the station that transmits the frame is a response frame.

! 1 [Field C indicates an instruction for the other station to operate if the frame is a command, or indicates a response to the command in the command frame if the frame is a response. Frame check sequence (FCS: fra
tae checking 5equence)
is a 16-bit sequence for detecting frame transmission errors.

Now that the frame format has been explained, the operation of the access control circuit CNT shown in FIG. 5 will be briefly explained.

Now, assume that the line empty detection circuit 6 determines that the shared channel is empty and notifies the transmission control circuit 4 that transmission is possible. When there is a frame to be transmitted, the processor CPU 7 writes a DMA transfer start command to the data transmitting circuit 1, so that the transmitting circuit 1 receives the transmitted frame data from the main memory 8 under DMA control and sends the data to the data transmitting terminals T and D. Start frame transmission.

At this time, the frame transmission start/end identification circuit 3 detects the start of frame transmission of the data transmitted from the data transmission circuit 1 by detecting a pattern different from the flag, and indicates that frame transmission has started to the transmission control circuit 4. If the line empty detection circuit 6 indicates that transmission is possible, the transmission clock is continued to be supplied to the data transmission circuit 1, and data writing to the transmission buffer 2 is started from the flag at the frame head position.

If the line empty detection circuit 6 indicates that the line cannot be sent,
It waits for transmission, stops supplying the transmission clock to the data transmission circuit 1, interrupts transmission data from the data transmission terminals T and D, and disables data writing to the transmission buffer 2. The shared channel becomes "empty" and the line empty detection circuit 6 issues a signal indicating that line transmission is possible, and at the same time restarts the supply of the transmission clock to the data transmission circuit 1 and starts writing data to the transmission buffer 2 from the flag at the beginning of the frame.

The above describes the case where data transmission is started by a command from the processor CPU 7, but in the case where the data transmission circuit 1 autonomously sends out a frame without going through the processor CPU 7, the transmission of the frame starts from the data sending terminals T and D. After that, follow the same steps.

When the collision detection circuit 5 detects a collision during frame transmission to the shared channel, it notifies the transmission buffer 2 and the transmission control circuit 4 (COD), and also selects all data by the selector 10 for the shared channel. “1” (called ink frame time fill)
is sent immediately after the collision.

At this time, the data transmission circuit 1 continues frame transmission from the data transmission terminals T and D without being involved in the collision state, and continues writing to the transmission buffer 2.

When the transmission control circuit 4 receives a notification (COD) that a collision has occurred from the collision detection circuit 5, it waits until the line empty detection circuit 6 indicates that the shared channel is empty and that transmission is possible. The appearance of the message indicates to the transmission buffer 2 that retransmission is possible.

In the transmission buffer 2, retransmission is started from the beginning of the frame in which the collision has occurred by opening the gate of the first selector 9 (SELI). Since it is possible that retransmitted frames will collide again, the transmission buffer 2 is configured to repeat retransmission no matter how many times collisions occur.

When the frame transmission start/end identification circuit 3 detects the end of frame transmission from the data transmission circuit 1, it writes data to the transmission buffer 2 up to the end flag and then stops.

The conventional shared channel access control circuit as described above with reference to FIG.
93094) was configured as described above, it required a flag pattern detection circuit to detect the start and end of frame transmission. The retransmission buffer, which buffers frames for retransmission, cannot be controlled in units of octets due to the "0" bit inserted into the transmitted frames to ensure transparency in the network, but requires control in units of bits. This has the disadvantage that the buffer control circuit becomes complicated and the circuit scale increases.

[Problem that the invention seeks to solve]

Therefore, in the present invention, in the shared channel access control circuit, it is possible to eliminate the need for the flag slam detection circuit that was conventionally required, to make it possible to control the retransmission buffer in units of octets, and to simplify the buffer control circuit. The problem to be solved is to reduce the size of the system, and it is therefore an object of the present invention to provide a shared channel access control circuit that makes this possible.

[Means and effects for solving the problem] Therefore, in the shared channel access control circuit according to the present invention, a retransmission buffer circuit is arranged on the input side of the data transmission circuit, and the information to be transmitted, including the flag sequence, is The information to be retransmitted is buffered in an information format without zero bits inserted to ensure line transparency, and under control from the transmission control circuit, at the time of retransmission, the information to be retransmitted is sent to the data transmission circuit in the above information format. The data transmission circuit assembles this information into frame configuration information and retransmits it, thereby simplifying the buffer control circuit.

In other words, in the present invention, buffering in preparation for retransmission of outgoing data is performed at a stage before framing (assembling into a frame format) for sending out data to a shared channel. The main feature of this technology is that a buffer for data retransmission is provided in front of the framing circuit, and call control signals and user information to be buffered can be controlled in units of octets. Simply put, the difference lies in the fact that there is no need to detect the beginning of a frame during buffering, so the detection circuit is not required.

〔Example〕

The present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, 5 is a collision detection circuit, 6 is an empty detection circuit, 7 is a CPU, 8 is a main memory, 10 is a transmission data selector, 11 is a CPU bus, 12 is a transmission control circuit, 13 is a data transmission circuit, and 14 is a transmission data selector. A retransmission buffer 15 is a transmission frame selector.

Comparing the embodiment of the present invention shown in FIG. 1 with the conventional circuit shown in FIG. 5, the retransmission buffer is located on the input side of the data transmission circuit in the former, and on the output side in the latter. Therefore, it will be recognized that the number of control lines for the retransmission buffer is significantly reduced in the embodiment of the present invention compared to the conventional circuit. As previously explained, this is the greatest feature of the present invention.

Next, the circuit operation will be explained with reference to FIG.

the CPU to send out to the shared channel via the terminal
The call control signal and user information inputted to the data transmission circuit 13 via the selector 15 by the retransmission buffer 14 are simultaneously buffered by the retransmission buffer 14, and the retransmission buffer 14 notifies the transmission control circuit 12 of a line request. . The transmission control circuit 12 notifies the collision detection circuit 5 that a frame is being sent based on the logical product of the line request and the vacancy detection notification (SACK) notified from the vacancy detection circuit 6, and causes the collision detection circuit 5 to monitor the occurrence of a collision. When the collision detection circuit 5 notifies the detection of a collision, it instructs the data transmission circuit 13 to stop frame transmission.

Thereafter, when the empty detection circuit 6 notifies that the shared channel is empty, the transmission control circuit 12 sends a transmission character request to the retransmission buffer 14 via the data transmission circuit 13, and sends a transmission character request to the retransmission buffer 14, which has been buffered until then. Data transmission circuit 1 transmits call control signals and user information via frame selector 15
3, and when the retransmission buffer 14 finishes outputting the buffered call control signal and user information,
The CPU 7 outputs subsequent call control signals and user information. Here, the call control signal and user information output to the shared channel are read out from the main memo I78 by the CPU 7 and transferred to the data transmission circuit 13. Also CPU7
The call control signal and user information directly transmitted by the retransmission buffer 14 and the call control signal and user information retransmitted from the retransmission buffer 14 are selected by the transmission frame selector 15, and when a collision occurs, the transmission data selector 10 selects the data Data of "1" is selected instead of the data from the transmitting circuit 13, and frame transmission by the data transmitting circuit 13 to the shared channel is immediately stopped.

Note that, as shown in the figure, the data transmission circuit 13 and the CPU 7 are connected via the CPU bus 11.

Now, the above is a general explanation of the shared channel access control circuit according to the present invention, but the case where this control circuit is applied to the above-mentioned I5DN home system will be explained below.

As mentioned earlier, L5DN is a network that attempts to provide various services in a unified manner, and the construction of such L5DN is actually a worldwide issue, and CCIT
The T (International Telegraph and Telephone Advisory Committee) is currently considering its standardization.

As a link to this, a common channel protocol is being considered as a protocol defined for the interface between the 15DN and users (ISDN user network interface).

As the name suggests, this common channel type protocol controls multiple information channels (the information channel is called the B channel for convenience) using a common signal channel (the signal channel is called the D channel for convenience in this protocol). This is a protocol that performs As mentioned earlier, when a multipoint configuration is used to accommodate multiple home devices, contention for access from each home device to the D channel shared for control signal transfer occurs, so the control It goes without saying that the shared channel access control circuit according to the present invention is used for this purpose. Probably not.

Now, the D channel frame of the I5DN user network interface having the background as explained above is shown in FIG. 2 (8), and the details of the address field therein are shown in FIG.

In FIG. 2(a), 31 is a frame start flag (1
32 is an address field (2 octets), 33 is a control field (1 to 2 octets), 34 is an information field (0 to 260 octets)
, 35 is Fe2 (2 octets), and 36 is a frame end flag (1 octet).

A D channel frame is a minimum of 3 octets (flag, Fe
2, excluding bit 0 inserted to ensure transparency), and in the L5DN user network interface, the terminal (home equipment) has finished sending 2 octets of the address field with a unique value, and continues. Since a collision is detected before the transmission of the control field is started, the collision detection circuit 5 does not need to continue detecting until the end flag, and when the collision occurrence monitoring ends, the CPU 7 notifies the data transmission circuit 13 of the final character. The retransmission buffer 14 notifies the transmission control circuit 12 that this has been done.

With such a configuration, the data transmission circuit 13
A circuit (identification circuit 3 in FIG. 5) that monitors the output of the shared channel frame and detects the start and end of the shared channel frame is no longer required, and the buffer 14 for frame retransmission can be controlled in units of octets. buffer 1
This means that the circuit scale of the control circuit No. 4 can be reduced.

Although the structure of the D channel frame shown in FIG. 2(a) appears to be the same as the structure of the frame in the HDLC procedure shown in FIG. 6, the structure of the address field in the frame is different between the former and the latter. The former case is shown in Figure 2).

In Fig. 2(b), for application to the multipoint configuration using the bus mentioned above, a termination point identifier (TEI) is provided in the 16-bit address field, and each in-home device has a different TEI. By assigning a value, multiple data link connections can be set at the same time. In addition, E is an extension bit, C/R is a command response bit, and SAP I is a service access point identifier.

FIG. 3 is a block diagram showing a second embodiment of the invention. In the figure, 5 is a collision detection circuit, 6 is an empty detection circuit,
7 is a CPU, 8 is a main memory, 10 is a transmission data selector, 11 is a CPU bus, 13 is a data transmission circuit, 16
1 is a retransmission buffer, and 17 is a transmission control circuit.

To explain the circuit operation of this embodiment, the retransmission buffer 16
is a buffer (RAM) in which a write address and a read address can be specified separately. When the CPU 7 writes data to the buffer 16, the buffer 16 puffs it, increases the write address, and sends the data to the data transmission circuit. When data is output to 13, the read address is increased, and if the write address and read address match, the CPU 7 is notified of a write request.

Call control signals and user information read from the main memory 8 by the CPU 7 and input to the retransmission buffer 16 for output to the shared channel are buffered into the buffer 16. The buffer 16 outputs input call control signals and user information to the data transmission circuit 13 and also notifies the transmission control circuit 17 of a line request. Check the channel empty notification and enable frame transmission to the data transmission circuit 13 (
SDW), and the collision detection circuit 5 and empty detection circuit 6
Notify that the frame is being sent.

The collision detection circuit 5 monitors the occurrence of a collision by notification during frame transmission, and when a collision is detected, it notifies the communication control circuit 17 (COD) L.
3 is interrupted and the read address of the retransmission buffer 16 is reset.

The buffer 16 outputs the buffer-pulled call control signal and the first octet of user information to the data transmission circuit 3 again, and notifies the transmission control circuit 17 of a line request.

Thereafter, when the emptiness detection circuit 6 notifies that the shared channel is empty, the transmission control circuit 17 notifies the data transmission circuit 13 that frame transmission is possible, and the data transmission circuit 13 starts transmitting frames again.

When frame retransmission begins, the retransmission buffer 16 outputs the call control signal and user information that were buffered until then to the data transmission circuit 13 in response to a request from the data transmission circuit 13. When all the contents have been output, that is, when the read address and write address match, the CPU 7 is requested to send the remaining call control signals and user information.

Furthermore, as described above, when applied to the 15DN user network interface, collisions are detected at the latest before the bits following the address field (2 octets) of the outgoing shared channel frame are sent to the shared channel, so the retransmission buffer is 116 should have a buffer capacity of at least 3 octets. Call control signals and user information output to the shared channel are stored in the main memory 8 by the CPU 7.
It goes without saying that the data is read from the data source and written to the retransmission buffer 16.

When a collision occurs, the transmission data selector 10 selects "1" data instead of the data from the transmission circuit 13, and immediately stops frame transmission to the D channel.

Needless to say, the retransmission buffer 16 and the CPU 7 are connected by the CPU bus 11.

This configuration eliminates the need for a transmission frame selector (15 in Figure 1), and also eliminates the need for a circuit for monitoring the output of the data transmission circuit and detecting the start and end of a shared channel frame (see Figure 5). 3) is no longer necessary,
The buffer for frame retransmission can be controlled in units of octets, and the scale of the buffer control circuit can be reduced.

〔Effect of the invention〕

As explained above, according to the present invention, buffering for retransmission is performed in the shared channel access control function.
By adding flags and inserting zero bits to ensure transparency before framing, there is no need for a circuit to detect the start and end of a shared channel frame.
Buffer 1 control for retransmission can also be performed in units of octets, so the circuit is simpler and smaller in scale than when controlled in units of focus, and the circuit scale of the entire shared channel access control circuit can be made smaller than before. There are advantages.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 (
a) is an explanatory diagram showing a D channel frame; FIG. 2) is an explanatory diagram showing details of the address field of the D channel frame; FIG. is a circuit diagram showing the connection status of multiple home devices using multi-point connections, Fig. 5 is a block diagram showing a conventional example of a shared channel access control circuit, and Fig. 6 is an HDL
An explanatory diagram showing the format of a frame in C procedure,
It is. Explanation of symbols 1... Data transmission circuit, 2... Retransmission buffer, 3
...Frame sending start/end identification circuit, 4...Transmission control circuit, 5...Collision detection circuit, 6...Empty detection circuit, 7...CPU, 8...Main memory, 9... ... Transmission frame selector, 10... Transmission data selector,
11... CPU bus, 12... Transmission control circuit, 13
...Data transmission circuit, 14...Retransmission buffer, 1
5... Transmission frame selector, 16... Retransmission buffer 1.17... Transmission control circuit, 31... Frame start flag, 32... Address field, 33...
control field, 34... information field,
35...Fe2, 36... Termination flag.

Claims (1)

[Claims] 1) A plurality of home devices are connected to a home bus connected to a subscriber line via a network termination device, and each home device shares a channel on the bus to terminate the network termination. In a shared channel access control circuit provided in each in-home device in case a collision occurs due to contention in access to the shared channel from each in-home device when transmitting and receiving information to and from the device, the network terminal A circuit that detects the availability of a shared channel based on the shared channel usage status information from the device, a circuit that also detects access conflicts to the shared channel based on the shared channel usage status information, a data transmission circuit that transmits information in a frame structure, and a data transmission circuit that transmits information in a frame structure. It comprises at least a retransmission buffer circuit that buffers information and prepares for retransmission, and a transmission control circuit, and the transmission control circuit detects the shared channel only when the vacancy of the shared channel is detected by the vacancy detection circuit. allowing the data transmission circuit to transmit information, and when the collision detection circuit detects an access collision to the shared channel, stopping the information transmission by the data transmission circuit; and then, when the shared channel is detected to be empty; The retransmission buffer circuit is used to retransmit already transmitted data that may be lost due to collision, and the retransmission buffer circuit is arranged on the input side of the data transmission circuit, The information to be retransmitted is buffered in an information format that does not include a flag sequence and does not have zero bits inserted to ensure network transparency, and under control from the transmission control circuit, the information to be retransmitted is supplying the data in the information format to a data transmission circuit;
A shared channel access control circuit characterized in that the data transmission circuit assembles the information into frame structure information and retransmits it.