JPS5958936A - Packet switching control system - Google Patents

Abstract

PURPOSE:To attain a high speed packet switching, by using the right of usage being the guarantee of receiving of a packet for an addressed resource of opposite party and the right of usage of a common data bus as a token, so as to transmit/receive the data on a control bus provided as a loop. CONSTITUTION:When there exists a packet to be transferred in a transmission buffer memory of the own channel, a corresponding RVi is set to busy state (RVi=1) and the occupancy of the right of usage is declared, by monitoring a control bus 42 with an I/D circuit and a busy/idle detecting circuit and waiting for an RVi signal having a number coincident with the address of the packet, i.e., the idle state (not in use RVi=0) of the opposed receiving buffer memory. The packet in the transmission buffer memory is transferred through the common data bus 41. A DB of the control bus signal is reset to the idle state (DB= 0) by detecting the end of packet transfer and the right of usage of common data bus is given up.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a packet switching control system used for data transmission.

(2) Technical Background Exchange methods in data communication include circuit switching and packet switching. While circuit switching is used for telephones and other devices and is performed by physically connecting transmission channels, packet switching divides the data to be transmitted into small blocks, and part of each block includes the address of the other party and the address of the other party. and outgoing i
f! It is treated as one packet by adding the address of It, etc., and transmitted to the desired communication destination as a unit under the control of the switching circuit.

(3) Prior Art and Problems In the conventional packet switching method, the packet is once imported into all computers under computer control, and then the destination address is fully determined and transferred to the corresponding output port. This method is Baku... 11. All needles E'i: ! ,Q
Since it is necessary to read hc, one pile is long when exchanging.
There are problems such as the need for large-scale hardware since a total of n machines are used for replacement.0 (4) Purpose of the Invention The purpose of the present invention is to solve the problems common to the conventional methods described above. Based on the idea that the right to use the data bus and the right to use the phase fJtR are transmitted and received through the control O-/L/bus in a loop, the common data bus and reception hub memory can be transferred without worrying about large-scale hardware. The purpose is to enable high-speed packet exchange without causing contention.

(5) Structure of the Invention In the present invention, in a bucket exchange control method in which packetized data input to which at least an address indicating a destination has been added is transferred to an arbitrary party indicated by the destination address of the packet, the bucket -Vl- is transmitted via a common data bus, and the right to use the common data bus and the destination partner resource are guaranteed to be accepted by the packet. The entire feature is that data packets are transmitted through a control bus provided in the control bus, thereby transmitting data packets without contention.
Sotho father exchange 1tIIJ method is promoted.

(6. Embodiment of the Invention An apparatus for performing a packet switching control system as an embodiment of the present invention is shown in FIG. (N+1) channel corresponding units (CH
It is composed of O to Cl1n)2.

The common section 3 includes a shift register 34 (reference memory circuit), a reception frame synchronization detection circuit 33, a frame memory circuit 32, and a timing circuit 31.

FIG. 2 shows the configuration of the channel correspondence section 2 in FIG. 1. The channel correspondence section 2 includes a client transmitting section 4,
0 comprising a packet receiving section 5 and a token control section 6
The packet transmitter 4 includes a shift register (SR) 13 and a shift register 1 that receive signals from each workstation.
The synchronization detection circuit (SYNCDET112
, a destination address circuit (T)A) 11 which receives the outputs of the synchronization detection circuit 12 and the shift register 13, and a common data node (DBU) which receives the outputs of the shift register 13.
s) Transmit bar memory (TB) that supplies output to 41
Consists of M114. The packet receiving unit 5 includes a shift register (SR,
) 15, Synchronization detection circuit (S'YI-JCDET l 17, Address-iron structure circuit (AI) receiving the output of the synchronization detection circuit 17 and shift register 15) D DEi' l18,
and the outputs of the shift register 15 and the address-structure output circuit 18, and the outputs are sent to the works station. Token fltlJ gvffB 6 (d control bus synchronous clock (CL)
SC) 19, time slot counter 19 and destination address circuit 11 output condition 1'1'' constant circuit (
TBSC120, busy/idle detection circuit CB that returns the output of the condition determination circuit 20 to the condition-specific ffM circuit 20, 'I DET)21. A busy/idle insertion circuit 22 receives the output of the condition determination circuit 20, and an insert/drol tube (receives the output of the busy/idle insertion circuit 22 and supplies it to the output busy/idle detection circuit 21).
I/D) circuit 23, and a delay circuit (DL) 24'i.

For each of the above-mentioned elements, the common section 3 sends a control hash synchronous clock (CLKl) and a phase signal (PHi
l is supplied to the time slot counter 19, and the control bus 42 is connected to the inputs of the I/D circuit 23 and the delay circuit 24. I/i) circuit 23 and delay circuit 2
One of the outputs 4 and 4 is selected by the switch 25 and connected to the inputs of the I/D circuit 23 and delay circuit 24 of the next channel via the control bus 42 again.

Next, the operations of the above-mentioned common 0 section 3 and channel correspondence section 2 will be explained. Common part 3 is VA2' corresponding to each channel.
Control bus 42 connected in cascade via c
In other words, it has the function of a device called a constant looper, which performs all the controls such that the frames shown in FIG. 3(2) are always rotated by one frame. Shift register: (0 synchronization detection circuit 33 that receives the 4fd control bus signal, stores the signal, and sends it to the frame memory 32)
The entire signal from the shift register 34 is the 7 lag of the signal ■
Position 14'fL: Detected and sends a flag timing signal to the timing circuit 31. In the timing circuit 31VC, a control is performed to notify each channel corresponding section 2 of the evening/f mink of the control bus 42. Bus synchronous clock (CLI (l) and phase signal (PI
Ii) f'51 will be born. The waveform diagram of the control bus synchronization clock is shown in Figure 4 (4), and the waveform diagram of the phase signal for each channel corresponding section is shown in Figure 4 (1) to 3).
is shown. The timing circuit 31 also generates all write and read timing signals for the frame memory circuit 32.

In the Baku-no-do transmitter 4, the shift register 13 receives packets transferred from the workstation (see FIG. 3 (1)), all of them are detected by the synchronization detection circuit 12 (as flags), and the beginning of the Baku-soto is detected. , detects the destination address section (DAI and final), and stores the destination address section in the destination address circuit 11 and the packet in the transmission buffer memory 14.The contents stored in the transmission buffer memory 14 will be explained later. When the token control unit 6 determines that the common data bus 41 is allowed to be used, the packet receiving unit 5 receives the packet sent to the common data bus 41 by the shift register 15. , the synchronization detection circuit 17 detects the flag, sends the destination address part of the packet node to the address match detection circuit 18, and the address match detection circuit 18 compares it with the address given in advance to the channel itself, All signals are selectively received and stored in the reception buffer memory 16.

The contents stored in the reception bus memory 16 are sent to the workstation.In the token control unit 6, upon receiving the control bus synchronization clock and )1-Z address supplied from the common unit 3, Control bus 421C function to generate synchronized timing and control bus 42 each 1.-
It has a function of monitoring busy/idle and changing the token only when condition 1c is satisfied.The signal from the control bus 42 passes through the 1./D circuit 23 or the delay circuit 24 and is sent to the next channel. .If there is no sending signal ∆ in that channel, the VC is !;I converter 25 & the delay circuit 24 is selected.The I/D circuit 23 is 1
All steps are delayed, and the control bus 42
The busy/idle detector 21 detects the contents of '1i-j' of 0 timeslot counter 19, which supplies a timing signal to the condition determination circuit 20 in response to the control bus synchronization O+/I and phased St.

(Common to the following) - 1 Tahas use and the use of the opponent's resources (Uke 1 Ayaba / Famemo IJ) 1・j of gaining and abandoning the use position
Let's talk about H.

(1) When the packet to be transferred to the bus memory 14 is obtained when the token is acquired and discarded from the own channel V, (,1) ko, / l・U −/L/buzz 42 'c
l/i,) circuit 23 and the busy1/idle detection circuit, the RVi signal with the number r matching the destination address of the packet (see Fig. Use, R
Wait for Vi2 ()) and make the corresponding RVi busy (RVi
= 1) to declare possession of the usage right. Matching with the destination address is performed by the condition determination circuit 20, and writing to the control bus signal is performed by the busy/idle insertion circuit 22.
and is performed in the I/D circuit 23.

(b) Then, the common data bus 41 becomes idle (D
B=0. (See Figure 3 (2)).
Set to e-busy (DB=1) to declare exclusive use of the usage right.

(c) Packet If in transmission buffer memory - transferred via common data bus 41;

(d) DBk idle (I)E=0) of the control bus signal when all packet transfer completions are detected.
, and the right to use the common FM data bus is released.

(2) Abandoning tokens in the receiving destination channel After monitoring the packets flowing on the common data bus 41 and storing the packets for itself in the receiving buffer memory 16, the token in the receiving buffer memory 16 is 1 node It waits until it becomes empty (RVi == 41) for its own channel band, and indicates that the right to use the receive buffer is -1i+4.

(7) Effect of Weight According to the present invention, it is possible to achieve high-speed data bus and reception bar... Bakut exchange can be performed.

4.Drawing iri'3 q"i: Explanation of the 11th bacterium is the first invention of the invention ``Baku as a small...
F Sf conversion control method: Professional circuit diagram of the device that performs it: 4↓Figure 2 is block 1 of the channel corresponding part of the device in Figure 1
Cock circuit diagram, 2n31 (1) is the packet former...1, figure without gold, Figure 3 (2) is εif.
Tips Used in the Roll Bus Figure 4 and FIG. 4 are waveform diagrams of timing signals used in the first factor device.

1...--Pakso [-father replacement control device, 2...
・Channel compatible fitS, 3... both) arc part, 4
・・・・・・Packet/1・Transmitter, 5・・・・Bakubutto receiver, 6・・・1・−kun control'l Hji, l
l...Destination address circuit 1.12...Synchronous output 11M, 13...Shift register, 14
・・・・・・＋云(r:;Ha sofa memory, 15...
...Shift register, l! i--Receiving buffer memory, 17... Doujin circulation 1116.18.
...7)"L/S coincidence detection circuit, 19...
Quimslo Soto counter, 20...Condition 1'
1] Constant circuit, 21... Busy/'idle detection circuit, 22... Busy/A r dollar insertion circuit, 33
・Old...-f insert/drop circuit, 24...
・Delay interval 1116.25...Kirisuki, 31...
...Timing times; 32...Frame memory circuit, 33...Received complaint synchronization IJj)
i, ll path, 34...shift register, 41
...Common j-tabus, 42 ...Control bus.

Office license applicant Fujitsu patent application agent Patent attorney Akira Aoki Patent attorney Kazuyuki Nishidate Patent attorney 1) Sweet potato man Patent Attorney Yamaguchi ut3 Front page 2nd time

Claims (1)

[Claims] In a packet switching control method in which packetized data input to which at least an address indicating a destination is added is transferred to an arbitrary destination indicated by the destination address of the packet, the packet is transmitted via a common data bus, and the common data The right to use the bus and the right to use the other resource at the destination, which guarantees that the packet will be accepted, are provided as tokens in a loop, and the control bus is used to receive and receive data back and forth without contention. A packet switching control method characterized by full transmission.