JPS595669A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS595669A
JPS595669A JP11515582A JP11515582A JPS595669A JP S595669 A JPS595669 A JP S595669A JP 11515582 A JP11515582 A JP 11515582A JP 11515582 A JP11515582 A JP 11515582A JP S595669 A JPS595669 A JP S595669A
Authority
JP
Japan
Prior art keywords
electrode
insulating material
metal
silicon element
bonded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11515582A
Other languages
Japanese (ja)
Inventor
Hitoshi Matsuzaki
均 松崎
Shuroku Sakurada
桜田 修六
Eiji Harada
原田 英次
Toshiyuki Ozeki
大関 俊行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11515582A priority Critical patent/JPS595669A/en
Publication of JPS595669A publication Critical patent/JPS595669A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thyristors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To provide a semiconductor device which has excellent mass productivity and a minute electrode structure and wherein metallic electrode foils for a cathode and a gate are not contacted in assembling, by providing two relay metallic electrodes at a part of the main surface of an insulating material, and connecting each relay metallic electrode and a specified part of a silicon element, which is formed into a minute pattern with two comb-shaped electrode metal foils, by using a solder. CONSTITUTION:A relay metallic electrode 31c for a gate and a relay metallic electrode 31e for a cathode are bonded to an annular ceramic insulating material 31a by silver solders 31b and 31d. A composition of metal and an insulating material 31 is formed in this way. A silicon element 1 is contacted with facing protruded parts 31f and 31g of the inner wall of the opening of the composition of the metal and insulating material 31 and the position of the element 1 is fixed. Assembling is performed as follows: the tooth parts of electrode metallic foils 3 and 4 are temporarily soldered to the specified parts of the silicon element 1; a solder 7, the composition of the metal and insulating material 31, the silicon element 1 and the electrode metallic foils 34 which are soldered together, and solders 32 and 33 are set on an anode electrde plate 6; a weight is mounted on the device; and the device is made to pass in a furnace.

Description

【発明の詳細な説明】 本発明は半導体装置に係り、特に微細パターン′構造を
有する半導体素子に好適な成極構造に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a polarization structure suitable for a semiconductor element having a fine pattern structure.

ゲートターンオフサイリスク(以下GTO)やトランジ
スタはその半導体素子のカンード側あるいはエミッタ側
が微細パターンとなっている。
A gate turn-off transistor (hereinafter referred to as GTO) or a transistor has a fine pattern on the cando side or emitter side of the semiconductor element.

GTOを例にとるに、微細パターンとなっているnエミ
ツタ層およびpペース層上の電極膜に金属箔からなる引
出し電・甑を牛田付けして、この引出し電極により外部
回路と接続するような構造、いわゆる微細電極構造を採
用する理由は、大きな主回路1流を制御電流でオン・オ
フ制御するため、主回路および制御回路の半導体素子表
面の屯極膜における電位降下が素子のスイッチング特性
に影響しないようにするためである。
Taking GTO as an example, a lead electrode made of metal foil is attached to the electrode film on the finely patterned n emitter layer and p space layer, and the lead electrode is connected to an external circuit. The reason for adopting a so-called microelectrode structure is that because one large main circuit current is controlled on and off by a control current, the potential drop in the electrode film on the surface of the semiconductor element in the main circuit and control circuit affects the switching characteristics of the element. This is to avoid any influence.

微細電極構造の従来例を第1図に示す。A conventional example of a fine electrode structure is shown in FIG.

図において、絶縁材11a、12as中継金属電極11
C,12C%およびこれらを接着する銀鑞11b、12
b、とからなる金属・絶縁材複合体11.12は櫛状の
電極金属W33,4と図示していない外部鑞極とを接続
するための中継体であり、それぞれカンード、ゲート用
でありシリコン素子1とともにアノード電極板6の上に
半田7で接着される。
In the figure, insulating materials 11a, 12as relay metal electrodes 11
C, 12C% and silver solder 11b, 12 to bond these
A metal/insulating material composite 11.12 consisting of b and 11.12 is a relay body for connecting the comb-shaped electrode metal W33, 4 and an external solder electrode (not shown), and is for candos and gates, respectively. It is bonded together with the element 1 onto the anode electrode plate 6 with solder 7.

またカソード電極金属箔3、ゲート電極金属箔4はシリ
コン素子1上の@、@膜2とは半田5で接着され、金属
・絶縁材複合体11.12とはそれぞれ半田13.14
で接着されている。
Further, the cathode electrode metal foil 3 and the gate electrode metal foil 4 are bonded to the @ and @ films 2 on the silicon element 1 with solder 5, and are bonded to the metal/insulating material composite 11.12 with solder 13.14, respectively.
It is glued with.

この微細電極構造の組立は例えば以下のように行なわれ
る。
Assembly of this fine electrode structure is performed, for example, as follows.

まず、11:極金属箔3,4をそれぞれ、シリコン素子
1上の電極膜2と半田5で仮半田付しておいて、各部品
、および接着用半田を固定用治具にセットする。固定用
治具は各部品が所定の位置に配置されるように設計され
ている。つぎにセットされたものをベルトコンベアにの
せ加熱炉内を通過させる。固定用治具が高温部を通過す
ると半田が溶けて各部品が接着される。
First, 11: The metal foils 3 and 4 are temporarily soldered to the electrode film 2 on the silicon element 1 with the solder 5, and each component and the adhesive solder are set in a fixing jig. The fixing jig is designed so that each component is placed in a predetermined position. Next, the set items are placed on a belt conveyor and passed through a heating furnace. When the fixing jig passes through a high temperature area, the solder melts and the parts are bonded together.

正常な接着がされると第2図(a)のように電極金属箔
3,4がシリコン素子1上の電極膜2に半田5で接着爆
れ−Cいる。
When normal adhesion is achieved, the electrode metal foils 3 and 4 are bonded to the electrode film 2 on the silicon element 1 by the solder 5, as shown in FIG. 2(a).

とζろが従来の構造では高?M部の通過後第2図(1)
)のようにゲート賀匪金属箔4とカソード1(イ1鉢金
桝箔3とが接触して1〜まう不良が多く発生した。
Is it high in the conventional structure? Figure 2 (1) after passing through M section
), many defects occurred due to contact between the gate metal foil 4 and the cathode 1 (1) and the metal foil 3.

この接触はpベース層11)とnエミッタ1aを短絡す
るためシリコン素子】のfl+IJ御能カを失なわせる
This contact short-circuits the p base layer 11) and the n emitter 1a, thereby causing the silicon element to lose its fl+IJ capability.

この不良原因を究明した結果、以下のことが判明した。As a result of investigating the cause of this defect, the following was discovered.

金鴇・絶縁材複合体11.12およびシリコン素子1と
は固定用治具により固定されているが、治具のしよめあ
い寸法公差があるため各部品が加熱炉を通過するときの
撮動により種々の方向へずれる。例えば金pし絶縁材複
合体11.12が、第1図(a)のY−Yの方向にそれ
ぞれ反対の方向にずhると、′NL極金Mffi3.4
はそれぞれ金属・絶縁相複合体11.12−ヒにのせら
れてお一部、組立時には電極金属箔3.4の上には適当
なウェイトがのせられているため、金属・絶縁材複合体
11.12と共に電極金嘴箔3,4が互いに反対方向に
ずれ、シリコン素子1上で第2図(bJのような接触不
良を生じる。
The gold-plated/insulating material composite 11.12 and the silicon element 1 are fixed by a fixing jig, but due to the dimensional tolerance of the jig, the images were taken as each part passed through the heating furnace. Shifts in various directions due to For example, if the gold plating insulating material composite 11.12 is shifted in opposite directions in the Y-Y direction in FIG.
are partially placed on the metal/insulating phase composites 11 and 12-H, respectively, and since an appropriate weight is placed on the electrode metal foil 3.4 during assembly, the metal/insulating material composite 11. .12, the electrode metal beak foils 3 and 4 shift in opposite directions, resulting in poor contact on the silicon element 1 as shown in FIG. 2 (bJ).

GTOはその主電流制御のためnエミツタ層1aを微細
に分割しており、電極膜2の間隔は通常0.1〜0.2
trm程度である。従って金属・絶縁材複合体11.1
2が組立時に独立にずれる構造では、通常の治具公差に
よりゲート用ル極金属箔4とカソード用電極金属箔3と
が接触する可能性が大きい。
In GTO, the n emitter layer 1a is finely divided in order to control its main current, and the spacing between the electrode films 2 is usually 0.1 to 0.2.
It is about trm. Therefore, metal-insulating composites 11.1
In a structure in which the electrode metal foils 2 and 2 are independently shifted during assembly, there is a high possibility that the gate electrode metal foil 4 and the cathode electrode metal foil 3 will come into contact due to normal jig tolerances.

また金属・絶縁材複合体11.12が第1図のY−Yの
同一方向にずれても、シリコン素子1に対してずれが生
じ、第2図(C)のようにカソード。
Furthermore, even if the metal/insulating material composites 11 and 12 are displaced in the same direction along Y-Y in FIG. 1, they will be displaced relative to the silicon element 1, and the cathode will be damaged as shown in FIG. 2(C).

ゲート用両を極金属箔3.4が接触不良も生じた。There was also a contact failure between the metal foils 3 and 4 for both gates.

これはシリコン素子1が金属・絶縁材複合体11゜12
に対し組立時に固定治具の公差内で独立にずれるためで
ある。
In this case, the silicon element 1 is a metal/insulating material composite 11°12
This is because they shift independently within the tolerance of the fixing jig during assembly.

以上のように従来例では組立時にゲート、カソードの短
絡不良が発生しやすく、微細電極構造の量産上の大きな
問題点となっていた。
As described above, in the conventional example, short-circuit defects between the gate and the cathode are likely to occur during assembly, which has been a major problem in mass production of fine electrode structures.

本発明の目的は前記のような組立時にカソード。The purpose of the present invention is to assemble the cathode as described above.

ゲート用電極金属箔の接触がおきることのない量産性の
よい倣細唯罹構造の半導体装置を提供することにある。
It is an object of the present invention to provide a semiconductor device having a shape-only structure that is easy to mass-produce and is free from contact between gate electrode metal foils.

本発明の特徴とするところは、環状の絶縁材の孔内にシ
リコン素子をその周縁が外接するように収納せしめ、絶
縁材の主面の一部に2個の中継金ス・4電極を設け、各
中継金属′電極と上記シリコン素子の微細パターンとな
った所定個所を2個の櫛状の1甑金属箔で半田によ多接
続していることにある。
The present invention is characterized in that a silicon element is housed in a hole of an annular insulating material so that its periphery is circumscribed, and two relay metal strips and four electrodes are provided on a part of the main surface of the insulating material. The main feature is that each relay metal electrode and a predetermined portion of the silicon element having a fine pattern are connected by solder using two comb-shaped metal foils.

以下、本発明を図面に示した一実施例により説明する。The present invention will be explained below with reference to an embodiment shown in the drawings.

( 第3図は本発明の一実施例を示しておシ、第1図と同一
′吻1目当!吻は同一符号を付けている。
(Fig. 3 shows an embodiment of the present invention, and the proboscis is the same as that in Fig. 1. The proboscis is given the same reference numeral.

第3図においで、ゲート用中継金属′電極31c、カソ
ード用中継金属心4M 31 eはセラミックの猿状絶
縁祠31aに銀臘31b、31dで接着されで、金属・
絶縁材複合体31を形成している。シリコン素子1は金
属・絶縁材複合体31の開孔内壁の対向した突出部31
f、31gK接触して位置決めされている。組立は、従
来例と同様、pHM金属箔3,4の歯部を、シリコン素
子10所定個所に半田により仮付しておいてから、アノ
ード電(愼仮6上に半田7、金94・絶縁材複合体31
、シリコン素子工と電極金属箔3.′4の仮付けしたも
の、半田32.33をセットし、ウェイトをのせて、加
熱炉を通過させた。この時、半田5,7゜32.33が
溶融するが、シリコン素子1、中継金属’成極31 c
、 31 eの相対位置は変らないため、少々、振動が
加わっても、ウェイトにより、シリコン素子1と電極金
属箔3,4の相対位置はほとんど変化しないので、各部
品は所定位置に半田付けされ、第2図(b)、 (C)
に示すような不良は生じない。
In FIG. 3, a gate relay metal electrode 31c and a cathode relay metal core 4M 31e are bonded to a ceramic monkey-shaped insulation shrine 31a with silver studs 31b and 31d.
An insulating material composite 31 is formed. The silicon element 1 is formed by opposing protrusions 31 on the inner wall of the opening of the metal/insulating material composite 31.
f, 31gK are in contact and positioned. As with the conventional example, the teeth of the pHM metal foils 3 and 4 are temporarily attached to the silicon element 10 at predetermined locations with solder. material composite 31
, Silicon element engineering and electrode metal foil 3. '4 was temporarily attached, solder 32 and 33 were set, a weight was placed on it, and it was passed through a heating furnace. At this time, the solder 5, 7° 32.33 melts, but the silicon element 1, the relay metal' polarization 31 c
, 31 e does not change, so even if a slight vibration is applied, the relative positions of the silicon element 1 and the electrode metal foils 3 and 4 will hardly change due to the weight, so each part will be soldered in a predetermined position. , Figure 2 (b), (C)
No defects such as those shown in will occur.

本実施例では第4図のように絶縁材31aの内争o、O
L+ 1    。
In this embodiment, as shown in FIG.
L+1.

壁の距離はD=15’    、シリコン素子1の外縁
の寸法はd = 15−〇・03“1 としている。こ
の場合の最大すきは0.08 mmであり、′重態金属
箔3゜4のゲート、カソード間距離P=0.2rrmで
あり、シリコン赤子1が最大にずれてもゲート、カソー
ド間距離に達することはない。一般的には第4図P>(
D   d)yAx 2        ′ にすることが好ましい。GTOの場合ゲート、カソード
短絡は致命不良となるため、後工程における異物混入の
可能性を考えると、2倍の余裕をとる必要があるからで
ある。
The distance between the walls is D = 15', and the dimension of the outer edge of the silicon element 1 is d = 15-0.03"1. In this case, the maximum gap is 0.08 mm, and The distance between the gate and the cathode is P = 0.2 rrm, and even if the silicon baby 1 is shifted to the maximum, the distance between the gate and the cathode will not be reached.Generally, the distance between the gate and the cathode is not reached.
D d)yAx 2 ' is preferable. This is because, in the case of GTO, a short circuit between the gate and the cathode is a fatal failure, so when considering the possibility of contamination by foreign matter in the subsequent process, it is necessary to provide twice as much margin.

上記のように本発明iCよれば、組立時にゲート、カン
ード用纜極金属箔の接触がおきることのない量産性のよ
い微細電極構造の半導体装置が得られる。
As described above, according to the iC of the present invention, it is possible to obtain a semiconductor device having a fine electrode structure that can be easily mass-produced without causing contact between the gate and canard metal foils during assembly.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のGTOを示しており、(a)はカンード
側からみた平面図、(b)は(a)のX−X切断線に沿
った断面図、第2図は第1図(a)のY−Y切断線に沿
った断面図で、(a)は正しい接着状況を示す図、(b
)、(C)は接着不良状況を示す図、第3図は本発明の
一実施例になるGTOを示しており、(R)はカンード
側からみた平面図、(b)は(旬のx −xvJ断線に
沿った断面図、第4図は第3図(a)のY−Y切断線に
沿った断面図である。 1・・・シリコン素子、2・・・電極膜、3.4・・・
電極金属箔、5.7,32.33・・・半田、6・・・
アノード、JJ極板、31・・・金属・絶縁材複合体、
31a・・・絶縁材、31b、31d−・・銀鑞、31
 C,31e”’第1図 ((1) <b) 第2図 (にZ) (b) C□) 第6図 (aン (b)
Figure 1 shows a conventional GTO, where (a) is a plan view seen from the canard side, (b) is a sectional view taken along the line XX in (a), and Figure 2 is the same as in Figure 1 ( Cross-sectional views taken along the Y-Y cutting line of (a), (a) shows the correct adhesion situation, (b)
), (C) are diagrams showing poor adhesion, Figure 3 shows a GTO that is an embodiment of the present invention, (R) is a plan view seen from the cand side, and (b) is 4 is a sectional view taken along the Y-Y cutting line in FIG. 3(a). 1... Silicon element, 2... Electrode film, 3.4 ...
Electrode metal foil, 5.7, 32.33...Solder, 6...
Anode, JJ electrode plate, 31... metal/insulating material composite,
31a...Insulating material, 31b, 31d-...Silver solder, 31
C, 31e"'Figure 1 ((1) <b) Figure 2 (Z) (b) C□) Figure 6 (a (b)

Claims (1)

【特許請求の範囲】 1、環状の絶縁材とその開孔内に外縁が接するように収
納された半導体素子が1個の電極板上に接着され、上記
半導体素子の上記電極板と接着されない側の主表面は微
細パターンを持ち、上記絶縁材の上記電極板と接着され
ない側の主表面に2個の中継金属電極が接着されておシ
、上記半導体素子の微細パターンの所定個所と各中継金
属電極は2個の櫛状の′電極金属箔と半田により接着さ
れていることを特徴とする半導体装置。 2、上記第1項において、半導体素子の微細パターンは
エミツタ層が平行配置されており、電極金属箔の歯状部
が接着されていることを特徴とする半導体装置。 3、上記第1項において、半導体素子は絶縁材の対向す
る両内壁に接していることを特徴とする半導体装置。
[Scope of Claims] 1. A ring-shaped insulating material and a semiconductor element housed in its opening so that its outer edge is in contact with each other are bonded onto one electrode plate, and the side of the semiconductor element that is not bonded to the electrode plate; The main surface of the insulating material has a fine pattern, and two relay metal electrodes are bonded to the main surface of the insulating material on the side that is not bonded to the electrode plate. A semiconductor device characterized in that the electrode is bonded to two comb-shaped electrode metal foils by solder. 2. The semiconductor device according to item 1 above, wherein the fine pattern of the semiconductor element has emitter layers arranged in parallel, and the toothed portions of the electrode metal foil are bonded. 3. The semiconductor device according to item 1 above, wherein the semiconductor element is in contact with both opposing inner walls of the insulating material.
JP11515582A 1982-07-01 1982-07-01 Semiconductor device Pending JPS595669A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11515582A JPS595669A (en) 1982-07-01 1982-07-01 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11515582A JPS595669A (en) 1982-07-01 1982-07-01 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS595669A true JPS595669A (en) 1984-01-12

Family

ID=14655683

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11515582A Pending JPS595669A (en) 1982-07-01 1982-07-01 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS595669A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62177190A (en) * 1986-01-30 1987-08-04 Hiroshi Ogawa Method for preventing corrosion
JPH01215988A (en) * 1988-02-24 1989-08-29 Nippon Boshoku Kogyo Kk Electrolytic protection method for duct and pipe
EP0758741A2 (en) * 1995-08-16 1997-02-19 Mercedes-Benz Ag Verifiable sheet pressure sensor

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62177190A (en) * 1986-01-30 1987-08-04 Hiroshi Ogawa Method for preventing corrosion
JPH01215988A (en) * 1988-02-24 1989-08-29 Nippon Boshoku Kogyo Kk Electrolytic protection method for duct and pipe
EP0758741A2 (en) * 1995-08-16 1997-02-19 Mercedes-Benz Ag Verifiable sheet pressure sensor
EP0758741A3 (en) * 1995-08-16 1998-02-25 Daimler-Benz Aktiengesellschaft Verifiable sheet pressure sensor
US6505521B1 (en) 1995-08-16 2003-01-14 Daimlerchrysler Ag Foil pressure sensor which can be tested

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