JPS595659A - Complementary type mis integrated circuit - Google Patents
Complementary type mis integrated circuitInfo
- Publication number
- JPS595659A JPS595659A JP57115027A JP11502782A JPS595659A JP S595659 A JPS595659 A JP S595659A JP 57115027 A JP57115027 A JP 57115027A JP 11502782 A JP11502782 A JP 11502782A JP S595659 A JPS595659 A JP S595659A
- Authority
- JP
- Japan
- Prior art keywords
- diode
- source
- potential
- integrated circuit
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000000295 complement effect Effects 0.000 title claims description 16
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims description 6
- 230000003071 parasitic effect Effects 0.000 abstract description 9
- 238000010586 diagram Methods 0.000 description 7
- NFLLKCVHYJRNRH-UHFFFAOYSA-N 8-chloro-1,3-dimethyl-7H-purine-2,6-dione 2-(diphenylmethyl)oxy-N,N-dimethylethanamine Chemical compound O=C1N(C)C(=O)N(C)C2=C1NC(Cl)=N2.C=1C=CC=CC=1C(OCCN(C)C)C1=CC=CC=C1 NFLLKCVHYJRNRH-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（Ａ） 発明の技術分野
本発明は、相補型ＭＩＳ集積回路、特に寄生ダイオード
が非所望に順方向に導通してラッチ・アップを生じる危
険性がある如き使用態様がとられる相補型ＭＩＳ集積回
路において、上記寄生ダイオードに対して予め逆バイア
ス電圧を印加せしめておくような構成を採用した相補型
ＭＩＳ集積回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION (A) Technical Field of the Invention The present invention relates to complementary MIS integrated circuits, especially those in which there is a risk of undesired forward conduction of parasitic diodes and latch-up. The present invention relates to a complementary MIS integrated circuit employing a configuration in which a reverse bias voltage is applied in advance to the parasitic diode.
（Ｂ） 技術の背景と問題点
相補型ＭＩ８集積回路においては、例えば第１図に示す
如きＮ型基板１上にＰ型ウェル２金もうけてＰチャネル
・トランジスタ３とＮチャネル・トランジスタ４とを形
成せしめる如き相補＃ Ｍ Ｉ Ｓ集積回路においては
、基板ｌを電源電圧Ｖｃｃ に接続したとするとＰ型
ウェル２はグランドに接続され、集積回路上での信号電
位は上記電源電位とグランド電位との間にあるように配
慮される。これは、第１図図示の例えば戸とＮ、ＰとＮ
、ＰとＮ＋などの形で存在する寄生ダイオードが非所望
に導通しないようにするためである。(B) Technical Background and Problems In a complementary MI8 integrated circuit, for example, a P-type well 2 is formed on an N-type substrate 1 as shown in FIG. 1, and a P-channel transistor 3 and an N-channel transistor 4 are formed. In a complementary #MIS integrated circuit such as that shown in FIG. Consideration will be given to the following. This corresponds to, for example, the door and N, and the P and N shown in Figure 1.
This is to prevent parasitic diodes existing in the form of , P and N+ from becoming undesirably conductive.
しかし、上記電位関係の条件がくずれ易い使用態様がと
られるような場合に、上記寄生ダイオードが非所望に導
通して、いわゆるランチアンプが生じることがある。However, if the above-mentioned potential relation conditions are likely to deteriorate, the parasitic diode may become undesirably conductive, resulting in a so-called launch amplifier.
（Ｃ）発明の目的と構成
本発明は、上記の点を改善することを目的としており、
上記ラッチアップの発生が上記寄生ダイオードの非所望
な導通が１つの原因になる点を考慮して、非所望の導通
を生じ難い構成を採用するようにすることを目的として
いる。そしてそのため、本発明の相補型ＭＩＳ集積回路
は、−力の導電型の半導体基板と該一方の導電型の半導
体基板に形成された他方の導電型のウェルとに夫々逆極
性のトランジスタを形成してなり、上記一方の導電型の
半導体基板と上記他方の導電型のウェルとの接合に逆バ
イアスがかかるように電源が接続された相補型ＭＩＳ集
積回路であって、少なくとも一方の極性の上記トランジ
スタのソースはダイオードを介して上記電源に接続され
ることを特徴としている。以下図面を参照しつつ説明す
る。(C) Object and structure of the invention The present invention aims to improve the above points,
In consideration of the fact that one of the causes of the latch-up is undesired conduction of the parasitic diode, it is an object of the present invention to adopt a configuration that makes it difficult for undesired conduction to occur. Therefore, in the complementary MIS integrated circuit of the present invention, transistors of opposite polarity are formed in the semiconductor substrate of the negative conductivity type and the well of the other conductivity type formed in the semiconductor substrate of the one conductivity type. a complementary MIS integrated circuit in which a power supply is connected so that a reverse bias is applied to a junction between the semiconductor substrate of one conductivity type and the well of the other conductivity type, the transistor of at least one polarity; The source of is connected to the power supply via a diode. This will be explained below with reference to the drawings.
（Ｄ） 発明の実施例
第２図は従来の相補型ＭＩ８集積回路の等価的回路図、
第３図は本発明による一実施例の相補型ＭＩ８集積回路
の等価的回路図、第４図は第３図に対応する断面構造を
示す。(D) Embodiment of the invention FIG. 2 is an equivalent circuit diagram of a conventional complementary MI8 integrated circuit.
FIG. 3 is an equivalent circuit diagram of a complementary MI8 integrated circuit according to an embodiment of the present invention, and FIG. 4 shows a cross-sectional structure corresponding to FIG. 3.
第２図において符号１．２．３．４は夫々第１図に対応
し、５ｉ：Ｐヂャネルトランジスタのソースを表わして
いる。第２図図示の回路図は、第１図図示の集積回路に
対応した回路図を示しており、一般にＰチャネル・トラ
ンジスタ３のソース５と基板１とが共に電源Ｖｃｃ に
接続される構成がとられる。In FIG. 2, numerals 1, 2, 3, and 4 correspond to those in FIG. 1, respectively, and represent the sources of the 5i:P channel transistors. The circuit diagram shown in FIG. 2 is a circuit diagram corresponding to the integrated circuit shown in FIG. It will be done.
上記ソース５と基板１との間には、図示ダイオード６の
如き寄生ダイオードが存在していて、一般には当該ダイ
メート６に対して逆バイアスが印加される電位関係が保
たれている。しかし、当該逆バイアス電圧は比較的小さ
い値であって、特殊な使用態様がとられる場合には、当
該ダイオード６が非所望に導通し、上述のラッチアップ
発生の原因となることがある。A parasitic diode such as the illustrated diode 6 is present between the source 5 and the substrate 1, and a potential relationship is generally maintained such that a reverse bias is applied to the dimate 6. However, the reverse bias voltage has a relatively small value, and in the case of special usage, the diode 6 may conduct undesirably, causing the above-mentioned latch-up.
第３図は上記の点を改善した本発明による一実施例の相
補型ＭＩ８集積回路の等価回路図を示している。図中の
符号１．２．３．４．５．６、Ｖｃｃ は第２図に対
応し、７．８は夫々ダイオードであって第１図図示の如
き集積回路上に一緒に形成されるもの、９．１０は夫々
ツェナ・ダイオードであって同じく集積回路上に一緒に
形成されるものを表わしている。FIG. 3 shows an equivalent circuit diagram of a complementary MI8 integrated circuit according to an embodiment of the present invention that improves the above points. The symbols 1, 2, 3, 4, 5, 6 and Vcc in the figure correspond to those in Figure 2, and 7 and 8 are diodes, respectively, which are formed together on the integrated circuit as shown in Figure 1. , 9.10 respectively represent Zener diodes which are also formed together on the integrated circuit.
本発明の場合、Ｐチャネル・トランジスタ３のソース５
に対して、ダイオード７が直列に挿入された形で電源電
圧Ｖｃｃ から給電される。一方、基板１に対しては
電源電圧Ｖｃｃ が直接接続される。このために、ソー
ス５の電位は基板Ｉの電位よりもダイオード７の順方向
電圧降下分だけ低い値が与えられるよう、いわば保証さ
れた形となっている。このために、上述の如く、ダイオ
ード６が非所望に導通する危険性が劣なくなる。In the case of the present invention, the source 5 of the P-channel transistor 3
In contrast, a diode 7 is inserted in series and power is supplied from the power supply voltage Vcc. On the other hand, the power supply voltage Vcc is directly connected to the substrate 1. For this reason, the potential of the source 5 is guaranteed to be lower than the potential of the substrate I by the forward voltage drop of the diode 7. For this reason, as described above, the risk of the diode 6 becoming undesirably conductive is reduced.
第３図１￥１示の構成においては、ダイオード７．８の
トランジスタ側に、グランド電位に接続され、るツェナ
・ダイオード９、ｌＯが介在するようにされている。こ
れによって、図示点（Ｐ）の電位は最大ツェナ雷、圧に
保持されることとなシ、何んらかの原因によってノイズ
が混入して、ソース５の電圧が非所望に上列しようとす
る如き事態が生じても、ツェナ・ダイオード９、ｌＯに
よって電位の上昇が抑止される。なお、第３図に於ける
ダイオード７は第４図の断面図に示す構造で形成すれば
良い。また、上記実施例ではＰチャネルトランジスタ３
のソースとＶｃｃ 間にダイオードを接続しているが
Ｎチャネルトランジスタ４０ンースと接地との間に接続
しても良い。In the configuration shown in FIG. 3, a Zener diode 9, 1O connected to the ground potential is interposed on the transistor side of the diode 7.8. As a result, the potential at the point (P) shown in the figure is maintained at the maximum Zener voltage, and the voltage at the source 5 may undesirably rise due to noise being mixed in for some reason. Even if such a situation occurs, the potential rise is suppressed by the Zener diodes 9 and 1O. Note that the diode 7 in FIG. 3 may be formed with the structure shown in the cross-sectional view of FIG. 4. Further, in the above embodiment, the P channel transistor 3
Although a diode is connected between the source of the N-channel transistor 40 and Vcc, it may also be connected between the N-channel transistor 40 and ground.
（約 発明の詳細
な説明した如く、本発明によれば、寄生ダイオードが非
所望に順方向に導）ｍする危険性が抑圧され、非所望な
ラッチアップを生じることが防止される。DETAILED DESCRIPTION OF THE INVENTION As described above, the present invention reduces the risk of undesired forward conduction of parasitic diodes and prevents undesired latch-up.
第１図は相補型ＭＩＳ集積回路の一例の断面構造、第２
図は従来の相補型Ｍ Ｉ ８集積回路の等価的回路図、
第３図は本発明による一実施例の相補型ＭＩＳ集積回路
の等価的回路図、第４図は第３図に示す回路に対応する
断面図を示す。
図中、ｌは基板、２はＰ型ウェル、３はＰチャネル・ト
ランジスタ、４はＮチャネル・トランジスタ、５はソー
ス、６は寄生ダイオード、７．８はダイオード、９．１
０はツェナ・ダイオードを表わしている。
特許出願人 富士通株式会社Figure 1 shows the cross-sectional structure of an example of a complementary MIS integrated circuit, and Figure 2 shows the cross-sectional structure of an example of a complementary MIS integrated circuit.
The figure shows an equivalent circuit diagram of a conventional complementary MI8 integrated circuit.
FIG. 3 is an equivalent circuit diagram of a complementary MIS integrated circuit according to an embodiment of the present invention, and FIG. 4 is a sectional view corresponding to the circuit shown in FIG. 3. In the figure, l is the substrate, 2 is a P-type well, 3 is a P-channel transistor, 4 is an N-channel transistor, 5 is a source, 6 is a parasitic diode, 7.8 is a diode, 9.1
0 represents a Zener diode. Patent applicant Fujitsu Limited
Claims (1)
板に形成された他方の導電型のウェルとに夫々逆極性の
トランジスタを形成してなり、上記一方の導電型の半導
体基板と上記他方の導電型のウェルとの接合に逆バイア
スがかがるように電源が接続された相補型ＭＩＳ集積回
路であって、少々くとも一方の極性の上記トランジスタ
のソースはダイオードを介して上記電源に接続されるこ
とを特徴とする相補型ＭＩＳ集積回路。Transistors of opposite polarity are formed in a semiconductor substrate of one conductivity type and a well of the other conductivity type formed in the semiconductor substrate of one conductivity type, and the semiconductor substrate of the one conductivity type and the well of the other conductivity type are respectively formed. This is a complementary MIS integrated circuit in which a power supply is connected so that a reverse bias is applied to the junction with a well of a conductivity type, and the source of the transistor of at least one polarity is connected to the power supply through a diode. A complementary MIS integrated circuit characterized by being connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57115027A JPS595659A (en) | 1982-07-02 | 1982-07-02 | Complementary type mis integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57115027A JPS595659A (en) | 1982-07-02 | 1982-07-02 | Complementary type mis integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS595659A true JPS595659A (en) | 1984-01-12 |
Family
ID=14652404
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57115027A Pending JPS595659A (en) | 1982-07-02 | 1982-07-02 | Complementary type mis integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS595659A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0660520A2 (en) * | 1993-11-30 | 1995-06-28 | Siliconix Incorporated | A bidirectional current blocking mosfet for battery disconnect switching including protection against reverse connected battery charger |
| US5747891A (en) * | 1993-11-30 | 1998-05-05 | Siliconix Incorporated | Method of blocking bidirectional flow of current |
-
1982
- 1982-07-02 JP JP57115027A patent/JPS595659A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0660520A2 (en) * | 1993-11-30 | 1995-06-28 | Siliconix Incorporated | A bidirectional current blocking mosfet for battery disconnect switching including protection against reverse connected battery charger |
| EP0660520A3 (en) * | 1993-11-30 | 1996-11-27 | Siliconix Inc | A bidirectional current blocking mosfet for battery disconnect switching including protection against reverse connected battery charger. |
| US5682050A (en) * | 1993-11-30 | 1997-10-28 | Siliconix Incorporated | Bidirectional current blocking MOSFET for battery disconnect switching including protection against reverse connected battery charger |
| US5747891A (en) * | 1993-11-30 | 1998-05-05 | Siliconix Incorporated | Method of blocking bidirectional flow of current |
| US6087740A (en) * | 1993-11-30 | 2000-07-11 | Siliconix Incorporated | Portable computer containing bidirectional current blocking MOSFET for battery disconnect switching |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5767733A (en) | Biasing circuit for reducing body effect in a bi-directional field effect transistor | |
| US4837460A (en) | Complementary MOS circuit having decreased parasitic capacitance | |
| JP2566064B2 (en) | I / O buffer circuit | |
| JPH0157533B2 (en) | ||
| EP0621693B1 (en) | BiCMOS output driver circuit | |
| US5923212A (en) | Bias generator for a low current divider | |
| JPS595659A (en) | Complementary type mis integrated circuit | |
| US6642120B2 (en) | Semiconductor circuit | |
| JPS60247959A (en) | Latch-up preventive circuit | |
| US5463240A (en) | CMIS device with increased gain | |
| US5276362A (en) | BiCMOS TTL to CMOS level translator | |
| JP3386661B2 (en) | Output buffer | |
| JP3610683B2 (en) | Analog switch circuit | |
| JP2557534B2 (en) | Semiconductor integrated circuit device | |
| JPH1028045A (en) | Mos transistor circuit | |
| JPS6232722A (en) | Push-pull output circuit | |
| JP2917693B2 (en) | Semiconductor integrated circuit | |
| JP2979716B2 (en) | CMOS integrated circuit | |
| JPH0257345B2 (en) | ||
| KR100248341B1 (en) | Array method of cmos | |
| JPH0225237Y2 (en) | ||
| KR100280437B1 (en) | Structure for cmos transistor | |
| JPH0329325B2 (en) | ||
| JPS63244671A (en) | Semiconductor device | |
| JPH11307786A (en) | Semiconductor diode |