JPH0225237Y2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a complementary semiconductor device (hereinafter referred to as
CMOS (CMOS) is particularly used in integrated circuits and provides a structure with high current capability.

Since CMOS has two opposite types of transistors on the same substrate, it results in a parasitic PNPN structure. As a result, this device has the possibility of causing a latch-up phenomenon. Generally, this latch-up phenomenon is classified into three types: (1) power supply latch caused by noise on the power supply line, (2) input latch on the input line, and (3) output latch on the output line. In general, for (1), it is possible to increase the withstand voltage by using a power supply diode, and for (2), by devising the arrangement and setting of the input protection resistor, it is possible to increase the withstand capability even with conventional technology. However, regarding (3), the reality is that the withstand capability can be increased by providing a sufficient distance between each transistor.

The present invention aims to improve these drawbacks.

The feature of the present invention is that in a complementary semiconductor device in which a MOS type P-channel transistor and an N-channel transistor are formed on the same semiconductor substrate, the transistor has a P ^- layer, a P ⁺ layer, and an N ^- layer.
It is found in a semiconductor device formed of an N ⁺ layer.

A detailed explanation will be given below using a CMOS inverter circuit as an example. FIG. 1 is a cross-sectional view of a conventional device, and FIG. 2 is a cross-sectional view of a device according to the present invention. output voltage
V _OUT > V _DD , V _OUT with respect to the power supply voltages V _{DD ,} V _SS
<V Shows the carrier flow when _SS is reached. (In the figure, the solid line is the flow of holes, and the wavy line is the flow of electrons)
When V _OUT >V _DD , the drain 6 of the P channel transistor has a positive potential with respect to the substrate, so this junction becomes forward biased and holes are injected from the P region 6 into the substrate 10. A portion of the holes flow into the P region 1 through the P ⁻ well 9 . This flow of holes in the P ^- well 9 passes through the resistor R _P and the junction N ⁺ 2P ^- well 9 becomes forward biased, so that electrons are injected into the P ^- well. Part of it passes through the P ^- well and P ⁺
It flows into 6. This promotes hole injection at the junction between P ⁺ 6 and N substrate 10 . By repeating the above process, the drain 6 of the P channel, the substrate 10,
The PNPN thyristor consisting of the P ^- well 9 and the source 2 of the N-channel transistor is turned on. When the PNPN thyristor turns on, the P well 9;
The junction consisting of substrate 10 is forward biased to V _DD −
The PNPN thyristor between V _SS may also turn on, leading to destruction. Similarly, latch-up occurs when V _OUT <V _SS . Therefore, in order to increase the output latch withstand capability, an effective means is to reduce the effective amount of holes and electrons that are injected as the trigger current that turns on the thyristor.

The purpose of the present invention is to improve upon such prior art and to increase the latch-up withstand current. That is, the purpose is to devise a path for the charge that causes latch-up, and to increase the withstand capability by reducing the amount of charge injected from each junction.

The new structure shown in FIG. 2 will be explained below while comparing it with the conventional structure shown in FIG. The structure of the drain 6 of the P channel transistor is formed from P ⁺ 6 and P ^- 12, and their arrangement is opposite to the N channel transistor.
Form P ^- 12. Furthermore, in an N-channel transistor, its drain is N ⁺ 2 and N ^- 1
1, and the arrangement is such that N ^- 11 is formed opposite the P channel transistor.

In other words, the amount of charge that becomes the trigger current of the PNPN thyristor has been structurally reduced.

As is clear from the above explanation, the present invention
This relates to the structure of CMOS integrated circuits, which are effective as devices with increased withstand current compared to conventional ones.

[Brief explanation of the drawing]

FIG. 1 and FIG. 2 are cross sections of a CMOS inverter circuit having a conventional structure and an embodiment of the present invention, respectively. In the figure, 1...N channel transistor source side P ⁺ channel stopper, 2
...Source of N-channel transistor N ⁺ , 3
...Drain N ⁺ of N-channel transistor,
4...Drain side of N-channel transistor
P ⁺ channel stopper, 5...Drain side of P channel transistor N ⁺ channel stopper, 6...Drain P ⁺ of P channel transistor, 7...Source P ⁺ of P channel transistor, 8...Drain side of P channel transistor Source side N ⁺ , 9...P ^- L, 10...N substrate, 11
...Source of N-channel transistor N ^- , 1
2...Drain P ^- of P channel transistor,
It is.

Claims (1)

[Scope of utility model registration request] A semiconductor substrate of one conductivity type has a well region of another conductivity type, a one-channel MOS transistor is formed in the semiconductor substrate and has a source and drain region of the other conductivity type, and the semiconductor substrate has a well region of another conductivity type. A different channel type MOS transistor having source and drain regions of one conductivity type is formed in the region, and one of the source and drain regions of the one channel type MOS transistor is formed with the other channel type MOS transistor.
A region of the other conductivity type, lower in impurity concentration than the source and drain regions, and deeper than the source and drain regions is provided in contact with the side facing the other channel type MOS transistor; said one channel type of one of the source and drain regions;
1. A semiconductor device, further comprising a region of one conductivity type, lower in impurity concentration than the source and drain regions, and deeper than the source and drain regions, in contact with a side facing a MOS transistor.