JPS63244671A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the generation of latchup, by arranging, between a well and a semiconductor substrate, a high concentration layer whose conductivity type is identical with that of the semiconductor substrate, and whose impurity concentration is higher than that of the semiconductor substrate. CONSTITUTION:Between the region of a P-type semiconductor substrate 1 and an N-well 2, a high concentration P<+> layer 11 is formed, whose impulity concentration is higher than that of the P-type semiconductor substrate 1. A depletion layer between the N-well 2 and the P<+> layer 11 is narrower as compared with the case where the high concentration P<+> layer 11 does not exisit. Accordingly, a P-N junction capacity also becomes larger in the case where the P<+> layer 11 is formed. By the effect of its capacitive coupling, a sharp and large change of electric potential in the N-well 2 and the substrate 1 can be restrained, so that latchup is hard to generate.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to semiconductor devices, particularly CMO devices having a well structure.
This relates to S semiconductor devices.

[Conventional technology]

FIG. 2 is a cross-sectional view showing a conventional CMOS inverter together with a parasitic bipolar transistor that causes latch-up. In the figure, 1 is a P-type semiconductor substrate;
2 is N-well, 3 is N-channel MOSFET, 4 is P
This is a channel MO3FET, and the P-type semiconductor substrate 1 is grounded through a P-type diffusion layer 5, and the N-well 2 is connected to a power supply VCC through an N-type diffusion layer 6. ■I is the input of the inverter, v out is the output of the inverter, 7.8 is the parasitic bipolar transistor, 9a.

9b is the electrical resistance of the P-type semiconductor substrate 1, and 10 is the electrical resistance of the N-well 2. Here P channel MO5FET4
The source is connected to the power supply VCC, and the drain is N-channel MOS.
At the drain of FET3, there is also an N-channel MOS F
The source of ET 3 is connected to ground potential, and they constitute a CMOS inverter.

In such a CMOS inverter, the input signal
It is applied to the gate of O3FET3.4, and a signal having the opposite phase to V114 is output as V011T.

[Problem that the invention seeks to solve]

In a semiconductor device with such a 0MO3 configuration, as shown in Figure 2, a si-risk circuit is formed by a parasitic bipolar transistor, and a large current flows from the power supply VCC to the ground level due to noise current, which is a so-called latch. Up phenomenon may occur. In particular, as the degree of integration increases, the distance between the elements constituting the device becomes smaller and the depth of the well becomes shallower, so the base width of the parasitic bipolar transistor 7.8 in FIG. 2 becomes smaller. Lunch-ups are becoming more and more likely to occur.

To begin with, latch-up begins to occur when the potential of the well or semiconductor substrate changes due to external noise and the parasitic bipolar transistor turns on. Explaining FIG. 2, for example, when the potential of the N-well 2 decreases due to noise from vout, and the voltage between the base and emitter of the parasitic bipolar transistor 8 increases, this transistor 8 turns on, and the transistor 8 is turned on from the power supply vec. Holes flow into the P-type semiconductor substrate 1 through the substrate, the potential of the substrate 1 increases, and the base of the parasitic bipolar transistor 7 increases.
When the emitter voltage increases, this transistor 7 is turned on, and electrons are transferred from the ground level to the transistor 7.
It flows into N-well 2 through , further lowering the potential of N-well 2, causing positive feedback.
A large current flows from the power supply vec to ground.

The present invention was made to solve the above-mentioned problems, and aims to obtain a CMO3 semiconductor device in which latch-up phenomenon is less likely to occur.

[Means for solving problems]

The semiconductor device according to the present invention focuses on the fact that latch-up can be prevented by realizing a device structure in which the potential of the well or the substrate is less likely to fluctuate. This is the same as the substrate, but a high concentration layer with a higher impurity concentration than the substrate is provided.

[Effect]

In the present invention, since a high concentration layer having the same conductivity type as the substrate and higher impurity concentration than the substrate is provided between the well and the substrate, the capacitance between the well and the substrate is increased, and the capacitance between the well and the substrate is increased. Steep and large potential fluctuations can be suppressed,
Furthermore, even if the potential of the well or the substrate fluctuates greatly, the parasitic thyristor circuit does not go into a low resistance state, and latch-up can be prevented from occurring.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a CMOS inverter according to an embodiment of the present invention, in which numerals 1 to 6 are the same as in FIG. 2,
Reference numeral 11 denotes a highly doped P layer formed between the P type semiconductor substrate region and the N-well 2 and having a higher impurity concentration than the P type semiconductor substrate l.

In a CMOS inverter with such a configuration, the high-concentration 29 layer 11 is connected to the N-well 2 and the P-type semiconductor substrate has a narrow area. The ring can suppress steep and large potential fluctuations in N-well 2 and substrate 1, which makes latch-up less likely to occur.Also, if the potential of either N-well 2 or substrate 1 changes for some reason, Even if it fluctuates greatly and the other one also fluctuates due to the capacitive coupling, the manner of fluctuation in this case is such that latch-up is unlikely to occur.

That is, to explain using the parasitic bipolar circuit shown in FIG. 2, it is assumed that the potential of the semiconductor substrate 1 increases significantly and the parasitic bipolar transistor 7 is turned on. At that time, since the coupling capacitance between the N-well 2 and the substrate l is large, the potential of the N-well 2 also increases greatly, but at this time, a large reverse bias is applied between the base and emitter of the parasitic bipolar transistor 8. Something happened, ONL,
In this way, latch-up does not occur unless parasitic bias transistors 7 and 8 are ON, so latch-up does not occur in this state, and the potential of N-well 2 fluctuates greatly. Similarly, latch-up will not occur in this case.

In the above embodiment, a case was shown in which an N-well was formed on a P-type semiconductor substrate, but a P-well may also be formed on an N-type substrate, and the same effect can be obtained in this case as well.

〔Effect of the invention〕

As described above, according to the present invention, a highly concentrated layer having the same conductivity type as the semiconductor substrate and a higher impurity concentration than the semiconductor substrate is provided between the well and the semiconductor substrate, so that latch-up is less likely to occur in the semiconductor device. can be obtained.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the structure of a CMOS inverter according to an embodiment of the present invention, and FIG. 2 is a diagram showing the structure of a conventional CMOS inverter and a parasitic iris circuit. ■...P-type semiconductor substrate, 2...N-well, 3...
・N-channel MO3FET, 4...P-channel MO3
FET, 5...P° diffusion layer, 6...N+ diffusion layer, 1
1...21 layers of high concentration. Note that the same reference numerals in the figures indicate the same or equivalent parts. Figure 1 1t: JJ skin P'i Figure 2

Claims (1)

[Claims] (1) MOS transistors of different conductivity types having second and first conductivity type source/drain diffusion layers are formed on the surface of a first conductivity type semiconductor substrate and a second conductivity type region formed on the substrate surface, respectively. A semiconductor device, characterized in that a first conductivity type semiconductor layer having a higher impurity concentration than the substrate is provided between the first and second conductivity type regions of the substrate.