JPS5955538A - Controller of electronic equipment - Google Patents

Abstract

PURPOSE:To simplify the constitution of a memory, by providing an address means consisting of an adder circuit and a latch circuit and a selection means consisting of plural gate circuits, to read out and process the data after setting it to a program region. CONSTITUTION:When a data storing instruction is supplied, a control signal generating part CONT delivers a pseudo instruction signal. Then an AND3 is turned on and an FF1 is set to deliver an ''NOP'' signal. The address data of an Rg3 existing on an address line is stored in an RAM through a Gg2 which is turned on by the output GOST of an NOR1 and via half adders HA2 and an Rg10. When a Gg5 is turned on by the output of an AND7, the data of 4 bits given from the Rg3 is fed to the RAM through a bus line. Here an R/W signal is delivered from the CONT to write the 4-bit data to an address designated by an address input ADD. Thereafter, the writing is successively carried out in the same way.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device for command control of an electronic musical instrument, etc.
In particular, the present invention relates to a control device having a function of reading and processing data set in a program area in a netast addressing type processor in which the address of the next instruction to be executed is included in the instruction.

BACKGROUND ART Conventionally, in an instruction control method using a program counter, which is used in a microprocessor, data is stored in a program area and the data is read on the program. However, in instruction control by a processor using the netast address method, there is still no way to read data in the program area as described above, so when a large amount of data is required, it is necessary to use a separate It was necessary to set a read-only memory ROM. The present invention improves the above-mentioned drawbacks by making it possible to set data in the program area, read it, and process it in a netast address system processor. It is an object of the present invention to provide a control device for electronic equipment using a processor using a flexible netast address method that can be easily configured.

The present invention is a control device using a processor using a netast address system, which includes an instruction to switch to a read mode in order to read data in a program area, and furthermore, after executing this instruction, the internal operation enters a no-operation state and starts the next program. This allows the data to be automatically divided, read, and processed. At this time,
There is no operation code, that is, an instruction in a pseudo-instruction, and Pino I~, which is an operation code, can also be treated as data. Also, the next address in a pseudo-instruction operates as the actual next address,
After the data has been read, execution of the order of the trial court is returned to the address indicated by the netast address.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows a block diagram of an embodiment of the present invention. A musical tone generating section 1 that generates digital data of musical tones of an electronic musical instrument is composed of a musical tone generating section 2 and a control section 3, for example, a one-chip L.
This is an S1 circuit. The musical tone generation section 2 generates musical tone digital data B3 based on the control signal C1 obtained from the control section 3 and the data obtained via the bidirectional data bus D1, and uses digital/analog (D/A) data (not shown). Output to converter. The bidirectional data bus also inputs data such as status from the tone generator to the controller 3.

Digital input data B2 is input to the control section 3 from the outside of the musical tone generating section 1, and digital output data B+ is further output. This input/output digital B2. For example, the state of the key of Shigeko's musical instrument is detected by Bl. The control device for electronic equipment of the present invention is used for the control unit 3 in FIG.

FIGS. 2(a) to ffl are detailed circuit diagrams of the control section 3 in FIG. 1. The read-only memory ROM (not shown) and the circuit diagram in FIG. 2 correspond to the control section 3 in FIG. 1. Input data B2 is input to the control unit via the input terminal INF, and output data B1 is input via the output terminal OUT.
outputs. The musical tone generator 2 corresponds to the tone generator TG in FIG. 2, and the bidirectional data bus D corresponds to the buffer B.
It is connected to the internal pass line BUS via UF. Figure 2 (Figure 2 is on the left of bl (Figure 2 (C) is on the right of al)
is arranged, and Fig. 2 (fd) is placed on the left of Fig. 2 (e), and Fig. 2 (fl) is placed on the right. Fig. 2 (al, (bl)
, (On the underside of the cl.
l, (f) are placed.

The data output of the read-only memory ROM (not shown) is as follows.
FIG. 2 (Latch circuit groups Rg1 to Rg
Enter a. The latch circuit groups Rg+ to Rg4 are controlled by clocks φRAN1 to φQO4, respectively, and data output from the read-only memory ROM is stored in the latch circuit groups Rg+ to Rga at the timing of these clocks.

In the embodiment of the present invention, the clock φ2゜l~φ)+
oa is output simultaneously as an AND output of clock 1+ and clock φ2 (at the beginning of each instruction) (Figure 4 (C))
. The latch circuit group Rg1 latches the lower six bits of output data of the read-only memory ROM, and stores instructions to be operated, that is, operation codes. Its output is shown in Figure 2 (AND gate ANI of bl)
It is input to the operation decoder OPD in the same figure via ++ to AND+6. AND GATE AND++~AND
Other inputs added to +6 will be described later, but they are at a high level during normal command operations. This operating gin decoder OPD crawl/edge circuit group Rg+ (second
The operation code sent from the read-only memory ROM is decoded through the control signal generating section CONT (FIG. 2B). The control signal generator C0NT receives the operation signal sent from the operation decoder OPD,
Each clock signal φ1. φ2 and t1 to t4 (Figure 4)
are input, and control signals for each part are generated according to those signals.

Launch circuit group Rg2. Rg3 (FIG. 2(a)) is for launching the 7th bit to the 18th bit from the bottom of the output data of the read-only memory ROM. Then, the operand corresponding to the latched operation code is stored in the launch circuit group RgI. For example, when the operation code stored in launch circuit group Rg1 is addition, etc., launch circuit group Rg2. Each address of the random access memory RAM is stored in Rg3, and in the case of a page jump, the next page address is stored in the latch circuit group Rg3.

Launch circuit group Rg 3. The outputs of Rg2 are respectively connected to the gate group Gg2. Gg3 (FIG. 2(b)), and the gate group Gg2. The outputs of Gg3 are combined into one system and sent to random access memory R M (Figure 2 (C))
The 6-bit address is input manually to the ADD. Gate group Gg2. Gga are Noah Gate NOR+ and N, respectively.
0R2 (FIG. 2(b)), and the gate groups Gg2 and Gg3 are respectively selected by having their outputs set to high level at different timings. A control line from a control signal generator C0NT is connected to the inputs of the NOR gates NOR+ and NOR2.

Now, in the case of an instruction such as the above-mentioned addition, the operation code of the instruction is decoded by the operation decoder OPD and inputted to the control signal generation section C0NT, so that the control signal generation section C0NT is converted to a NOR gate NOR+.

The NOR inputs are turned on at different timings to select gate group Gg2.0g3. As a result, latch circuit group Rg3. The contents of Rg2 (FIG. 2(a)) are selected respectively, and the contents of the random access memory RAM (
The addresses shown in FIG. 2(C)) are designated respectively. The contents of the specified random access memory RAM are output to the output terminal. Output from IJT, clock φ1. The latch circuit group Rg5. Rg6 (Figure 2 (C))
is stored in Detailed timings for each will be described later when explaining FIG. 4, but naturally, gate group Gg2. Gg
3 (FIG. 2(b)) is selected, that is, the timing of address designation of the random access memory RAM and the output of the random access memory RAM.Latch circuit group Rg5. Rg6
This is synchronized with the timing of selective launch (FIG. 2(C)). Figure 2 (In C1, the data input to each of the latch circuit groups Rg5 and Rg6 is further input to the inputs Δ1 to A8 and the input BI=Be of the arithmetic circuit ALU.The data input to the arithmetic circuit ALU is the control signal The operation specified by the operation code is performed by the operation control signal generated by the generation unit C0NT, and is output to the output terminals St, S2.S4.Ss and the carry output terminal C3LIT.The 4-bit output terminal S
l, S2, 34. Se is connected to the pass line BUS, and is output to the terminal specified by the operation code. For example, in the case of an addition instruction, the instruction is stored in the memory corresponding to the address of the random access memory RAM specified by the latch circuit group Rg2 (FIG. 2(a)).

The launch circuit group Rga (FIG. 2(C)) launches the top 6 bits of the output data of the read-only memory ROM, and stores the address of the next instruction to be executed, that is, the next address NA. Launch circuit group Rg
The output of No. 4 is inputted via the half adder HA+ and the gate group Gga to the launch circuit group Rg7 (FIG. 2(d)) for determining the address within the page of the next read-only memory ROM. In addition, launch circuit group Rg3 (Fig. 2 (a))
The output is sent to the latch circuit group Rge for determining the page address of the next read-only memory ROM via the gate group Gga.
(The input is shown in Fig. 2 (mountain). The latch circuit Rg7 latches the clock φAo+-+Rg8 at the timing of φADH. Now, assuming that a page break is not performed, first, the output is output from the control signal generator C0NT. The address selection signal As that is selected becomes low level, and the signal is passed through the inverter 12 to the gate group Gga (FIG. 2(d)).
Turn on.

As a result, the netast address NA of the latch circuit group Rga is transferred to the latch circuit group Rg via the half adder HA+.
7 at the timing of clock φADL. At this time, since a page break is not performed, the clock φADH is not generated, and no storage is performed in the launch circuit group Rgθ. As a result, of the 12 bits for determining the address of the read-only memory ROM, the lower 6 bits are assigned to the launch circuit group R.
This is the address stored in gn (= content of Rg7),
Specifies the in-page address of the next instruction in the read-only memory ROM. At this time, the page address of the upper 6 bits for address determination is not changed and a page break is not performed. When a page break is to be performed next, the output of inverter I2 becomes high level and gate group Gga is turned on.
Furthermore, by simultaneously generating clocks φADL and φAoH, in addition to the above operations, data specifying the next page due to a page break in latch circuit group Rg3 is transferred to launch circuit group R.
ge, thereby making the read-only memory RO
Of the 12 bits for determining the address of M, the upper 6 bits become the address stored in the launch circuit group Rg3 and specify the page address of the next instruction in the read-only memory ROM, and the lower 6 bits specify the next instruction by the above operation. The in-page address of the instruction is specified, and the page break specification and netast address NA are specified at the same time.

NOR gate NOR3, latch circuits R1, R2 (Fig. 2 (
C1), AND gate AND+7°AND+e (FIG. 2(f)), OR gate OR2, and half adder HA+ (FIG. 2(d)) determine the next instruction to be executed based on the result of the arithmetic circuit ALU in FIG. 2(C). This is a circuit that determines and executes whether or not to advance the address, that is, the netast address NA by one address (increase it to +1). In other words, it is a circuit that generates an operation to skip the address of the next instruction depending on conditions. Now, by executing the addition and comparison instruction, the arithmetic circuit AL
4-bit output of U 31. S2. When Sa and Sθ are all O, the output of NOR3 becomes high level and is taken into the latch circuit R1 at the clock φS (the timing is not particularly shown). Furthermore, the captured data is sent to the half adder HA via the AND gate AND+e (Figure 2 (f)) and the OR game FOR2 (Figure 2 (d)).
1 Enter the carry person number 01N (Fig. 2(d)). At this time, since the next address NA has already been input to the half adder HA+ from the latch circuit group Rga (Fig. 2 (a)), the netast address NA is incremented by 1 by the output of the OR gate OR2, and the next clock φAD
Inputs the next address of the next instruction in the read-only memory ROM to the launch circuit group Rgv at the timing of N.
Access as A+l.

The same is true when a carry is output from the arithmetic circuit ALU in FIG. AND gate AND+7 (Figure 2 (f))
Through the OR gate ORt (FIG. 2(d)), it is input to the carry numbers c and N of the half adder HA+, and the next address NA is incremented by 1. The operation of incrementing the netast address NA by 1 is performed by the four pinpoint outputs Sl, S2 . Sa.

Do this when S8 is all O, or carry output co, J
Whether to perform this when T occurs is determined by the AND gates AND+ of the control signal generator C0NT (FIG. 2(b)) to FIG. 2(f).7. Selected by the signal input to AND+e. If the netast address NA is incremented by 1 as a result of the above operation, the next instruction to be executed is the next address from which the netast address NA (the address next to the address of the current instruction is skipped) by one address. Becomes the property of In addition, in this embodiment, the value to the net store address N was set to 4-1 depending on whether the result of the addition operation was all 0 or if a carry occurred, but the operation decoder in Fig. 2 fbl OPD,
and a control signal generator C0NT.

NOR gate NOR3, launch circuit R1, R2 (Fig. 2 (
C1), Antogame-LAND I 7. AND Ig
(trl in FIG. 2) and the configuration of the or game FOR2, etc., it is possible to easily change and set the skip condition of the netast address NA to one based on a specific command condition. Furthermore, by slightly changing the input to Half Adder 11AI, the number of skips can be increased not only by +1 but by +2.
．． It is also possible to easily change the value to +3, etc.

AND gate AND+9~AND23. OR GATE OR
2 operates when the next execution is skipped at 1 to 4 addresses by a signal input to the skip terminal SKT from an external circuit. The number of skips in this operation is the skip control signal 5r generated from the control signal generator C0NT.
-3a, and changes depending on the data input to the skip terminal SKT. For example, skip control signal 3
When 1 is set to high level and 32 to S4 are set to low level, if the data input to the skip terminals 5KT2 and 5KT3 are both high level, 3 addresses are skipped. Further, when the skip terminal 5KT2 is at a high level and the skip terminal 5KT3 is at a low level, 2 addresses are skipped, and when both are input at a low level, there is no skipping.

In the case of an electronic musical instrument, the input terminal INF is a terminal for inputting signals such as a function switch that specifies the keyboard, tone, rhythm, etc., and is stored in the launch circuit group Rgq by clocks φ, 4°φp5 (timings are not particularly shown). be done. Naturally, their storage operation and launch circuit group Rg
The data output operation from 9 is performed by the control signal generator C.
Controlled by control signals from 0NT. The input data output from the launch circuit group Rg9 is subjected to various determinations and processing via the pass line BUS according to a program stored in the read-only memory.

It is connected to the lotus line BUS, and its output is the output terminal OU.
The output of the launch circuit group Rg++ connected to T is sent to the launch circuit group Rg7.T via another gate B\Gg+o. R
Enter in ge. (A in Fig. 2(e) is shown in Fig. 2(e).
Connected to A of dl. ) This is a case where execution moves to the address specified by the data output to the output terminal. At this time, since the address selection signal As generated by the control I-roll signal generating section C0NT becomes high level, the gate group Gg+o is turned on, and furthermore, the inverter I2
Day 1 to group Gg4 are turned off via . As a result, the netast address signal NA and page break signal input to the data 1 to group Gga are blocked, and the launch circuit group Rg+
+ output is gate group Gg+.

selected by For example, when a subroutine makes a quick turn, the address to be returned to is read from random access memory and the output command is used to clock φ
, 1. φ, 2. The addresses are sequentially stored in the latch circuit group Rg++ at timings φ, 3 (timings not particularly shown), and the addresses stored in the launch circuit group Rgl+ are stored in the latch circuit group Rg7. It is taken into Rge and used as the read-only memory ROM address for the next instruction. The above operations are naturally executed by a program stored in the read-only memory ROM.

Figure 2 (111 gate group Gg++ and Figure 2 ffl
AND gates AND24 to AND33. or gate O
R3 to OR6, flip-flops FF2 to FFa, decoder DOC, and latch circuits R3 to R5 operate when an execution address is determined by program data input from the outside. For example, it operates when an instruction to move the next execution to an address specified from the outside is input from the read-only memory ROM. When the above-mentioned command is input to the control signal generator C0NT (FIG. 2(b)), an input waiting command signal IWA is output from there, and the input wait command signal IWA is outputted from the flip-flop FFa via the AND gate AND32.
(Fig. 2(f)). Since the AND output of the clock t6 and the clock φ1 is input to the AND gate AND32, the setting at this time is performed in synchronization with this signal. When the flip-flop FFa is sent, its output Q becomes high level, turning on the gate group Gg++, and further passing through the inverter 4 to the AND gate AND+.
+ to AND+6 (FIG. 2(b)) is turned off. Also,
Gate group Gg+ with lightning on (Figure 2 (a))
Since this signal is input through inverter (1), it is turned off. That is, the control signal generator C0N
The input wait signal IWA is output from T (FIG. 2(b)), and the flip-flop FF4 (FIG. 2(f)) is set, so that the launch circuit groups Rg1 to Rg4
(Fig. 2(a)), the output of the read-only memory ROM is no longer input, and the external program terminal EPT (second
The data input from (d) in the figure is input sequentially (clock φ).

1 to φRO4). At this time, the control signal generator C0NT requests programming from an external circuit (not shown). In response to this signal, 24 bits of program data are input from the external circuit via the external program terminal EPT in 6 bits every 4 clock times. At this time, a signal indicating the 6-bit program data is input from the terminal ADI, and a clock signal is input from the terminal CC. (Fig. 2(f)) These signals are sent to launch circuits R3 to R5 by clock φ1.
(FIG. 2(f)) and passes through the decoder DOC to the latch circuit group Rg1 to Rga of FIG. 2F8.
Clocks φ1101 to φ1jQ4 for performing 7 checks are output from AND gates AND2a to AND27. As a result, the program data manually input to the external program terminal EPT (FIG. 2(d)) is transferred to the specified launch circuit group Rg+-Rga at the timing of clocks φ2o+ to φ11LQ4 by 6 bits. As a result, a program for one address is manually inputted in four clocks, and a completion signal is input to the input completion terminal. Then, the signal is set to flip-flow knob FF3 (Fig. 2 (f)),
The flip-flop knob FF4 is activated by the output of the flip-flop FF3. This reset operation executes the program at the input address. In addition, in FIG. 2 (fl, flip-flop FF2.inno-ri I5°OR gate OR3~OR6, AND gate AND2~AND3+, black tsuku φRL) l~
φI! This is a circuit for generating 04 from the signals inputted from the terminal DI and the terminal CC in synchronization with the clock φ2.

In FIG. 2(C), the tone generator control signal output from the lotus line BUS and the control signal generator C0NT is connected to a tone generator TG (not shown).

In FIG. 2(b), OR gate OR+, AND gate AND+~AND? , half adder HA2° launch circuit group Rg+o, inverter 13. Gate groups Gg5 to Gg8 in FIG. 2(a) operate when the contents of the read-only memory ROM are used as data. FIGS. 3 and 4 are time charts of each signal related to this operation.

FIG. 3 shows an execution cycle which is a unit when executing a transfer command. FIG. 3 (al and fb) shows the main clock φ2. φ1, and all control operations are performed in synchronization with these clocks. In FIGS. 3(e) to (11), each clock t+"ta and a pair of main clocks φ2 and φ1 form one clock, and the period from clock t1 to clock t4 represents one execution cycle. The clock φp-oI (
~φλoa) is the clock t1 in this embodiment
It is obtained as an AND output of main clock φ2 and indicates the start of each execution cycle. In addition, these clocks transmit each program data to launch circuit groups Rg+ to Rg.
It is also a launch signal for storing program data in the read-only memory ROM (FIG. 2(a)).
lot~φ1LO4 have the same clock. Third
Figure (d+ is launch circuit group Rg+ (Figure 2 (al)).

It shows the output state of the operation code input to the operation decoder OPD (Fig. 2 (b)) via AND++ to AND+a (Fig. 2 (b)), and during one execution cycle of clock t 1 = t a. indicates that if the same operation code is output and the instruction is for one execution cycle, the operation code will change to that of another instruction in the next execution cycle. FIG. 4 (al to hl are the same as FIG. 3(a) to fh).

Figure 4 (11 is Figure 2 (ill's Noah Game 1-N0R2
The output signal G5O2 in Fig. 4 (J) is also the NOR gate N.
Output signal GDST of OR+, FIG.
S■, Figure 4 +11 to (0) are AND gates A N D
Output signals GT1 to G'r4 of D7 to a to 8, Fig. 4 (
ρ) is the output signal φ of the analog game) ANDl. .

Figure 4 (ql, (rl is launch circuit group Rg5.Rg6
4 (31 is a signal indicating the output state of the lotus line BUS (Figure 2 (C)), Figure 4 (11 is a random access signal from the control signal generator C0NT (, Figure 2 (b)) The fourth signal R/W instructs the memory RAM (Fig. 2 (C)) to write and read data.
Figure (ul is flip-flop FFI (Figure 2(b)
), the output signal "NOP" in FIG. 4(v) is the launch signal of the launch circuit group Rg7 (FIG. 2(d)).

Now, each operation when a data storage command is executed, for example, will be explained with reference to the time chart of FIG. The instruction operation for this can be roughly divided into two execution cycles.

First, as shown in FIG. 4 fwl, the cycle in which the data storage instruction is input is cycle 8 of the instruction that activates the pseudo-instruction. When a data storage command is input, the control signal generator C0NT simultaneously outputs a pseudo command signal GSI.
Output. (Fig. 4(k)) Then, during the latter half of clock t4 in this execution cycle A, that is, during the time when clock t4 and main clock φ1 are simultaneously at high level, ant gate AND3 is turned on, and flip-flop FF+ is set, and from the beginning of the next execution cycle B, the output of flip-flop FF1 becomes high level, and a no-operation signal "NOP" is output.

(FIG. 4 ft++) The "N OP" signal turns on the gate group Gg9 and outputs the contents of the launch circuit group Rg+o. Prior to this, the output signal GDST of the NOR gate NOR+ becomes high level from clock 2 to clock t4 in execution cycle 8, so that signal turns on the gate group Gg2 and connects the address line to the latch circuit group Rg.
3 (FIG. 2(a)) is outputting the address data stored in FIG. Then, when the main clock φl heard in the latter half of clock t4 in execution cycle A becomes high level), pseudo-instruction signal GSI becomes
R+, latch circuit group Rg via AND gate AND+
+o launch circuit signal φ. (Figure 4(p)). At this time, the half adder HA2, which is the input to the launch circuit group Rg+o, is connected to the latch circuit group Rg3 (see FIG. 2).
The address data from a)) is input manually, and the carry input C1N is inputted to the pseudo command signal GSI by the inverter I6.
Since the input signal is input, the carry input C1N is "0" in this case, and the output of the half adder HA2 becomes the address data, which is output from the latch circuit group Rg+o. Therefore, when the gate group Gg9 is turned on at the beginning of execution cycle B, the launch circuit group Rg3 (
The address data shown in FIG. 2(a) is output. When the no-operation signal "NOP"' is output, the AND gate AND++~ΔN is output via the inverter I3.
Since D+6 is turned off, the external (launch circuit group Rg+
) will no longer be input (FIG. 4(d)). Furthermore, since the "NOP" signal is simultaneously input to the NOR gates N0RI and N0R2 to turn them off, the launch circuit group Rg2. Rg3 (Figure 2(a))
Address data from is blocked. These operations result in an internal operation of the control circuit, that is, a pseudo-instruction execution cycle B. At the beginning of this execution cycle B,
Since the clocks φRL)1 to φ404 become high level (FIG. 4(C)), data from the read-only memory ROM is stored in the launch circuit group Rg+ to Rga. Of these data, 16 bits are data to be stored in the random access memory RAM. These data are transferred 4 bits at a time from the north line BUS to the RA by 4 clocks from clock 1+ to ta in execution cycle B.
Written to M. The operation will be explained below.

In the second half of clock t1 of execution cycle B (when main clock φ2 is at high level), the "NOP" signal outputs the latch signal φC (FIG. 4(p)) to OR+ and ND+ to AND gate. It outputs and latches the launch circuit group Rg+o.

At this time, the input half adder HΔ2 is connected to the launch circuit group Rg from the address data line as described above.
3. Since the address data (Fig. 2 (a)) is input and the pseudo command signal GSI is "0", the signal inverted by inverter 6 is input to the carry human power C1N. ing. Therefore, in the latter half of the clock t1, from the latch circuit group Rg+o to the gate group Gg9
Data obtained by incrementing the address data by one address is output to the address line via
becomes. At this time, AND gate A N D? turns on, outputs the signal GT+ (Fig. 4 (1)), and turns on the gate group Gga (Fig. 2 (al). As a result, 4-bit data from the launch circuit group Rg3 is output to the pass line BUS. Then, at the same time, the R/W signal is output from the control signal generator C0NT (FIG. 4 (tl)), and this data is written to the address specified by the address input ADD.Next, the execution In the latter half of the clock t2 of cycle B, the launch signal φ is output again via the OR game FOR+ and the AND gate AND1, and the launch circuit group Rg10 is latched.At this time, the clock t is output by the half adder HA2.
The address incremented by 1 is further incremented by 1 address, and is output to the address line via the gate group Gg9, and becomes the address input ADD of the random access memory RAM. At this time, the AND gate AND6 is turned on at the same time, and the gate group Qgs is turned on by the signal GT2 (Fig. 4(m)), so new 4-bit data is written to the RAM via the lot line BUS. . Similarly, the clock t
3. At ta, the AND gate AND5. Signals GT 3 and GT a are output from ANDt, and gate group G
g7. By sequentially turning on Gge, 4 bits of data are written to addresses incremented by one address in the random access memory RAM. By the above operation, 4 bits x 4 data can be stored from the read-only memory ROM to the random access memory RAM in a total of two execution cycles of execution cycles Δ and B. In the latter half of clock t4 of execution cycle B, the AND gate AND2 is turned on and the flip-flop FF+ is reset, so the NOP" signal becomes "0" and the next execution cycle returns to the execution cycle C of TSUTOMI. .

Note that in execution cycle A, clock φA11)L
((■) in FIG. 4) is a latch signal for storing a netast address for determining the address of the only memory ROM for the next execution in the launch circuit group Rg7 ((d) in FIG. 2). In this embodiment, when a data storage instruction is executed in execution cycle A, the contents of latch circuit group Rg4 (second i ta) in that instruction become the next address, and half adder 1 (A2 (Fig. 2) dl), launch circuit group Rg7 via gate group Gga
is stored in Its operation is as described above. This next address is the address of data in the read-only memory ROM that is to be stored in the random access memory RAM in execution cycle B. Then, the data at this address is transferred to the launch circuit group Rg by the clock φ712o1 to φp, oa at the beginning of the execution cycle B.
+ to Rga (FIG. 2(a)).

Furthermore, as described above, the contents of the launch circuit group Rg3 (Fig. 2(a)) in the data storage instruction in execution cycle A are random when storing data in the read-only memory ROM to the random access memory RAM. This is the address one address before the start address of the access memory RAM. In execution cycle B, latch circuit group R
Among the data stored in g+ to Rga (FIG. 2(a)), the content of the launch circuit group Rga is the address (next address) of the instruction to be executed when returning to the execution cycle C of the next lightning strike. By the same operation as described above, the data is stored in the latch circuit group Rg7 (FIG. 2(d)) using the clock φADL (FIG. 4(U)). Then, the instruction at the address of the read-only memory ROM specified by this is executed at the clocks φiol to φR at the beginning of the execution cycle C.
latch circuit group RgI-Rg4 (Fig. 2(
a)) is input and executed.

In addition, in a normal instruction, the output signal GSO of the NOR gate N0R2 (FIG. 2 (bl)) becomes high level (FIG. 4 (il)) at the clock t1, and by turning on the gate group Gg3, the latch circuit group Rg 2 (second
The contents of figure (a)) are random access memory RAM (
This becomes the address input ADD in FIG. 2(C)). The content of the data at that address is output from the output D0LIT, and the launch circuit group R
gr, (FIG. 2(C)).

Furthermore, at clock t2~4, the output signal GDST of NOR gate N0R1 (Fig. 2 (bl) (7)) becomes high level (Fig. 4 (Jl)), and gate group Gg2 is turned on (gate group Gg3 is turned off). ), so the launch circuit group Rg3
The contents of (Fig. 2(a)) are random access memory R.
It becomes the address input ADD of AM, and the contents of the data at that address are output from the output D OUT, and the launch circuit group Rg5 (second
(C)).

These latch circuit group Rg5. According to the output of Rg 6, the arithmetic operation according to each instruction is executed in the arithmetic circuit ALU and the result is output.

As described above, in next address type program control, data can be set in the program area and can be freely retrieved and processed, making programming easier and reducing programming time, that is, development time. Furthermore, since an external read-only memory ROM dedicated to data is no longer required, costs are also reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the invention, FIG. 2 is a detailed circuit diagram of the embodiment of the invention, and FIGS. 3 and 4 are time charts of the embodiment of the invention. Gg2. Gg3. Gg5. Gg 9...Gate group, AND +~AND 7...And gate,
OR1...Or game I-1NOR+. NOR2...Nor gate, HA2...Half adder, Rglo...Latch circuit group. Patent applicant Casio Computer Co., Ltd. agent patent attorney
Yoshiyuki Osuga Figure 3 ":':'ol+ L, Battle Cycle--1" No. 4133

Claims (2)

[Claims] (1) In a processor using the next address method, 5
A random access memory, an address means for sequentially specifying addresses of the random access memory, a selection means for connecting a data line of a memory in which a program is stored to a data terminal of the random access memory, and a control means. . A control device for an electronic device, wherein the control means controls storing output data of the memory at an address designated by the address means of the random access memory. (2) The addressing means comprises an adder circuit in which a key is set to logic l, and a launch circuit for launching the output of the adder circuit, and the output of the launch circuit specifies the random access memory and 2. The control device for electronic equipment according to claim 1, wherein the control device inputs the signal to the adder circuit. (3) The selection means has a plurality of gate circuits corresponding to the bits of the data terminal of the random access memory,
2. The control device for electronic equipment according to claim 1, wherein said gate circuit is separately connected to a data output of said memory.