JPS5955541A - Controller of electronic device - Google Patents

Abstract

PURPOSE:To realize the nesting of a subroutine without providing an exclusive register, by providing a gate circuit on an address line between a memory and a processor and a latch circuit connected to a bus line of the processor. CONSTITUTION:An address selection signal AS generated from a control signal generating part CONT is set at a high level. Thus a gate group Gg10 is turned on, and a gate group Gg5 is turned off via an inverter. Then a clock is generated to store the 12-bit data stored in a latch circuit group Rg11 is then stored in latch circuit groups Rg7 and Rg8 respectively. With this instruction the address to be executed next is not equal to an address that is designated in the instruction but an address that is stored in the Rg11. Thus it is possible to change the address to be executed next within a program without using an exclusive register.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a processor, and more particularly to a control device for an electronic device including a next address type microprocessor which has an address to be executed next in a memory program.

Processors are currently used in control devices and the like. Processors execute programs created in advance, and most of them have arithmetic functions. The operation W function has the function of performing logical operations, such as addition and subtraction.

Processing such as AND and OR is performed. Microprocessors are used in various devices because they have such functions. The same applies to electronic musical instruments, and these processors are used to control musical tone generation in recent electronic musical instruments.

The processor as described above sequentially executes programs stored in memory. However, programs that can be used in common are generally executed as subroutines, and in such a case, a jump is made to the subroutine program, and upon completion, execution of the original program is continued. A processor capable of jumping to a subroutine program must not have the function of storing the next address during execution, that is, the address next to the address to which the subroutine jumps.

Since these addresses are stored in registers and memories, there is a problem in that the number of elements in one circuit increases.

Additionally, there is a next-address-type processor that requires the next address to be executed in a program. In this netast addressing system processor, the next execution address is specified by the contents stored in the program, and instructions are executed sequentially according to that address. The same applies to processors using this netast addressing method.

A function is required to store the address for executing the original program after executing the subroutine program. For this purpose, a dedicated register or the like must be provided, which poses a problem in that the number of elements in one circuit increases.

Furthermore, since the next address type processor executes the address specified in the program, there is a problem in that the jump destination cannot be easily changed depending on conditions or the like.

The present invention is intended to solve the above-mentioned problems, and its first purpose is to provide a control device for electronic equipment including a microprocessor that allows nesting of subroutines without having a dedicated register. It is about providing. A second object of the present invention is to provide a control device for electronic equipment that includes a microprocessor that allows the next execution address to be changed within a program.

The present invention is characterized by a processor that accesses a memory storing one program and executes a predetermined process, including a gate circuit provided on an address line between the memory and the processor.

a launch circuit connected to a lot line of the processor, and the gate circuit outputs an output of the launch circuit to an address line of the memory in accordance with a control signal of the processor. be.

The present invention will be described in detail below using the drawings.

FIG. 1 shows a block diagram of an embodiment of the present invention. A musical tone generating section 1 that generates digital data of musical tones of an electronic musical instrument is composed of a musical tone generating section 2 and a control section 3, for example, a one-chip L.
This is an S1 circuit. The musical tone generation section 2 generates musical tone digital data B3 based on the control signal CI obtained from the control section 3 and the data obtained via the bidirectional data bus D1, and performs digital/analog (D/Δ) conversion (not shown). output to the device. Further, the bidirectional data bus also inputs data such as status from the tone generating section to the control section 3.

Digital input data B2 is inputted to the control section 3 from outside the musical tone generation section 1, and digital output data B+ is further outputted. This input/output digital data B2. For example, the state of the keys of an electronic musical instrument is detected by Bl. The control device for electronic equipment of the present invention is used for the control unit 3 in FIG.

Figures 2+al to (f) are detailed circuit diagrams of embodiments of the present invention. The read-only memory ROM (not shown) and the circuit diagram in FIG. 2 correspond to the control section 3 in FIG. 1.

Input data B2 is input to the control unit via the input terminal INF, and output data B1 is output via the output terminal OUT. The musical tone generation section 2 is the tone generator T in FIG.
A bidirectional data bus D corresponding to 'G is connected to an internal hash line BUS via a hash sofa BUF. Figure 2 (b
) are arranged on the left and right of Figure 2 (al, (C1, respectively), and Figure 2 (the left and right of Ql are Figure 2 fd, respectively), (f
) is placed. Figure 2 (al, (b), (lower side of C1 is shown in Figure 2 (di, (el), respectively.

(fl is placed.

The data output of the read-only memory ROM (not shown) is controlled by the output of inverter 1.

It is input to launch circuit groups Rg+ to Rg4 via gate group Gg+. The input to the launch circuit group Rg1 to Rga and the data output of the one-only memory ROM are input to the launch circuit group Rg.
1 to Rga are taken in by each of the clocks φRol to φQo4. In the embodiment of the present invention shown in FIG. 2, as will be described later, the AND output of the system clock φ2 and the clock t1 corresponds to the aforementioned clocks φ2°1 to φraot.

The launch circuit group Rg+ latches the lower 6 bits of the output of the read-only memory ROM, and stores an instruction to be executed, that is, an operation code. The output is inputted to the operation decoder OPD via AND gates ANDl+ to ANDI6. The operation decoder OPD decodes the input operation code and outputs it to the control signal generator C0NT. The control signal generator C0NT receives the operation signal sent from the operation decoder OPD,
Each clock signal φ1. φ2 and L I-ta are input, and control signals for each part are generated according to these signals.

Launch circuit group Rg2. The operand of the operation code is input to Rg3. For example, launch circuit group Rg
1 and the operation code is addition, etc., the address of the random access memory RAM is stored in the latch circuit group Rg2°Rg3, and in the case of a page jump, etc., the next page address is stored in the latch circuit group Rg3. Ru.

In the case of the above-mentioned addition, etc., NOA game) N ORI.

Gate groups Gg2.0g3 are each selected by the output of NOR2 and input to the 6-bit address input ADD of the random access memory RAM. The contents of the specified random access memory are output to the output terminal. Clock φ4. output from LIT. Launch circuit group R selectively by φB
g5. Stored in Rg6. Each launch circuit group R
g5° was input to Rg6. The data is further processed by the arithmetic circuit AL.
They are input to input A + -A e and inputs B1 to Bθ of U, respectively. The data input to the arithmetic circuit ALU is subjected to the arithmetic operation specified by the arithmetic control signal generated from the control signal generator C0NT.

It is output to output terminals 81 to S8 and carry output terminals C0 and A. Output terminals 81 to S8 of the arithmetic circuit ΔLU are connected to the lotus line BtJS, and are supplied to the terminal designated by the operation code, that is, the instruction code. For example, in the case of an addition instruction, the random access memory RAM specified by the launch circuit group Rg2
is stored in memory at the address of .

The netast address NΔ to be executed next is stored in the launch circuit group Rga. Control month/signal generator CON
The gate group Gg4 is turned on via the inverter ■2 by the Arres selection signal ΔS output from T. The data of the edge circuit group Rga is stored in the opening/notch circuit Rg7 for the °ζ address via the half adder)]Δ1. Ru. The storage at this time is performed using the clock φADL, and the clock φAo' is not generated unless a page break is specified. I mean.

The lower six bits of the 12-bit addresses of the read-only memories R and OM become the addresses stored in the latch circuit group Rga, and select the address of the read-only memories ROM. If a page break is executed, launch circuit group R
The data of g3 is stored in the launch circuit group Rge via the gate circuit Ggi.

The page and netast address NA are specified at the same time.

Input terminal INF is input to launch circuit group Rgq.

Clock φ, 6. φ, stored by u. The storage of launch circuit group Rg9 and the output of its data are controlled by control signal generating section C0NT. For example, it is used when changing the data output to the output terminal OUT according to an input signal, or when making a desired change to the tone generator TG according to the data of these input/output cover sofas. Naturally, the process of storing the data input to the above-mentioned input terminal in the launch circuit group Rg9.

The process of transferring the data to the random access memory RAM, the process of determining the data, the process of outputting the data, etc. are performed according to a program stored in the read-only memory ROM.

ORGATE OR+, AND GATE AND1~ANT)
7. Half adder HAD, latch circuit group Rg Io
, gate groups Gg5 to Gg9. Impark I3 operates when the contents of a read-only memory ROM in which a program is stored are used as data. For example, when a data storage instruction is executed, the pseudo-instruction signal generated from the control signal generator C0NT is sent to the inverter ■
The address of the ROM of the one-drive only memory is sent to the latch circuit group R via the half adder HA 6.
It is stored in g1o. At the same time, Antogame I・AND
3, the flip-flop FF1 is secessed, and the no-operation signal NOP is output from the output Q.

No-operation signal NOP is sent to gate group Gg9. Ant game 1・AND Turn on a to ΔND7.

Further, gate group Gg2°Gg3 is turned off via NOR gates N0R1 and N0R2, AND gates 8 AND11 to AND16 are turned off via inverter I3, and OR gate OR
+ turns on the AND gate AND1.

As a result, the clock φ1 is input to the launch circuit group Rg1o via the AND gate A N D +, and is sequentially incremented via the half adder HA2.

Its output is input to the address input ADD of the random access memory RAM for addressing. At the same time, the AND gate AND7 is clocked and 1 to t4 are applied.
~ Turn on 0g5~Gge sequentially via AND a,
Further, a write signal is input from the control signal generating unit C0NT to the read/write terminal R/W of the random access memory RAM, and a part of the program stored in the read only memory ROM is stored as data in the random access memory RAM.

NOR1-NOR3, latch circuit R1, R2゜and gate AND l 7. AND l [+, OR gate OR2 is a circuit that determines whether or not to increment the primary address by +1 based on the result of the arithmetic circuit ALU.

In other words, it is a circuit that generates a skip operation based on two conditions. When the outputs of the arithmetic circuits are all zero due to the execution of addition or comparison instructions, the output of the NOR gate NOR3 becomes high level and is taken into the launch circuit R1 at the clock φ. Further imported data is Antogame)AN
D+e, Half Adder HA via Noah Gate N0R2
1 carry human power C1N. The next address is input from the launch circuit group Rga to the half adder HA+, so when the data on the hash line BUS is all zero, its output is changed to -1 and input to the launch circuit group Rg7 to access the address of the read-only memory ROM. do. The same holds true when a carry is output from the LU to the arithmetic circuit, and the carry output is taken into the launch circuit R2 and further into the AND gate ANDI7. Input to half adder llAl's carry power 01N via ORG-1/OR2.

The next address is incremented by 1. The control signal generator C0NT selects the resultant zero or the back of the carry for the calculation.
17. It is selected by the signal input to ΔNI)+e. By operating this circuit, the address increases by +1
may be done. If the result is +1, the program execution skips the next address and executes the next address.

Connected to the pass line BUS, its output is the output terminal OU
The output of the launch circuit group Rg++ connected to T is input to the latch circuit group Rg7 or Rge via another gate group Gg+o.

(A in Fig. 2 (A in el is connected to A in Fig. 2 (d).) This is a case where execution moves to the address specified by the data output to the output terminal. In this case, the control Signal AS generated from signal generator C0NT
As a result, gate group Gg+o is turned on, and Gg4 is further turned off via inverter 2. For example, when returning from a subroutine, the addresses to be returned to are read from the random access memory RAM and sequentially stored in the latch circuit group Rg11.

At the end of storage, gate group Gga is turned off, gate group Gg
+o is turned on, and the address stored in the launch circuit group Rg11 is taken into the launch circuit group Rg7. The above operations are performed by executing multiple programs.

Ann(・Ge1-ANI)+9~ANI)23. The OR game hOR2 operates when the next execution is skipped from 1 to 4 addresses by a signal input from an external circuit to the skip terminal SI<T. The number of skips in this operation is controlled by the skip control signals 81 to s4 generated from the control signal generator C0NT, and the skip terminal S
It changes depending on the data input to KT. For example, when the skip control signal S1 is at a high level and S2 to S4 are at a low level, three addresses are skipped if the data input to the skip terminals 5KT2 and 5KT3 are both at a high level. Also, the skip terminal SK'r2 has a high level.

When a low level is input to each of the skip terminals S K T3, two addresses are skipped, and when both low levels are input, no skipping is performed.

Kate group GgI+, AND gate ΔN D 2 a~A
ND33. OR gates OR3-ORa, flip-flops FF2-FF4. Decoder DOC, latch circuit R3~
R5 operates when the execution address is determined by externally input data. For example, it operates when an instruction to move to IS-less, where the next execution is specified from the outside, is input from the read-only memory ROM. When the above-mentioned command is input to the control signal generator C0NT,
An input designation command signal IWA is outputted from the control signal generating section C0NT and is applied to the flip-flop FFa via an AND gate 8ND32. If set at this time, clock t4 and clock φ are applied to AND gate ΔND32.
Since the tent signal of I is being input, this is done in synchronization with this signal. When flip-flop FFa is sent, its output Q becomes high level and turns on gate group Gg11, which is then connected to AND gate AND via inverter I4.
11 to AND+6 are turned off. Furthermore, the gate group Gg], which is normally on, is turned off because this signal is input through the in-hark circuit 1. That is, by setting this flip-flop FFa, the latch circuit group Rg1-Rga is no longer manually output from the read-only memory ROM, and data input from the external program terminal EPT is sequentially set. That is, when the output of the flip-flop FFa becomes high level, an input wait signal is output from the input wait signal terminal IWT, and a program input is requested to an external circuit (not shown). In response to this signal, part of the data of the program, ie, 6 bits, is inputted from the external circuit through the external program terminal EPT. Further, a signal indicating the number of the aforementioned data is inputted from the terminal ADI, and a clock signal is inputted from the terminal CC. These signals are taken into the latch circuits R3 to R5 by the clock φ1, and are sent to the clocks φ12ol to φF2 of the specified launch circuit group via the decoder DOC.
-od is output from the AND gates AND24 to AND,27. As a result, the specified latch circuit group Rg+~R
A part of the blockogram manually entered is sequentially input to the terminal IEPT in g4. Then, the program of one address is inputted by 4 clocks, a completion signal is inputted to the input completion terminal IWE, and the flip-flop FF3 is inputted.
The flip-flop FFa is sent through the flip-flop FFa. The input program is executed by this reset. Flip-flop FF 2. Inverter 15° OR game) OR4~OR6, AND gate AND 2s~AN
D 3 + connects the clock φQol to φR06 to the terminal ADI
This is a circuit for generating a signal input from the terminal CC in synchronization with the clock φ2.

On the other hand, a tone generator control signal generated from a control signal generating section C0NT is input to the tone generator TG, and a pass line BUS is connected to the tone generator TG via a hash line buffer BUF.

The invention of each part will be explained below using a time chart.

FIG. 3 is a time chart of one instruction cycle of the embodiment of the present invention shown in FIG. Clocks φi and φ2 are system clocks, and most of the elements, especially latch circuits, operate with clocks synchronized with these clocks. Clock t1 of the AND logic of clock t1 and clock φ2
φ2 is the clock φgol of the launch circuit group Rg1 to Rga
~φRD4 and the data output of the read-only memory ROM, that is, the instruction code, is sent to the gate group Gg.
+ into latch circuit groups Rg1 to Rga. ■
The instruction is executed with four clocks.

In this case, the clock t+''ta sets the timing of each execution.

FIG. 4 is a time chart when the circuit according to the embodiment of the present invention executes an instruction. Particularly, the element according to the present invention is the launch circuit group Rg7. Rg e.

Rg1+ and gate group Gg+o, and FIG. 4 shows a time chart when execution is transferred to a jump address stored in the random access memory RAM.

Flip-flop F except when inputting a program or instruction from an external program terminal.
Since the output of Fa is at a low level, the control input of the gate group Ggl becomes a high level through the inverter 11, and the output of the read-only memory becomes the latch circuit group Rg+ to Rga.
Enter.

And o1 to φg on the clock φ. 4 (as shown in FIG. 3, this clock is the AND logic clock tl.phi.2 of the clock t1 and the clock .phi.2) to take in the output of the read-only memory ROM, that is, the instruction code, into the launch circuit group Rg+ to Rga. (At this time, the control input of the gate group Gg11 is at a low level, so it is off. The instruction code shown in FIG. 4 shows the output signals of the latch circuit groups Rg+ to Rga.) The instruction code is the latch circuit After being stored in the groups Rg+ to Rga, the address where the next instruction to be executed is stored is stored in the launch circuit group Rg7 via 1 to the half adder H by the AND logic clocks t1 and φ2 of the clock L1 and the clock φ2. be done. In other words, since the argument to instance 1 stored in the launch circuit group Rg4 indicates the address to be executed next, this causes the read-only memory ROM
The address specifies the next execution address.

Among the instructions stored by the clocks t1 and φ2, the instruction stored in the launch circuit group RgI is an instruction to store the data stored in the random access memory RAM in the lower 4 bits of the latch circuit group Rg11, and the instruction is an instruction to store the data stored in the random access memory RAM in the lower 4 bits of the latch circuit group Rg11. Decoded by OPD, control signal generator CONT
The control signal generator input to the control signal generator performs control corresponding to the command. For example, the contents of the random access memory RAM designated by the instruction stored in latch circuit group Rg3 or latch circuit group Rga are stored in the lower four bits of launch circuit group Rg++. The address of the random access memory RAM is selected by the control signal generating section C0NT, and the signals generated by the control signal generating section C0NT are used to send the addresses of the gate group Gg2 . Gate group Gg3 is controlled to open and close, and one of them is turned on. The data stored in the addressed random access memory RAM is output to the pass line BUS and taken into the lower 4 bits of the launch circuit group Rg11 at clock φ,1. When jumping, such commands are repeated three times in succession. However, in these instructions, the bit positions input to the launch circuit group Rg++ are different. That is, the second execution generates the clock φ,2, which becomes the middle 4 bits.

Further, by the third execution, a clock φp3 is generated, and the contents of the designated random access memory RAM are stored in the upper four pins. The fourth instruction transfers the contents of launch circuit group Rg11 to launch circuit group R.
g7. This is a command to be stored in Rge, and the address selection signal AS generated by the control signal generating section C0NT becomes high level, turning on the gate group Gg+o and turning off the gate group Gg5 via the inverter.

Furthermore, clocks φAl)L, φAヮ are generated, and the 12-bit data stored in the launch circuit group Rg+1 is transferred to the launch circuit group Rg7. Stored in Rge. The address to be executed next by this instruction is not the address specified during the instruction, but the address stored in the launch circuit group Rg11. That is, the next execution will be at the address indicated by the data stored in the launch circuit group Rg11. The clocks ψ, 1 to φ, 3 are generated by the control signal generator C0NT, and the clocks φ
1 and clock t4.

In the fourth execution described above, the clock φADL.

If φADH has occurred but there is no need to change the page address, it is only necessary to change the lower six bits of the address. In this case, the third launch circuit group Rg
There is no need for an instruction to store the contents of the random access memory RAM in the upper 4 bits of ++, and the execution of the jump instruction is completed with 1 total of 3 instructions.

Although the execution of a jump (return) instruction has been explained using FIG. 4, if the data at the output terminal OUT is not used and ignored by the external circuit during execution of a subroutine, the subroutine can be is possible. Before jumping to the subroutine, a return address from the subroutine is generated, the first to third instructions are executed, and stored in the launch circuit group Rg11 to execute the next address. The next execution address is a subroutine, and at the end of the subroutine, the fourth
The contents of the second execution, that is, the contents of the edge circuit group Rg11 are stored in the launch circuit group Rgt.

Execution of this instruction enables the next execution of the instruction that jumps into the subroutine.

As described above, according to the present invention, it is possible not only to jump to a specific address, but also to select and jump to a plurality of addresses stored in the random access memory IJRAM. Furthermore, even without a specific register, by using a group of output latch circuits -IJ-
Allows nesting of routines.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a detailed circuit diagram of an embodiment of the present invention, and FIGS. 3 and 4 are time charts of an embodiment of the civil engineering invention. ROM... Read only memory, Gga. Gge, Gg 9. Gg + o... Gate group, Rgl~Rga, Rg 7. Rge, Rg +
O. Rgll... Launch circuit group, CON T... Control signal generator, OPD... Meperation decoder, RAM... Random access memory, ΔLU... Arithmetic surface 17L patent applicant Casio Computer Co., Ltd. agent Yoshiyuki Osuga, a patent attorney?

Claims (4)

[Claims] (1) In a processor that accesses a memory storing a program to execute a predetermined process, a gate circuit provided on an address line between the memory and the processor, and a launch circuit connected to a lot line of the processor. A control device for an electronic device, wherein the gate circuit outputs the output of the launch circuit to the address line of the memory in response to a control signal from the processor. (2) the memory also records the address to be executed next;
Claim 1 characterized in that the processor is a next address type processor that next executes the address stored in the memory.
A control device for the electronic equipment described in Section 1. (3) The control device for electronic equipment according to claim 1, wherein the output of the launch circuit is connected to an output terminal that controls an external circuit. (4) The control device for an electronic device according to claim 3, wherein the external circuit is a control circuit for an electronic musical instrument that electronically generates musical tones.