JPS5955537A - Controller of electronic equipment - Google Patents

Abstract

PURPOSE:To ensure the effective use of an ROM memory and to facilitate the production of software, by feeding at least either one of the output obtained by a zero detecting means of an arithmetic logical circuit and the carry output of the arithmetic logical circuit to an adder. CONSTITUTION:The output of an NOR3 is set at a high level when the outputs of an arithmetic circuit ALU are all set at zero owing to execution of an addition or a comparison instruction. Thus the data fetched into a latch circuit R1 is supplied to an OR2 via an AND18. If an output is delivered from a character Cout of the circuit ALU, this output is fed to the OR2 via a latch circuit R2 and an AND17. The signal fed to the OR2 is supplied to a character Cin of a half adder HA1 to add +1 to the next address NA which is already fed to the adder HA1. The input of the other side of AND17 and AND18 respectively serves as a control signal generating part CONT, and zero or carry is selected for the arithmetic result by an input signal of AND17 or AND18.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a processor, and more particularly to a control device for an electronic device using the next address method, which stores an address to be executed next in a memory program.

Conventionally, in processors, which control various arithmetic instructions by reading and decoding instructions from RoM (leat-only memory), each instruction, i.e. Enter the address of the next instruction to be executed in the lower 6th and 7th bits of the instruction, for example,
By decoding it, the next instruction to be executed is stored in the ROM.
There is a processor that uses the NA (Next Address) method, in which data is read from a corresponding atlus in the atlas and executed sequentially. In such a next-address type processor, whether the operation results of one current instruction are all O (zero status).

9 For example, 6 bis 1 depending on whether the kyaυ- is alive or not.
- By OR-adding the value of the lower two bits of the next address NA with the zero status signal, carry signal, etc., the NA value is changed and the instruction to be executed next can be changed depending on the operation result of the current instruction. I try to choose. OR addition is, for example, adding specific hints using an OR circuit, and since it is an operation without a carry, the augend value must be zero. That is, if both the addition value and the augend are 1, the output of the OR circuit is 1, and no addition operation is performed.

Hereinafter, an addition instruction will be explained using FIG. 1, FIG. 2, and FIG. 3 as an example.

Figure 1 shows that when a binary addition instruction of 21[1i1 is executed and the result is not 0, the value of the netast address NA included in the binary code of the addition instruction is not changed (decimal number (NA + 0) If the result is 0, then NA
OR add the lower 2 bits of the O value (NA+2 in decimal)
) is a flowchart of conditional logic.

FIG. 3 also shows that in the same addition instruction, if a carry occurs in the result, the lower 1 bit of the NAO value included in the binary code of the addition instruction is ORed (NA+1 in decimal) L, This is a flowchart of conditional logic that if no carry occurs, the value of NA is not changed (NA+0 in decimal notation).

Figure 2 assumes that the address in memory where the addition instruction is stored is page address 00002 (the 2 to the right of the first lower bit indicates that it is a binary number), and page address 0010002. .

The 6-bit NA value in this instruction is

0011002, the above-mentioned FIG.

This figure shows how the value of NA (the address of the next instruction) changes according to the logic shown in FIG.

In FIG. 2, if the result of the operation by the addition instruction is not 0, the value of NA will not change according to the logic in FIG. 1, and the address of the first instruction will be NA-0011002 (in FIG. 2,
y).

Also, if the result of the operation is 0, then according to the logic in Figure 1,
For the NA value, the lower two bits are ORed together.

NA-0011102 (x in Figure 2).

Furthermore, if the addition result is O and a carry has occurred, the lower two bits of the NA value are OR-added according to FIG. 1, and then according to FIG.

By ORing the first lower bit of the NAO value, NA=OO11112.

When calculated in this way, the lower 2 bits of NA are ORed together depending on the condition, so the value of the lower 2 bits of NA is
It must necessarily be O.

NA=0011002, etc. is decided. That is, if the NA in the addition instruction in FIG. 2 is NΔ=00100
12, if the addition result is not 0 and a carry occurs, even if the first bit from the bottom of the NAO value is ORed.

NA=0010012, and as a result, depending on how the NA included in the first addition instruction is set, the NA value may or may not change even if the conditions for the operation result are the same. I end up. From the above, in Figure 2.

The NA in the addition instruction is NA where both lower 2 bits are O.
0011002, etc., and as a result, addresses within the page from 0010012 to 00100112 are unused here, resulting in wasted memory.

In other words, in the NA (Netast Address) method that uses the OR addition method, the addresses where instructions are placed are limited, and it is important for software creators to consider the logic of OR addition when creating software and set addresses. must be carried out.

Furthermore, since the addresses where the data can be placed are limited, there are inevitably many unused read-only memory ROM areas. This thing comes down to it.

A typical example of an inefficient program is one that only makes it even more difficult to determine whether the product specifications to be developed are satisfied (determining whether the software can fit into the limited ROM). In other words, manually assigning addresses and figuring out how to make unused ROM areas more efficient is extremely difficult and takes a lot of time. Almost everything is lost.

Furthermore, if we go back to the OR addition method, we must control the lower 2 bits to oo or the lower 1 bit to 0 when creating the program, so an assembler (
ASS[! MBLER) etc. will be difficult to mechanize. In addition, it becomes difficult to specify an address from outside the control device.

The present invention is intended to solve the above-mentioned problems, and its purpose is not only to eliminate unused areas of memory by providing an adder circuit on the address line, but also to facilitate program creation (program development support). An object of the present invention is to provide a microprocessor, that is, a control device for electronic equipment, which enables the system.

In other words, one feature of the present invention is that a control device that accesses a memory storing a program and executes a predetermined process includes one arithmetic logic circuit and the fact that the arithmetic result of the arithmetic logic circuit is zero. It has zero detection means for detecting, and an adder provided on the address line of the former memory,
A control device for an electronic device, characterized in that the next execution is skipped depending on the calculation result by inputting at least one of the output of the zero detection means or the carry output of the arithmetic logic circuit to the input terminal of the adder. .

The present invention will be described in detail below using two drawings.

FIG. 4 shows a configuration diagram of an embodiment of the present invention. A musical tone generating section 1 that generates digital data of musical tones of an electronic musical instrument is composed of a musical tone generating section 2 and a control section 3, for example, a one-chip L.
It is an SI circuit. The musical tone generation section 2 generates musical tone digital data B3 based on the control symbol c1 obtained from the control section 3 and the data obtained via the bidirectional data bus D1. Output to converter. Further, the bidirectional data bus also manually inputs data such as status from the musical tone generation section to the control section 3.

Digital input data B2 is inputted to the control section 3 from outside the musical tone generation section 1, and digital output data B1 is further outputted. Digital data output by this person B2. For example, the state of the keys of an electronic musical instrument is detected using Bl. The control device for electronic equipment of the present invention is used for the control unit 3 in FIG. 4.

5 (al to (fl) are detailed circuit diagrams of the control unit 3 in FIG. 4. The read-only memory ROM (not shown) and the circuit diagram in FIG. 5 correspond to the control unit 3 in FIG. 4. Input data B2 is input to the control unit via the input terminal INF, and output data B+ is input via the output terminal OUT.
outputs. The musical tone generator 2 corresponds to the tone generator TG in FIG. 4, and the bidirectional data bus D is connected to the internal bass line BUS via the bass sofa BUF.

To the left of Figure 5 fb) is Figure 5 ta+, and to the right is Figure 5 (
C) is arranged and Fig. 5 (dl is placed on the left of Fig. 5 (el), Fig. 5 (f) is placed on the right of Fig. 5 (al, fbl
, (on the lower side of cl, respectively, Fig. 5 fd), fe
d, Ir) are placed.

Data output of the only memory ROM (not shown) is
The launch circuit group Rg+-Rg is
Enter a. The data output of the read-only memory ROM input to the latch circuit group Rg+ to Rga is input to the latch circuit group Rg+ to Rga via the gate group Gg+ controlled by the output signal of the inverter I+. Launch circuit group Rg+"Rg4, each clock φlO+~
Controlled by φ104, the data output of the read-only memory ROM is taken into the launch circuit group Rg+ to Rg4 at these clock timings.

In the embodiment of the present invention, the clock φRot~φl!
o6 is output simultaneously at the end of each instruction (at the beginning of the next instruction). The launch circuit group Rg+ latches the lower 6 bits of output data of the R-only memory ROM, and stores instructions to be operated, that is, operation codes. The output is input to the operation decoder OPD via the AND gates ANI)+t to AND+6 in FIG. 5fb). Antogame-LAND11~Δ
For other inputs of NDI6, inverter ■4 in Fig. 5(a) is used.
The output signal is added, and as will be described later, the output is always at a high level. Operation decoder OPD
(Fig. 5(b)) shows the launch circuit group Rg+(Fig. 5(a)
)) The operation code sent from the read-only memory ROM is output to the lever 1' control signal generator C0NT. The control signal generating unit C0NT generates an operation signal sent from the operation decoder OPD and each clock signal φ1. φ
2° and t1 to t4 are input, and control signals for each part are generated according to these signals.

Launch circuit group Rg2. Rg3 (Fig. 5(a)) latches the lower 7th to 18th bits of the output data of the read-only memory ROM, and stores the operand corresponding to the operation code launched in the launch circuit group Rg+. be done. For example, launch circuit group R
If the operation code stored in g+ is addition, etc., launch circuit group Rg2. Each address of the random access memory RAM is stored in Rg3, and in the case of a page jump, the next page address is stored in the launch circuit group Rg3.

Launch circuit group Rg 3. The outputs of Rg2 are respectively connected to gate groups Gg2. Gg3 (FIG. 5(b)), and the gate group Gg2. The outputs of Gg3 are combined into one system and sent to random access memory RAM (Figure 5 (C)).
The 6-bit address is input manually into ADD. Gate group Gg2. Gg3 is Noah Gate N0RI respectively
, N0R2 (FIG. 5(b)), and their outputs become high-level at different timings, thereby selecting the gate groups Gg2.0g3, respectively.

A control line from a control signal generator C0NT is connected to the inputs of NOR+ and NOR2.

Now, in the case of an instruction such as the above-mentioned addition, the operation code is written to the operation code decoder OPD (Fig. 5(b)
)) and input to the control signal generator. The control signal generation section includes a NOR gate N0R1,
N0R2 is turned on at different timings to select gate group Gg2.0g3. As a result, launch circuit group Rg3. The contents of Rg2 (FIG. 5(a)) are respectively selected and the addresses of the random access memory RAM (FIG. 5(C)) are respectively designated.The contents of the designated random access memory RAM are output terminals. U
The clock ψA is output from T.

φB, these timings are selectively controlled by the latch circuit group Rg5. Rg6 (Figure 5 (C))
- Money will be paid. At this time, naturally, gate group Gg2. Gg3
is selected, that is, the timing of addressing the random access memory RAM and the output of the random access memory RAM. However, the clock φ4. φ
Launch circuit group Rg at θ 5. The timing selected by Rg 6 is synchronized. Each launch circuit group Rg5
゜The data input to Rg6 is further sent to the arithmetic circuit ALU.
Inputs are made to input persons 1 to Ae and inputs 81 to B@ (FIG. 5(C)), respectively. The data input to the arithmetic circuit ALU is subjected to the arithmetic operation specified by the operation control signal by the arithmetic control signal generated by the control signal generating section C0NT, and is then output to the output terminals 31, 32, 1, 32, . Sa, Se and carry output are output to C3UT. (Figure 5 (C1) 4
Bit output terminals 31.32. S4. Se is connected to the lotus line Bus, and is stored in the terminal specified by the operation code. For example, in the case of an addition instruction, the instruction is stored in the memory at the address of the random access memory RAM designated by the latch circuit group Rg2 (FIG. 5(a)).

The launch circuit group Rga (Fig. 5(a)) latches bits 2 to 6 of the output data of the read-only memory ROM, and stores the address of the instruction to be executed next, that is, the next address NA. Ru. The output of the launch circuit group Rga is the half adder HA+ and the gate group G g
The launch circuit group Rg7 for determining the in-page address of the next one-step only memory ROM is connected to
) is entered.

Further, the output of the launch circuit group Rg3 is inputted to the launch circuit group Rge (FIG. 5(d)) for determining the page address of the primary read-only memory ROM via the gate group Gg4. Storage in Rg7 is performed using clock φADL I Rg
The storage in B is performed in synchronization with the clock φAI)l-I. Assuming that a page change is not performed, first, the address selection signal AS output from the control signal generating section C0NT becomes low level, and this signal turns on the gate group Gga via the inverter 2. As a result, the netast address NA of the launch circuit group Rga is transferred to the launch circuit group Rg7 via the half adder H-AI.
It is stored at the timing of clock φADL. At this time, a page break will not occur.

Clock φAo,4 is not generated, and therefore no storage is performed in latch circuit group Rge. by this.

Among the 12 bits for determining the address of the read-only memory ROM, the lower six bits become the address stored in the latch circuit group Rga, and specify the address within the page of the read-only memory ROM.

At this time, the page address of the upper 6 bits for address determination is not changed, and no page break is performed.

Next, when a page break is to be performed, the output of the inverter I2 becomes high level, the gate group Gga is turned on, and the clocks φΔDL and φ8. .

As a result of the simultaneous occurrence of ``, in addition to the above operations, data specifying the next page due to the page break of the two latch circuit group Rg3 is stored in the launch circuit group Rgθ. The second 6 bits become the address stored in the latch circuit group Rg3, specifying the page address of the read-only memory ROM, and the lower 6 bits specify the in-page address by the above operation, specifying a page break, and the netast address NΔ.
are specified at the same time.

Note that the operation of the half adder HA+ will be described later.

The input terminal INP (Fig. 5 (C)) is, for example, in the case of an electronic musical instrument, a terminal for inputting signals such as a keyboard, a function switch for specifying a tone, a rhythm, etc. Although not shown in the figure, the input terminal INP (Fig. The gate is stored in the launch circuit group Rg9. Naturally, the storage operation and the data output operation from the launch circuit group Rg9 (FIG. 5(C)) are controlled by a control signal from the control signal generating section CON_T. The input data output from the launch circuit group Rg9 is read-only memory ROM.
According to the program stored in Hass Line BU
Various determinations and processes are performed via S.

Figure 5 (ORD1~OR1 in BL, AND GATE AN
D, +~AND? , half adder HA2, launch circuit group Rg+o, gate group Gg5-Gge, and inverter 3 operate when the contents of the read-only memory ROM are used as numerical data. For example, when a data storage instruction is executed, the secondary execution is performed by the control signal generator C.
It is controlled by a pseudo command signal generated from 0NT.

Pseudo-command signal.

It is inverted at the impark 16 and sent to the carry human CIN of the half adder HA2, and directly via the OR gate OR+ and the AND gate AND+, the launch circuit group Rg+o
latch signal input. Further, this pseudo-instruction signal is input to the AND gate AND3 for setting the flip-flop FF+. Now, by executing the data storage command, the control signal generator C0
When a pseudo-command signal is issued from NT, read-only memory R
The specified address from OM is half adder HA
2, it is incremented by 1 bit by the pseudo-instruction signal, and at the same time.

Ant game) Half adder 14 is input to launch circuit group Rg1o at the timing of black 7ri φ1 input to AND +.
The output of A2 is stored. At the same time, one flip-flop FFI is set via the ant' gate AND3 (the AND signal of the timing signal t4.φI is applied as another input to the ant' gate AND3), and the no-operation signal NOP is output from the output Q.
is output.

The no-operation signal NOP turns on the gate t[\Gg9, and also turns on the NOR gate NOR+.

Through NOR2, gate group Gg2. Gg: Turn + off. As a result, the signals from the launch circuit group Rg2°Rg3 are blocked, and the address signal incremented by the half adder to HA2 is input to the address input ΔDD of the random access memory RAM via the launch circuit group Rg+o and the gate group Gg9. be done. Furthermore, the no-operation signal NOP is ant game-1-ANDa~ΔN
It is input to D7 and turns on the gate b AN D 7 at the timing of the clock t1, and this output turns on the gate group Gga (FIG. 5(a)). As a result, the data of 4 hints in the latch circuit group Rg3 (FIG. 5(a)) are input to the random access memory RAM (FIG. 5(C)) through the pass line BUS.

A write signal is generated at the read/write terminal R/W from the control signal generating section C0NT, and is thereby written as 4-bit data into the memory at the address corresponding to the aforementioned address input ADD of the random access memory RAM. Further, the no-operation signal NOP turns on the OR gate OR+ and is input to the AND gate AND+. Therefore, at the timing of the primary clock φ1, -
Launch circuit group Rg+o is launched. At this time, since the previously incremented address signal has been feed-hacked to the input of the half adder HA2, it is again increased by 1 bit by the pseudo-instruction signal and is input to the launch circuit group RgIa. The output of the launch circuit group Rg+o is input as a signal advanced by one address to the address input ADD of the random access memory RAM via the gate group Gg9. Since the no-operation signal NOP is added to the AND gate A N D 6, the AND gate AND
6 is turned on, and this output is output from gate group Gg6 (Fig. 5(a)
)). Therefore, the 4-bit data in the latch circuit groups Rg2 and Rg3 of FIG. The memory corresponding to the advanced address is written.

After that, t3. Similarly to t3, the address is advanced and 4-bit data is written to the random access memory RAM. As described above, the data in the three read-only memory ROMs is written as four sets of 4-bit disks, one address at a time, starting from the specified address in the random access memory RAM.

It is connected to the lotus line BUS, and its output is the output terminal OU.
Latch circuit group R connected to T (Fig. 5(e))
The output of g1+ (Fig. 5(e)) is the output of other gate group Gg1
o (FIG. 5(d)) to launch circuit group Rg7. Rg
Enter e. (A in Fig. 5(e) is shown in Fig. 5(d).
(connected to A of l) This is a case where execution moves to the address specified by the data output to the output terminal. At this time, the address selection signal AS generated from the control signal generation section C0NT is at a high level, so that
Gate group Gg+o is turned on, and further inharc I2
This turns off gate group Gga via.

The next 1-address signal NA and page feed signal input to the gate group Gga are blocked, and the launch circuit group Rg
11 outputs are selected by gate group Gg+o.

For example, when returning from a subroutine, the address to return to is read from the random access memory RAM, and the clock φ is output by an output command. ! ,φ,2. φ
Launch circuit group R sequentially at timing p3 (not shown)
The addresses are stored in latch circuit group Rg7. It is taken into Rge and used as the address of the read-only memory ROM for the primary instruction. The above operation is.

Naturally, this is executed by a program stored in the read-only memory ROM.

Gate group Gg++ (Fig. 5(a)) and Fig. 5ffl
AND gates AND24~AND33° OR gates OR3~OR6, flip-flops FF2~FF, shown in
a. The decoder Doc and latch circuits R3 to R5 operate when the execution address is determined by data input from the outside.1 For example, a command to move the next execution to an address specified from the outside is input from the read-only memory ROM. When it works. The above instructions are shown in Figure 5 (
When input to the control signal generating section C0NT of BL, the control signal generating section C0NT outputs the command signal IWA, which is input to the control signal generating section C0NT. Set FF4. At this time, since the AND signal of clock t4 and clock φ1 is input to Antogame 1-,
This is done in synchronization with this signal. flip flop FF
When a is input to Seso 1, its output Q goes to high level, turning on gate group Gg11 (Fig. 5(a)), and further outputting AND gates AND1+ to AN via impark I4.
Turn off D16 (FIG. 5(b)). Furthermore, the gate group Gg+ (FIG. 5(a)), which is normally turned on, is turned off because this signal is input through the inverter 1. That is, by setting this flip-flop FFa, the launch circuit group Rg1 to Rga (FIG. 5(
a)> is no longer input with the output of the read-only memory ROM, and the external program terminal EPT (Fig. 5 (d))
The data that is input is cented sequentially.

That is, when the output of the flip-flop FFa becomes high level, an input wait signal is output from the input wait signal terminal IWT.2 This signal requests a program input to an external circuit (not shown), and a part of the program is sent from the external circuit. data.

That is, 6 bits are input from the external program terminal EPT. Further, a signal indicating the number of the aforementioned data is inputted from the terminal ADI, and a clock signal is inputted from the terminal CC. These signals are taken into the latch circuits R3 to R5 by the clock φl, and are sent to the clocks φ1lol to φ of the specified launch circuit group via the decoder DOC.
ρo2 is output from AND gates AND24 to AND27. As a result, the specified launch circuit group Rg+~Rg
A part of the program inputted to the terminal EPT is sequentially inputted to a. A program of one address is input by four clocks, an IWE completion signal is input to the input completion terminal, and the flip-flop FFa is reset via the flip-flop FF3. The input program is executed by this reset. Flip-flop FF2゜inheritance 15. OR GATE OR MIL O
R6 and AND gates AND2e to AND31 are circuits that generate clocks φP01 to φpod from signals input through terminals ADI and CC in synchronization with clock φ1.

On the other hand, the first generator TG (FIG. 5(C)) has a controller call signal generator C0NT (FIG. 5(b)).
The tone generator control signal generated by the tone generator control signal is input, and the pass line BUS is connected via the pass line buffer BUF.

NOR1-NOR3, latch circuit R1, R2 (Fig. 5 (C1), Antgame) ANDl? .

ANDle (Fig. 5 (fl), OR gate OR2 (Fig. 5
FIG. 5(d)) is a circuit that determines whether or not the next address, that is, the next address NA, is incremented by -1 based on the result of the arithmetic circuit ALU of FIG. 5(c). In other words, it is a circuit that generates an operation to skip the address of the next instruction based on nine conditions. Now, by executing the addition comparison instruction,
The output of the arithmetic circuit ALU.

When all are O, the output of the NOR gate NOR3 becomes high level, and is taken into the launch circuit R1 at the clock φ. Further data is captured.

AND GATE AND + DAY (Figure 5 10), OR GAME)
Half adder HA+ via OR2 (Figure 5(d))
Input to the carry human power C1, 4 (FIG. 5(d)).

Since the netast address NA is input to the half adder I (A1) from the launch circuit group Rga (FIG. 5(a)), the netast address NA is incremented by 1 and latched by the output of the OR game 1-0'R2. When input to the circuit group Rgv, access is made by setting the netast address of the next instruction in the only memory ROM as NA-)-1. In addition, Fig. 5 (C
The same is true when a carry is output from the arithmetic circuit ALU of No. 1, and the carry output C0IJT is taken in by the latch circuit R2 (Fig. 5 (C)), and then the AND gate AND+
7 (Fig. 5 + r)), OR Gate 0R2 (Fig. 5 (d)
) via.

It is input to the carry power C1゜1 of the half adder 11A1, and the netast address NA is incremented by 1. The operation of adding 1 to the next address NΔ is performed by the arithmetic circuit ΔLU (Figure 5 (C)).
In this case, whether to perform the operation when all the results are O or when the carry output CiN is generated is determined from the control signal generation unit C0NT (FIG. 5(b)) in FIG. 5(f).
)'s Antogame-1~ANDl? .

It is selected by the signal input to AND+8.

In the above operation, when the next address NA is incremented by 1, the primary instruction skips the next address NA (the address next to the address of the current instruction) and becomes the next address.

AND gate AND+9~AND23. Or game) OR
2 (Fig. 5(d)) is the skip terminal SK from the external circuit.
It operates when the signal input to T causes the execution of the primary instruction to be skipped from 1 to 4 addresses. The number of skips in this operation is determined by the skip control signals 81 to S generated by the control signal generator C0NT (Fig. 5(b)).
6, the skip terminal 5KT (Fig. 5(d)
)) varies depending on the data input. For example, when the skip control signal S+ is at high level and S2 to Sd are at low level, the skip terminals S K T 2 , S
When the signals input to KT3 both become high level.

Skip 3 addresses. Also, skip terminal 5KT2
When SK'r3 becomes high level and SK'r3 becomes low level, two addresses are skipped. Also.

When the skip terminal 5KT2 goes high and the skip terminal 5KT3 goes low, two addresses are skipped, and when both go low, no skipping is performed.

Next, the operation of the embodiment of the present invention described above will be explained.

This will be explained using a timing chart.

FIG. 6 shows the timing of each signal when the instruction read from the read-only memory ROM is an instruction for an operation related to addition.

Figures 6 (al and b) show the main clock that controls the overall operation, and are two-phase clocks of φ1 and φ2. Figure 6 fc) and (f) show the main clock φ2.
The clocks t1 to t4 are synchronized with t1 to t4, and tl to t4 are 1
In the case of an addition instruction as a unit execution cycle, two execution cycles constitute one instruction cycle. Fig. 6 (hl and +i1 are not used directly in the operation explanation here, but
In the above two execution cycles, each execution cycle 1
．． This is a signal indicating execution cycle 2. Figure 6 (g)
At the end of one instruction (beginning of the next instruction), the main clock φ
The signals φgot~φ&Q4 (in this embodiment, output simultaneously) are output in synchronization with φRol(
~φgon) to the next φgo+(~φ*o4) is 1
It is a command cycle. FIG. 6 fj) is a signal φAD generated as an AND output of clock φI and clock t1.
L, and the netast address is read-only memory RO.
This is a launch signal to be output to M.

In FIG. 6(k), 1 does not occur in the case of an addition instruction.

This signal φADI-1 is a jump instruction to be described later and is generated as an AND output of clock φI and clock t1. FIG. 6 (1) is an addition instruction and clock φ1
and the signal φ5 generated as the AND output of clock t4.
This is a signal that latches each status of the calculation result, which will be described later.

Now, in FIG. 5(ill), if the data read from the read-only memory is an addition instruction, each data is read from the read-only memory ROM at the timing of clocks φEQI to φQO6 (FIG. 6(g)). Data is stored in launch circuit groups Rg+ to Rga.

The output from the launch circuit group Rg+ indicates an addition instruction.

Decoded by operation decoder OPD.

When the control signal is input to the control signal generator C0NT (Fig. 5(b)), it is sent to the read/write terminal R/W.
In the random access memory RAM (FIG. 5(C)) by generating a read signal.

The addresses of the two data to be added are determined by clock tl and clock t2, respectively, and launch circuit group Rg5
．． Clock φ4 to Rg6. It is stored in φB. Clock φ4. Although not particularly shown, φ9 (FIG. 5(C)) is generated at the timing of clock φ1 of clock t1 and clock L2, respectively.

Launch circuit group Rg 5. The output of Rg 6 is the arithmetic circuit A
The addition is performed by the arithmetic control signal inputted to the LU (FIG. 5(C)) and from the control signal generator C0NT (FIG. 5(b)). Thereby, its output is determined between clocks t3 and t4.

If the addition result is 0, the signal indicating zero status is
The signal is stored in the 5-launch circuit R1 via the NOR gate NORe at the timing of the clock φs7 (FIG. 6(I)). Similarly, when a carry occurs in the addition result (carry status), the carry signal is sent to the launch circuit R2.
is stored at the timing of clock φ5T. Launch circuit R1, indicating zero status and carry status.
The output of R2 is.

AND GATE AND+ 7. AND+ e (Figure 5 (
After being selected in (f)), or game) OR2 (Fig. 5 (d)
)) Carry human power C1 of Half Adder HA+
Launch circuit group R that joins N and indicates the next address NA
It is added to the output of ga (FIG. 5(a)). The added netast address is passed through the gate group Gg4 to the clock φAI)L that follows the clock φST (FIG. 6 (J)).
At this timing, the signal is stored in the launch circuit group Rg7 and becomes a signal for accessing the read-only memory ROM as the address of the secondary instruction. At this time, the clock φc. Because H does not occur.

No signal is input to the launch circuit group Rge, and no page break is performed. The secondary clock φ1 is generated by the above next address (Fig. 5 (output of launch circuit group Rg7 of dl)).
At timings 1101 to φRo4, the current next instruction is read from the read-only memory ROM, and the addition instruction ends. In addition.

At this time, before the clock φST, the clock φAI)L
has occurred (Fig. 6 (J)), and the launch circuit group R
g7 (Fig. 5(d)), launch circuit group Rga (Fig. 5(d))
The netast address NA from Figure (a)) is stored, but in the case of an add instruction, the l instruction cycle has not yet been completed, so the next address in the read-only memory ROM by the output of the launch circuit group Rg7 is stored. Access to the address of the instruction is not performed and is ignored. Furthermore, during the second execution, the clock generation prohibition signal from the control I/roll signal generating section C0NT is applied to the AND gates AND24 to AND27, so that the clocks φro1 to φko4 are not output. Then, at the next clock φADL after the clock φsr is generated, the address of the next instruction in the read-only memory ROM is accessed.

FIG. 7 shows the operation timing for the jump command. The clocks in FIG. 7 (fat to fl) are as follows.

This is the same as the case in FIG. Note that in the case of a jump instruction, one instruction cycle is one execution cycle. now,
Data from the read-only memory ROM is clocked φ
The data is stored in the latch circuit group Rg+ to Rga (FIG. 5(a)) at the timing of frames 1 to φRo4 (FIG. 7(g)), and the output of the launch circuit group Rg1 is output by the operation decoder OPD.

If it is decoded as a jump instruction, the clock φ
At the ADL timing, the netast address that is the output of the launch circuit group Rga is stored in the launch circuit group Rg7 via the half adder HA + and the gate group Gga (FIG. 5(d)). Furthermore, due to the clock φ5I)H < FIG. 7(h)) generated at the same time as the clock φAC)L, the page address, which is the output of the launch circuit group Rg3 (FIG. 5(a)), is transferred via the gate group Gga. Launch circuit group R
ge. (FIG. 5(d)) As described above, when a jump instruction is executed, the page address of the jump destination is output from the launch circuit group Rge at the timing of the clock φADH, and the clock φ4tlL is generated at the same timing as the clock φApH. At the timing, the next address NA is output from the latch circuit group Rg7. As a result, the address of the next instruction in the read-only memory ROM is accessed, and the jump instruction is completed. Note that at this time, the clock φs7 is not generated, so in the half adder HAI (Fig. 5(d)), the next address which is the output of the launch circuit group Rg4 (Fig. 5(a)) is not changed and is sent to the latch circuit group as it is. R, g7
is output to.

The above is the operation timing for specific instructions.

In addition, in determining the netast address NΔ, the output of the addition result of the arithmetic circuit ALU (Fig. 5 (C)) in the addition is all 0 (zero status), or the carry status is ) is selected and the next address is increased by +1, but the NOR gate NOR3 in FIG. 5(C) or the un[gate AND+ 7.AND+
By changing the configuration and connection of the OR gate OR2 in FIG. In particular, the input for 1 to Half Adder II does not have to be carried manually, and may be weighted appropriately.

As explained above, the address of the secondary instruction can be set as one address or several addresses ahead of the next address NA of the current instruction, depending on the conditions. Therefore, the netast address NA may be the address next to the address of the current instruction. This will be explained with reference to FIG. First, Figure 5 (a+~
(In the embodiment shown in fl, the next address is incremented by 1 depending on whether the addition result is zero status or carry status. Therefore, in FIG. 8, at G1, the addition instruction is at page address OOOOOOOO.

Assuming that the address is within the page address 001000, the next address NA can be set as NA-001001. Here, if the addition result is all 0 (zero status) and is changed to -1, the address of the secondary instruction will be 001010 (x in FIG. 8) in the NA'' river. If it is not all O, NA will not be changed, 001001
(y in Figure 8). You can do the same thing if you change your carry status to tI).

As a result, the next address NΔ can be set to the address following the address of the current instruction, so the memory of the read-only memory ROM can be used efficiently and software can be created easily. This reduces software development time and makes it easier to trace and modify the created software. In addition, Tessembler ^SSEMBLER)
It is easy to create G.

[Brief explanation of drawings]

Figure 1 depends on whether the addition result is 0 or not. Flowchart for determining whether to skip. FIG. 2 is a master knob diagram of a memory according to the conventional method, FIG. 3 is a flowchart for determining whether to skip depending on whether or not a carry is reached by addition, and FIG. A block diagram of a musical tone generator; FIG. 5 is a circuit diagram of an embodiment of a control device for electronic equipment according to the present invention;
Fig. 6.7 is a time chart of an embodiment of the present invention, and Fig. 8 is a memory master knob diagram of an embodiment of the present invention. ALU...Arithmetic circuit NOR3...Nor gate ΔN+ )+7. 8ND1e...An1 gate HA+
...Half Adder Patent Applicant Casio Computer Co., Ltd. Representative Patent Attorney
Yoshino Osuga 1] Middle school 3m 01111 Age 21 Junior high school 8 mother

Claims (5)

[Claims] (1) In a control device that accesses a memory that stores a program and executes a predetermined process. an arithmetic logic circuit, a zero detection means for detecting that the arithmetic result of the arithmetic logic circuit is zero, and a sawtooth adder provided on the address line of the memory; A control device for an electronic device, characterized in that by inputting at least one of the carry outputs of the logic circuit to the input terminal of the adder, the next execution is skipped depending on the calculation result. (2) The memory also stores an address to be executed next, and the control device is a netast address type processor that next executes the address stored in the memory. A control device for electronic equipment according to scope 1. (3) The control device for electronic equipment according to claim 1, wherein the zero detection means is a NOR circuit. (4) The control device includes a selection circuit that selects the zero detection means and the carry output of the arithmetic logic circuit, and a control circuit that controls the selection circuit. A control device for the electronic device described. (5) The selection circuit is the first one. The second AND gate and the OR gate consist of the first AND gate. First inputs of the second AND gates are respectively connected to the control circuit, and second inputs of the first AND gates are connected to the zero detection circuit.
A second input of the AND gate of the first . The electronic device according to claim 4, wherein the output of the second AND gate is connected to the input terminal of the OR circuit, and the output of the OR circuit is connected to the carry input terminal of the adder. control device.