JPS5950546A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5950546A JPS5950546A JP57160841A JP16084182A JPS5950546A JP S5950546 A JPS5950546 A JP S5950546A JP 57160841 A JP57160841 A JP 57160841A JP 16084182 A JP16084182 A JP 16084182A JP S5950546 A JPS5950546 A JP S5950546A
- Authority
- JP
- Japan
- Prior art keywords
- film
- forming
- metal layer
- layer
- melting point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Abstract
Description
【発明の詳細な説明】
この発明は、半導体基板上に形成される高融点金属層お
よびその上の主配線金属層からなる積層構造を有する半
導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device having a laminated structure consisting of a high melting point metal layer formed on a semiconductor substrate and a main wiring metal layer thereon.
浅い接合を有する半導体装置、たとえば、高集積密度の
低電カシヨツトキーＴＴＬなどの半導体集積回路におい
ては、主配線金属であるＡｔとシリコンが熱処理によっ
て相互拡散するのを阻止するために、半導体基板と主配
線金属層との間にバリアメタルとして、高融点金属層、
たとえば、Ｗ。In semiconductor devices with shallow junctions, for example, in semiconductor integrated circuits such as high-density, low-power cashier TTLs, the semiconductor substrate and the main wiring metal are bonded in order to prevent At and silicon, which are the main wiring metals, from interdifusing during heat treatment. A high melting point metal layer as a barrier metal between the wiring metal layer,
For example, W.
Ｔｉ ｒ Ｍｏなどを挿入することが一般的であり、熱
的に安定な信頼性の高い半導体装置を得ることができる
。It is common to insert Ti r Mo or the like, and a thermally stable and highly reliable semiconductor device can be obtained.
すなわち、従来の半導体装置は半導体基板上に拡散層を
形成し、半導体基板上の絶縁膜に電極引出し用の窓を形
成し、この拡散層と主配線金属層との間に高融点金属層
を挿入しており、この高融点金属層は主配線金属層と拡
散層中のＳｔとの相互拡散全阻止する役割を有すると同
時に、絶縁膜と拡散層とに主配線金属層を固着させてい
る。That is, in a conventional semiconductor device, a diffusion layer is formed on a semiconductor substrate, a window for leading out an electrode is formed in an insulating film on the semiconductor substrate, and a high melting point metal layer is formed between this diffusion layer and a main wiring metal layer. This high melting point metal layer has the role of completely inhibiting mutual diffusion between the main wiring metal layer and the St in the diffusion layer, and at the same time fixes the main wiring metal layer to the insulating film and the diffusion layer. .
また、この高融点金属層とその上の主配線金属層との積
層からなる金属配線は絶縁膜上を引き延ばされ、同時に
ポンディングパッドを形成している。このポンディング
パッドは絶Ｒ膜と高融点金属層とが接する構造であり、
高融点金属層とじて粘着性の高い材料を使用しているも
のの、一般的な半導体装置に使用している。Ｕ膜などに
比べて密着性が劣る。Further, a metal wiring made of a laminated layer of this high melting point metal layer and a main wiring metal layer thereon is stretched over an insulating film, and at the same time forms a bonding pad. This bonding pad has a structure in which the absolute R film and the high melting point metal layer are in contact with each other,
Although a highly adhesive material is used for the high melting point metal layer, it is used in general semiconductor devices. Adhesion is inferior to U film etc.
このため、ポンディングパッドにワイヤデンディングし
ようとすると、がンディング時のエネルギによって、ノ
クツド部分の配線が剥離すると云う不良が発生し、半導
体装置の組立歩留やを低下させる欠点があった。For this reason, when wires are attached to the bonding pads, the energy generated during bonding causes defects such as peeling of the interconnects at the bonding pads, which has the disadvantage of lowering the assembly yield of semiconductor devices.
また、この密着性を改善する手段として、高融点金属層
とその上の主配線金属層とで眉間絶縁膜全形成し、この
眉間絶縁膜上にスルーホール′ｔ−あけた後Ａｔ膜でポ
ンディングパッドを形成することも提案されている。In addition, as a means to improve this adhesion, the entire glabellar insulating film is formed using a high melting point metal layer and the main wiring metal layer thereon, and after a through hole is made on the glabellar insulating film, an At film is used to form a through hole. It has also been proposed to form a padding pad.
負かし、この場合のポンディングパッドは半導体基板上
の絶縁膜とｋＬ膜との間に層間絶縁膜を新たに形成する
必要があるなど、工程が複雑でちゃ、歩留りを低下させ
る原因となっていた。On the other hand, the bonding pad in this case required a new interlayer insulating film to be formed between the insulating film on the semiconductor substrate and the kL film, which caused a drop in yield if the process was complicated. .
この発明は、上記従来の欠点を除去するためになされた
もので、簡単な工程でがンディングパッドの密着性を向
上させ、信頼性および歩留りの向上を期することのでき
る半導体装置の製造方法を提供することを目的とする。The present invention was made in order to eliminate the above-mentioned conventional drawbacks, and provides a method for manufacturing a semiconductor device that improves the adhesion of a bonding pad through a simple process and improves reliability and yield. The purpose is to provide.
以下、この発明の半導体装置の製造方法の実施例につい
て図面に基づき説明する。第１図（ａ）ないし第１図（
ｅ）はその一実施例の工程説明図である。Embodiments of the method for manufacturing a semiconductor device of the present invention will be described below with reference to the drawings. Figure 1(a) to Figure 1(
e) is a process explanatory diagram of one example.
まず、第１図（ａ）に示すように、公知の方法によシ、
半導体基板ｌ上に拡散層１１を形成した後、この半導体
基板１上の５ｉ０２Ｊｌｔ（２に電極引出し用のコンタ
クト窓１２を形成し、このコンタクト窓１２に白金シリ
サイド層１３を形成する。First, as shown in FIG. 1(a), by a known method,
After forming a diffusion layer 11 on a semiconductor substrate 1, a contact window 12 for leading out an electrode is formed in 5i02Jlt (2) on this semiconductor substrate 1, and a platinum silicide layer 13 is formed in this contact window 12.
この白金シリサイド層１３はたとえば、半導体基板１上
の全面に白金を蒸着またはスパッタ法で５０ＯＡの厚さ
に被着した後、約５００℃の不活性雰囲気中で熱゛処理
を行うことｒｊ：υ形成される。This platinum silicide layer 13 is formed by, for example, depositing platinum on the entire surface of the semiconductor substrate 1 to a thickness of 50 OA by vapor deposition or sputtering, and then performing heat treatment in an inert atmosphere at about 500°C. It is formed.
このとき、Ｓ １０２Ｊｌａ Ｚ上の未反応の白金は王
水で除去する。At this time, unreacted platinum on S 102Jla Z is removed with aqua regia.
次に、第１図（ｂ）に示すように、全面に高融点金属層
３、たとえば、Ｔｉ 、Ｍｏ 、 Ｗあるいはこれらの
２層構造や合金層を蒸着またはスパッタ法で形成する。Next, as shown in FIG. 1(b), a high melting point metal layer 3, such as Ti, Mo, W, or a two-layer structure or alloy layer thereof, is formed on the entire surface by vapor deposition or sputtering.
この高融点金属層３はこの上に形成される主配線金属層
であるＡｔがその後の熱処理によりコンタクト窓１２を
介してシリコンと相互拡散して接合を破壊するのを防ぐ
ために形成するものであり、信頼性、再現性の面から１
０００〜２０００Ａの厚さが必要である。This high melting point metal layer 3 is formed to prevent At, which is the main wiring metal layer formed thereon, from interdiffusing with silicon through the contact window 12 during subsequent heat treatment and destroying the junction. 1 from the viewpoint of reliability and reproducibility.
A thickness of 000-2000A is required.
次いで、高融点金属）ｉ４３と同様の方法でこの高融点
金属層３上に約２００ ＯＡのＡｔ膜４を形成して積層
構造の金属層を形成する。このＡ２膜４は主として、活
性なＴｉなどの高融点金属層３の酸化防止あるいは高融
点金属層３をパターニングする際の保護膜として用いる
。Next, an At film 4 of approximately 200 OA is formed on the high melting point metal layer 3 in the same manner as the high melting point metal (i43) to form a laminated metal layer. This A2 film 4 is mainly used to prevent oxidation of the high melting point metal layer 3 such as active Ti or as a protective film when patterning the high melting point metal layer 3.
次に、通常のホトリソ工程でレジストマスクとしてＡ／
４ｊ＠４をエツチングし、レジストを除去した後、）Ｌ
膜４をマスクとして高融点金属／１ｌｉ３を、Ａｔ膜４
をエツチングしない方法、たとえば、フレオン系のガス
プラズマエッチ法によりエツチングして、第１図（ｂ）
に示すように、コンタクト窓１２およびコンタクト窓１
２０周辺部を覆うようにパターニングする。Next, A/
After etching 4j@4 and removing the resist, )L
Using film 4 as a mask, high melting point metal/1li3 is applied to At film 4.
1(b).
As shown, contact window 12 and contact window 1
Patterning is performed so as to cover the periphery of No. 20.
これにより、コンタクト部以外はすべてエツチングで除
去される。このとき、レジス）を残したままＡｔ膜４と
高融点金属層３ｆ、続けてエツチングし、その後レジス
）を除去してもよい。また、Ａｔ膜４の代わシに、Ａｔ
−８ｔ膜を使用してもよい。As a result, everything except the contact portion is removed by etching. At this time, the At film 4 and the high melting point metal layer 3f may be etched successively while leaving the resist (resist), and then the resist (resist) may be removed. Moreover, instead of the At film 4, At
-8t membrane may also be used.
次に、第３図（ｃ）に示すように、全面に再度Ａｔ模膜
４ａｉ蒸
さに形成し、第３図（ｄ）に示すように、Ａｔ膜４と接
しかつ覆うように、Ｍ膜４ａをパターニングして電極配
線を形成し、ポンプイングツ９ツド２０を引き出してお
く。Ａｔ膜４ａは従来の電気良導体としての役割を果す
。Next, as shown in FIG. 3(c), a vaporized At film 4a is again formed on the entire surface, and as shown in FIG. 3(d), an M film 4a is formed so as to contact and cover the At film 4. is patterned to form electrode wiring, and the pumping tube 9 is pulled out. The At film 4a serves as a conventional good electrical conductor.
最後に、第１図（ｅ）に示すように、パッシベーション
膜５’（（ＣＶＤ法で形成し、ホトエツチングにより、
パターニングし、半導体装置を完成する。Finally, as shown in FIG. 1(e), a passivation film 5' ((formed by CVD method,
Patterning is performed to complete the semiconductor device.
以上説明したように、第１の実施例の電極配線構造にお
いては、コンタクト窓１２の部分以外の大部分の配線が
密着性のよい５ｉＯｚ膜２とＡｔ膜４ａとの接合で構成
されているため、ボンディング・ぞラド２０の密着性は
著しく改善でき、ワイヤボンディング時の衝撃および応
力に対して剥離するととなく、半導体装置の組立て歩留
シおよび信頼性の向上を図ることができる。As explained above, in the electrode wiring structure of the first embodiment, most of the wiring other than the contact window 12 is composed of a bond between the 5iOz film 2 and the At film 4a, which have good adhesion. The adhesion of the bonding pad 20 can be significantly improved, and it will not peel off due to impact and stress during wire bonding, and the assembly yield and reliability of semiconductor devices can be improved.
また、電極配線形成工程における熱応力などによる高融
点金属層の浮き上がりゃ、剥離などは減少し、半導体装
置の製造歩留ｐｔ内向上る。Further, lifting and peeling of the high melting point metal layer due to thermal stress or the like in the electrode wiring formation process is reduced, and the manufacturing yield of semiconductor devices is improved within pt.
さらに、従来の半導体装置における中間絶縁膜を形成す
る工程が省略できることになり、工程の短縮ならびに製
造歩留υが向上すると云う、効果を生じる。Furthermore, the process of forming an intermediate insulating film in the conventional semiconductor device can be omitted, resulting in the effects of shortening the process and improving manufacturing yield υ.
次に、この発明の第２の実施例について説明する。上記
第１の実施例では、コンタクト窓１２およびコンタクト
窓１２の周辺部を覆うように高融点金属層およびＡｔ膜
４をエツチングしてパターン形成すると説明したが、第
２図（ａ）に示すように、この工程では、配線ノ＋ター
ンの形成を行わず、ポンディングパッド部のみ高融点金
属層３およびＡｔ膜４′ｆｃエツチングして除去した後
、第１の実施例と同様の方法で、全面にＡｔ膜４ａを被
着させ、レジストをマスクとしてＡｔ膜４ａおよびＡｔ
膜４、次いでＡ７１．膜４ａｉマスクとして、高融点金
属層３のエツチングを行ない、電極配線を形成すると、
デンディングパッド部のみが絶縁膜、すなわち、ＳｊＯ
。Next, a second embodiment of the invention will be described. In the first embodiment, it was explained that the high melting point metal layer and the At film 4 are patterned by etching to cover the contact window 12 and the periphery of the contact window 12, but as shown in FIG. 2(a), In this step, the wiring no+turns were not formed, and only the high melting point metal layer 3 and the At film 4'fc were removed by etching, and then the same method as in the first embodiment was carried out. An At film 4a is deposited on the entire surface, and the At film 4a and At
Membrane 4, then A71. When the high melting point metal layer 3 is etched as a film 4ai mask and electrode wiring is formed,
Only the denting pad part is an insulating film, that is, SjO
.
膜２とＡＬＬ１２が接する構造となる。The structure is such that the film 2 and ALL 12 are in contact with each other.
したがって、この第２の実施例においては、ポンディン
グパッドは密着力のよいＡｔ膜４ａと５ｉｎｔ膜２とが
接触する構造であるので、組立て歩留りおよび信頼性が
向上でき、また、ボンディング／９ツド部以外の素子領
域内の配線は１回のホトエツチング工程で形成される。Therefore, in this second embodiment, the bonding pad has a structure in which the At film 4a and the 5-int film 2, which have good adhesion, are in contact with each other, so that the assembly yield and reliability can be improved, and the bonding/9. Wiring in the element region other than the area is formed by one photoetching process.
これにより、配＃ｊ！パターンが２重形成とならず、コ
ンタクト窓１２に対する配線の合わせ余裕が減少できる
ため、パターンの縮小化が図れる。As a result, distribution #j! Since the pattern is not formed twice and the margin for alignment of the wiring with respect to the contact window 12 can be reduced, the pattern can be reduced in size.
なお、この発明は１層配線構造に限定されるものではな
く、°多層配線構造にも適用できる。Note that the present invention is not limited to a single layer wiring structure, but can also be applied to a multilayer wiring structure.
以上のように、この発明の半導体装置の製造方法によれ
ば、拡散層を有する半導体基板上の絶縁膜にコンタクト
窓を形成した後、半導体基板上に高融点金属層と電極配
線層との積層構造の金属層を形成した後、再度電極配線
を半導体基板上に絶縁膜？介することなく形成し、この
電極配線を・やターン形成してボンデイングパッド部分
および積層構造の金属層間の相互配線を形成するように
したので、層間絶縁膜の形成やスルーホールの形成など
、複雑な工程を必要とせず、簡単な工程にできるととも
に、ポンプイングツぐラドの密着性全向上させることが
できるばかりか、信頼性および歩留ジの向上が可能とな
る利点を有する。As described above, according to the method for manufacturing a semiconductor device of the present invention, after forming a contact window in an insulating film on a semiconductor substrate having a diffusion layer, a high melting point metal layer and an electrode wiring layer are laminated on the semiconductor substrate. After forming the metal layer of the structure, connect the electrode wiring again to the insulating film on the semiconductor substrate. This electrode wiring is formed in a slight turn to form bonding pad portions and interconnections between metal layers in a laminated structure, making it possible to form complex interlayer insulating films and through-holes. This method has the advantage that it does not require any steps, can be made into a simple process, can completely improve the adhesion of the pumping pad, and can also improve reliability and yield.
第１図（ａ）ないし第１図（ｅ）はそれぞれこの発明の
半導体装置の一実施例を説明するための工程説明図、第
２図（ａ）および第２図（ｂ）はそれぞれこの発明の半
導体装置の製造方法の他の実施例を説明するための工程
説明図である。
１・・・半導体基板、２・・・５ｉ０２膜、３・・・高
融点金属層、４，４ａ・・・ＡｔＭ、５ ・・パッシベ
ーション膜、１１・・・拡散層、１２・・・コンタクト
窓、１３・・・白金シリサイド層、２０・・・ポンディ
ングパッド。
−２２′
手続補正書
昭和５８年５月１８日
特許庁長官若 杉 和 夫殿
１、事件の表示
昭和５７年 ％ 許 願第 １６０８４１ 号２、
発明の名称
半導体装置の製造方法
３、補正をする者
事件との関係 特 許 出願人（０２９）沖電
気工業株式会社
４、代理人
５、補正命令の日付 昭和 年 月 日 （自
発）６、補正の対象
明細省の発明の詳細な説明の欄
２２９−1(a) to 1(e) are process explanatory diagrams for explaining one embodiment of the semiconductor device of the present invention, and FIG. 2(a) and FIG. FIG. 3 is a process explanatory diagram for explaining another embodiment of the method for manufacturing the semiconductor device of FIG. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... 5i02 film, 3... High melting point metal layer, 4, 4a... AtM, 5... Passivation film, 11... Diffusion layer, 12... Contact window , 13...Platinum silicide layer, 20...Ponding pad. -22' Procedural amendment May 18, 1980 Kazuo Wakasugi, Commissioner of the Patent Office 1, Indication of the case 1981 Permit Application No. 160841 2,
Name of the invention Method for manufacturing semiconductor devices 3 Relationship with the case of the person making the amendment Patent Applicant (029) Oki Electric Industry Co., Ltd. 4 Agent 5 Date of amendment order Showa Year Month Day (Spontaneous) 6 Amendment Column 229- Detailed explanation of the invention of the Ministry of Subject Specifications
Claims (1)
ともにこの拡散層上に電極引出し用のために上記絶縁膜
にコンタクト窓を形成する工程と、高融点金属層と電極
配線とからなる積層構造の金属層を上記半導体基板上に
形成する工程と、絶縁膜を介することなく上記積層構造
の金属を有する上記半導体基板上に再度電極配線全形成
する工程と、この再度形成された電極配線全パターン形
成してポンディングパッド部分および上記積層構造の金
属層間の相互配線を形成する工程とからなる半導体装置
の製造方法。After forming a diffusion layer on a semiconductor substrate, forming an insulating film and forming a contact window in the insulating film for leading out an electrode on this diffusion layer, and laminating a layer consisting of a high melting point metal layer and an electrode wiring. a step of forming a metal layer of the structure on the semiconductor substrate, a step of forming all the electrode wiring again on the semiconductor substrate having the metal of the laminated structure without interposing an insulating film, and a step of forming all the electrode wiring formed again on the semiconductor substrate having the metal of the laminated structure without intervening an insulating film. A method for manufacturing a semiconductor device comprising the steps of forming a pattern to form a bonding pad portion and interconnections between metal layers of the laminated structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57160841A JPS5950546A (en) | 1982-09-17 | 1982-09-17 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57160841A JPS5950546A (en) | 1982-09-17 | 1982-09-17 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5950546A true JPS5950546A (en) | 1984-03-23 |
Family
ID=15723559
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57160841A Pending JPS5950546A (en) | 1982-09-17 | 1982-09-17 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5950546A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH022131A (en) * | 1988-06-13 | 1990-01-08 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPH02143531A (en) * | 1988-11-25 | 1990-06-01 | Hitachi Ltd | Semiconductor device |
-
1982
- 1982-09-17 JP JP57160841A patent/JPS5950546A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH022131A (en) * | 1988-06-13 | 1990-01-08 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPH02143531A (en) * | 1988-11-25 | 1990-06-01 | Hitachi Ltd | Semiconductor device |
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