JPS5947766A - Insulated gate type semiconducor device and manufacture thereof - Google Patents
Insulated gate type semiconducor device and manufacture thereofInfo
- Publication number
- JPS5947766A JPS5947766A JP57156655A JP15665582A JPS5947766A JP S5947766 A JPS5947766 A JP S5947766A JP 57156655 A JP57156655 A JP 57156655A JP 15665582 A JP15665582 A JP 15665582A JP S5947766 A JPS5947766 A JP S5947766A
- Authority
- JP
- Japan
- Prior art keywords
- type
- type region
- gate
- polycrystalline
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 18
- 239000012535 impurity Substances 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 6
- 230000005669 field effect Effects 0.000 claims description 4
- 238000004321 preservation Methods 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims 2
- 230000004308 accommodation Effects 0.000 claims 1
- 230000008878 coupling Effects 0.000 claims 1
- 238000010168 coupling process Methods 0.000 claims 1
- 238000005859 coupling reaction Methods 0.000 claims 1
- 238000005530 etching Methods 0.000 claims 1
- 230000005284 excitation Effects 0.000 claims 1
- 239000002184 metal Substances 0.000 claims 1
- 239000003921 oil Substances 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 abstract description 8
- 238000001259 photo etching Methods 0.000 abstract description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract description 3
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 3
- 239000011574 phosphorus Substances 0.000 abstract description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052782 aluminium Inorganic materials 0.000 abstract description 2
- 229910052796 boron Inorganic materials 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract description 2
- 238000005468 ion implantation Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 10
- 108091006146 Channels Proteins 0.000 description 9
- 230000015556 catabolic process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7808—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a breakdown diode, e.g. Zener diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Protection Of Static Devices (AREA)
- Amplifiers (AREA)
Abstract
Description
【発明の詳細な説明】
本発明１は一つの半導体基体上にｐチャネルＭ０ＳＦｍ
Ｔ（絶縁ゲート形電界効果トランジスタ）とその保護ダ
イオード紮有する半導体装置に関する。Detailed Description of the Invention The present invention 1 provides a p-channel M0SFm on one semiconductor substrate.
The present invention relates to a semiconductor device having a T (insulated gate field effect transistor) and its protective diode.
筒出力ＭＯ８ＦＦｉＴとして、ドレインとなるｎ型シリ
コン基＆衣面にｐ型領域ケ設け、このｐ型領域の一部に
ｎ４−型領域を設けてソースとなし、ソースの設けらｎ
ないｐ型領域表１７ｉｉに薄い酸化膜を弁してゲート電
極全没け、このゲート電極への電圧印加によってソース
・ドレイン間のｐ型領域表面のチャネル電流音制御する
ｎチャネル縦形Ｍ０８１１ＰＥＴにおいて、外部サージ
電圧から薄いゲート絶縁膜ｒ保餓するために基板の１１
０部衣面上にＮい絶縁膜ミオして多結晶シリコン層ヶ形
成し、この多結晶層に選択的不純物拡散によるｎ ｐ
ｎ接合ダイオード全膜設て前記ＭＯ８ＦＥＴのゲート・
ソース間に接続する構造は既に本願出願人により提案さ
几ているところである。As a cylinder output MO8FFiT, a p-type region is provided on the n-type silicon base and coating surface that becomes the drain, an n4- type region is provided in a part of this p-type region to serve as a source, and the source is provided with an n-type region.
In the n-channel vertical M0811PET, a thin oxide film is placed on the p-type region without the gate electrode to completely submerge the gate electrode, and by applying a voltage to this gate electrode, the channel current on the surface of the p-type region between the source and drain is controlled. 11 of the substrate to protect the thin gate insulating film from surge voltage.
A polycrystalline silicon layer is formed by forming an N insulating film on the surface of the substrate, and Np is formed by selective impurity diffusion into this polycrystalline layer.
The gate of the MO8FET is equipped with an n-junction diode throughout the film.
A structure for connecting sources has already been proposed by the applicant.
上記拾遺によ１１ば、上記ｎ ｐｎ ハック・ツー
φバンク接合ダイオードはｎチャネルＭＯ８ＦＩ！；Ｔ
のｎ＋型ソース拡散工程を兼用させることで比較的にＢ
〕＋なプロセスで得ることができ、そ１１による保穫効
果ｔユ太きｂことが認めらｎ、る。しかし多結晶シリコ
ン層によるバックφンー・バンク接合ダイオードに関し
ては、ｎｐｎ 型よシもｐ＋ｎｐ″−型の方が尾、答
が速いことが実験的により判明した。そこで前記のｎチ
ャネルＭＯ８ＦＬ！！Ｔにｐ”ｎｐ＋型（３１，＃にダ
イオード？接続したもの？一つの半導体基体上に形成し
ようとする場合、ｎ 型ソース拡散工程奮タ゛イオード
形成に利用するわけには行かず、ｐｒｌｐ 接合形成
のためにｌ［たにｐ＋マスク拡散工程ｒ追加する必要が
あシその結果製造プロセスが極めて復雑化することにな
った。According to item 11 above, the n pn hack-to-φ bank junction diode is an n-channel MO8FI! ;T
By combining the n+ type source diffusion process, B
] It can be obtained by a positive process, and it is recognized that the preservation effect due to this method is increased. However, for back φ-bank junction diodes made of polycrystalline silicon layers, it has been experimentally found that the p+np''- type has a faster response time than the npn type.Therefore, the above-mentioned n-channel MO8FL!!T When trying to form a p"np+ type (diode connected to 31,#) on one semiconductor substrate, the n-type source diffusion process cannot be used to form the diode, and is used to form the prlp junction. In addition, it was necessary to add a p+ mask diffusion step to the method, and as a result, the manufacturing process became extremely complicated.
本願発明者は上記した問題にかんがみて、従来あｌシか
えりみらｉｔ、なかったｐチャネルＭＯ８ＦＥＴの保麟
素子としてｐ ｎｐ 接合ダイオード？接続すること
に着目した。したがって本発明の目的は製造プロセスが
簡単であってゲート保睡効果の丁ぐｎた保膿素子付きパ
ワーＭＯ８ＦＥＴを提供することにある。In view of the above-mentioned problems, the inventors of the present application have decided to use a pnp junction diode as a protective element for a p-channel MO8FET, which was not available in the past. We focused on connecting. Therefore, an object of the present invention is to provide a power MO8FET with a storage element that has a simple manufacturing process and has a gate storage effect.
以下本発明を適用した一笑施列とじでｐチャネルパワー
Ｍ ＯＳ Ｗ ＦＩ Ｔの構造プロセスの各工程に従っ
て詳述する。Each step of the structural process of a p-channel power MOSFET to which the present invention is applied will be described in detail below.
（１）第１席１全参照し高比抵抗ｐ型シリコン単結晶基
ｖｉｌ奮用意し、酸化性雰囲気中で表面を熱酸化して厚
い（５０００〜８０００Ａ ）酸化１ｍ（８１ｏｚ）膜
２全形厄した後、この犀い酸化膜２の一部を選択エッチ
【４．て基板１の表面全露出し、その後熱酸化（ゲート
酸化）により薄い（通常１３００Ａ程度）ゲート酸化膜
３′ｆ：形成する。(1) Refer to the first seat 1 and prepare a high resistivity p-type silicon single crystal base vil, and thermally oxidize the surface in an oxidizing atmosphere to form a thick (5000-8000A) oxidized 1m (81oz) film 2. After cleaning, selectively etch a part of this thin oxide film 2 [4. The entire surface of the substrate 1 is exposed, and then a thin (usually about 1300 Å) gate oxide film 3'f is formed by thermal oxidation (gate oxidation).
（２） シリコン化合物の熱分解等の方法に、ｃシ全
面にシリコン勿堆積して第２図に示すように多結晶シリ
コン層４奮形成する。この後全面にＰ（リン）不純物イ
オン打込みによシ多結晶シリコン＝２ｎ型化する。この
場合必要とするゲート保砕素子の耐圧によってＰ打込み
量？コントロール（例えば打込ミエネルギ： １２５に
８Ｖ、 表面不純物＃／ｆｆ：１０ｓ ２〜１０１ ’
ａｔＯｍ８ ｃＡ ）する。(2) Using a method such as thermal decomposition of a silicon compound, silicon is deposited on the entire surface of the substrate to form a polycrystalline silicon layer as shown in FIG. Thereafter, P (phosphorus) impurity ions are implanted into the entire surface to make polycrystalline silicon=2n type. In this case, the amount of P implanted depends on the required voltage resistance of the gate crushing element? Control (e.g. implant energy: 125 to 8V, surface impurity #/ff: 10s 2~101'
atOm8 cA).
（３）第３図に示すようにチャネル部全露出するための
ホトエッチ７行なう。(3) As shown in FIG. 3, photoetching 7 is performed to fully expose the channel portion.
（４）Ｐ（ＩＪン）イオン打込み、拡散葡行ない氾番図
で示すようにチャネル部となるｎ型領域５全自己整合的
に形成する、なお、多結晶シリコン層へのＰイオン打込
みにこの工程で行なってもよい。(4) P (IJ) ion implantation and diffusion As shown in the diagram, the n-type region 5 that will become the channel part is formed in a fully self-aligned manner. It may be performed in the process.
（５）全面にＬＴＰ（低温生成酸化）膜６ケ第５図のよ
うに形成する。(5) Six LTP (low temperature generated oxidation) films are formed on the entire surface as shown in FIG.
（６） ホトエッチによシ一部紮除去して残ったＬＴ
Ｐ）漠６ケマスクとしてＢ（ボロン）不純物ケ商濃度に
デポジット乃至拡散することにより第６図に示すように
チャネル部の一部にソースとなるｐ＋型伸域７紮形成す
るとともに多結晶シリコン層の露出するｉＨ１分８ｋｐ
″”型化し、マスク３１１．７ｔｎ型部分との間にｐ＋
ｎｐ＋接合ケ得接合
ケア） この後、第７図に示すように層間絶縁膜９と
してＰ２Ｏ（リン・シリケートガラス）又にポリイミド
糸待（脂葡形成し、コンタクトホトエッチ後、アルミニ
ウムケ密Ｎ（又はスパッタ）し、ｐ″−ｎｐ＋接合の一
方１ｊ、ｌＩのｐ＋型多結晶シリコン層に接続するソー
ス電極（配Ｉｖｊり１０と池万側のｐ＋型多結晶シリコ
ン層８に接続するゲート電極（同図でに実線の配線とし
て示（７てめる）１１−形成する。(6) Remaining LT after partially removing the ligature by photoetching
P) By depositing or diffusing B (boron) impurity as a mask to a high concentration, a p+ type extension region 7 which becomes a source is formed in a part of the channel part as shown in FIG. 6, and a polycrystalline silicon layer is formed. iH exposed 1 minute 8kp
``'' type, and between the mask 311.7tn type part and the p+
After that, as shown in FIG. 7, an interlayer insulating film 9 is formed using P2O (phosphorus silicate glass) or polyimide thread, and after contact photoetching, an aluminum film is formed. or sputtering), and a source electrode connected to the p+ type polycrystalline silicon layer 1j and lI on one side of the p''-np+ junction (layer 10) and a gate electrode connected to the p+ type polycrystalline silicon layer 8 on the side of the p''-np+ junction. In the figure, the wiring shown as a solid line (point 7) 11- is formed.
なお、ゲート保護ダイオードはｐ ｎｐ ｋ基本と
じてこｆｌ’ｚＮ個直列に接続することによってＮ倍の
耐圧ゲイ（）ることができる。It should be noted that the gate protection diode can be increased in breakdown voltage by N times by connecting p np k basic gates fl'zN pieces in series.
第８図は上記プロセスによル製造さｔｌ、たｐチャネル
ＭＯ８ＦＥＴとそのゲート保Ｈφダ・イオードの動作原
理ケ説明するためにモデル化した図で第９図はその等価
回路図である。同図に示すようにｐチャネルＭＯ８ＦＥ
Ｔとしてはドレイン側となるｐ型基板ｌとソースｐ 型
領域７とに挾’Ｅｊ１．７ｔ、ｎ型領域表面がチャネル
部５ａとなってゲート（ａ）への電圧印加によって上記
チャネル部における一ＴＥＩＤ Ｃソース・ドレイン電
流）がｆｌｔｌＪ １１δれ、ゲート（Ｇ）とソース（
８）との間に介挿８れ足長結晶シリコン層からなるバッ
ク拳ツー〇バック構造のｐ ｎｐ ダイオードがＩＭ
、＃！にダイオードとしてＭＯ８ＦＥＴ？外部ＦＥＴ型
圧からゲート絶縁膜２保膿する。このような保護ダイオ
ードがない場合薄いゲート酸化膜３の静電破壊強度が低
く、取扱いによる破壊が生じたが、上記のような保賎ダ
イオードを接続することで静電破壊に対する耐性が大き
くなった。！侍に多結晶シリコンのｐｎ接合を用いた作
、Ｉ灸ダイオードの場合、ｎ＋ ｐｎ十型の場合よシも
ｐ ｎｐ 型の方が応答が速いため静市、破壊強度
レベルが同上した。例えば静菖容ｊ＃Ｃ＝２００ ｐ
Ｆでの破壊テストでｅよ約１．５〜２倍に向上した。FIG. 8 is a modeled diagram for explaining the operating principle of a p-channel MO8FET manufactured by the above process and its gate protection Hφ diode, and FIG. 9 is an equivalent circuit diagram thereof. As shown in the figure, p-channel MO8FE
As T, there is a gap between the p-type substrate l on the drain side and the source p-type region 7, and the surface of the n-type region becomes the channel part 5a, and by applying a voltage to the gate (a), one part in the channel part is TEID C source/drain current) is fltlJ 11δ, and the gate (G) and source (
8) A pnp diode with a back fist-to-back structure consisting of a long crystalline silicon layer inserted between the IM
, #! MO8FET as a diode? The gate insulating film 2 is impregnated from external FET type pressure. Without such a protection diode, the electrostatic breakdown strength of the thin gate oxide film 3 was low and damage occurred due to handling, but by connecting the protection diode as described above, resistance to electrostatic breakdown increased. . ! In the case of an I moxibustion diode made using a pn junction of polycrystalline silicon, the response of the pnp type was faster than that of the n+pn ten type, so the breakdown strength level was the same as above. For example, Shizukayo j #C = 200 p
In the destructive test with F, it was improved by about 1.5 to 2 times compared to e.
本発明ＶＣよればｐ ” ｎ ｐ＋接合ダイオード紫ｐ
チャネルハヮーＭＯ８ＦＥＴと同じ基体上に形成するも
のであって、ｐチャネルパワーＭ ＯＳ Ｆ ＥＴの製
造プロセスにおいてｎ型チャネル部拡散工程とｐ 型ソ
ース拡散工程全その１１利用丁ｔ’Ｌばνｒｆｃに工程
葡追加することなくゲート保譲素子の挿入が可能でるる
。According to the VC of the present invention, p ” n p+ junction diode purple p
It is formed on the same substrate as the channel power MOSFET, and in the manufacturing process of the p-channel power MOSFET, the n-type channel part diffusion process and the p-type source diffusion process are all used. It is possible to insert a gate protection element without adding anything.
本発明はパワーＭＯＥＩＦＥＴ、詩にｐチャネルパワー
ＭＯ８Ｆ１！ｉＴの全てに１６用して有効である。The present invention is a power MOEIFET, a p-channel power MO8F1! It is effective to use 16 for all iT.
第１図乃至第７図は本発明ｋｐチャネルパワーＭＣＪＥ
ＪＦＥＴの製造プロセスに通用した場合の一実ＭｆＪ列
全示す上極断面図でるる。
第８図は本発明によるｐ＋” ｐ＋Ｊｌｊ（ｉタイオー
ド付きｐチャネルパワーＭＯ日Ｆ ｍ Ｔ （１）動作
原理葡説明するＦめの（・莫型酊「面図、
第９図ｔよ第８図に等ｆｌｌｉの回路図である。
１・・・ｐ型シリコン基板（ドレイン）、２・・・Ｊ’
Ｊい酸化膜、３・・・辿い酸化膜（ゲート酸化膜）、４
・・・多結晶シリコン層、５・・・チャネル部ｎ型領域
、６・・・Ｌ Ｔ Ｐ膜、７・・・ソースル＋副領域、
８・・・ｐ 型化した多結晶シリコンノ醋、９・・・層
間絶紅膜、１０・・ソース電極（配線）、１１・・・ゲ
ート電極（配線）。
２９
第 １ 図
第 ２ 図
第 ３ 図
第 ４ 図
第 ５ 図
第 ７ 図Figures 1 to 7 show the kp channel power MCJE of the present invention.
This is a cross-sectional view of the upper pole showing the entire MfJ array when it is applied to the JFET manufacturing process. Fig. 8 shows the p+"p+Jlj(i diode-equipped p-channel power MOF m T (1) operation principle according to the present invention. It is a circuit diagram of the same flli. 1...p-type silicon substrate (drain), 2...J'
J oxide film, 3...Tracing oxide film (gate oxide film), 4
... Polycrystalline silicon layer, 5... Channel part n-type region, 6... LTP film, 7... Source + sub region,
8... P-type polycrystalline silicon base, 9... Interlayer insulation film, 10... Source electrode (wiring), 11... Gate electrode (wiring). 29 Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 7
Claims (1)
尋体基体表面の一部にｎ四半Ｓ体領域３〔設け、このｎ
型領域の表面の一部にｐ 型領域を設けてソースとなし
、ｐ 型領域の設けられないｎ型領域の表面に瀞す絶縁
膜を弁し１り−１・’ｊｌＬ極奮設け、このケート電極
への電圧印加によってソース・ドレイン間のｎ型領域表
面のチャネル電流を制御する絶縁ゲート電界効果トラン
ジスタ奮イｆＬ、この絶縁り゛−ト亀界効果トランジス
タの形成８１″Ｌｆｔ、いｐ型半辱体基体の油部表面に
賄い絶ｆ萱ｌ良を弁して多結晶半導体層を形成し、この
多結晶半導体層ｒ（ｐ″ｒｎ ｐ−’−接接合収設”ｉ
： Ｆ７ｉＪ記Ｍ Ｏｆ３ ’Ｍ ｙ、Ｉ、 ＵＮＩ掛
５ンジスタのゲート保Ｉ用ダイオードとして接続したこ
と全特徴とするＰ３縁ゲート形半専体装匝。 ２、ｐ型シリコン基板上の一部にｊｌいシリコン酸化膜
ｔ、１１０都に薄−シリコン酸化膜を形成する］−程、
その上全面にシリコン全堆積して多結晶シリコン／ｉＪ
’（ｒ形成する工程、薄い酸化膜とその上の多結晶シリ
コン層を部分的にエッチして基板の一部盆露出する工程
、ドナ不純物を導入することによシシリコン基板の露出
する部分の表面にｎ型領域全形成するとともに多結晶シ
リコン層′ｔ−ｎ型化する工程、ｎ型領域及び多結晶シ
リコン層の表面の一部全マスクして高濃度アクセプタ不
純′吻全導入することによ５ｎ型領域の表面の一部にｐ
型領域全形成するとともに多結晶シリコン層にｐｎｐ
＋接合全形成する工程とｔ！ Ｌ、上記ｐ型基板全ドレ
インとし、ｐ＋型領領域ソースとし、ソース・ドレイン
に挾まれたｎ型領域上の多結晶層ｒゲートとする絶縁ゲ
ート形電界効果トランジスタ金構厄するとともに上記ｐ
ｎｐ 結合ケ上記絶縁ゲート形電界効果トランジ
スタのゲート保設ダイオードとして接続することヲ爵留
とする絶縁ゲート形半導体装置の製造法。[Scope of Claims] 1. As a p-type half-body substrate excitation drain, an n-quadrant S-body region 3 is provided on a part of the surface of this p-type ten-half body substrate;
A p-type region is provided on a part of the surface of the type region to serve as a source, and an insulating film is provided on the surface of the n-type region where no p-type region is provided. An insulated gate field effect transistor that controls the channel current on the surface of an n-type region between the source and drain by applying a voltage to the gate electrode is formed. A polycrystalline semiconductor layer is formed on the surface of the oil part of the semi-abrasive body base, and this polycrystalline semiconductor layer r(p"rn p-' - junction accommodation"i)
: F7iJ M Of3 'My, I, P3 edge gate type semi-dedicated box, which is connected as a gate protection diode for a 5-unit UNI transistor. 2. Form a thin silicon oxide film on a part of the p-type silicon substrate and a thin silicon oxide film on 110 parts.
On top of that, silicon is completely deposited on the entire surface and polycrystalline silicon/iJ
'(r forming process, partially etching the thin oxide film and the polycrystalline silicon layer thereon to expose a portion of the substrate, introducing donor impurities into the surface of the exposed part of the silicon substrate) In this step, the entire n-type region is formed and the polycrystalline silicon layer is made into a t-n type.The n-type region and the surface of the polycrystalline silicon layer are partially masked and a high concentration acceptor impurity is completely introduced. P on part of the surface of the 5n type region
While forming the entire mold region, PNP is applied to the polycrystalline silicon layer.
+Process of forming all the joints and t! L, an insulated gate field effect transistor metal structure in which the p-type substrate is the entire drain, the p + type region is the source, and the polycrystalline layer r gate is on the n-type region sandwiched between the source and drain;
A method of manufacturing an insulated gate type semiconductor device in which the np coupling is connected as a gate preservation diode of the above insulated gate type field effect transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57156655A JPS5947766A (en) | 1982-09-10 | 1982-09-10 | Insulated gate type semiconducor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57156655A JPS5947766A (en) | 1982-09-10 | 1982-09-10 | Insulated gate type semiconducor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5947766A true JPS5947766A (en) | 1984-03-17 |
Family
ID=15632397
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57156655A Pending JPS5947766A (en) | 1982-09-10 | 1982-09-10 | Insulated gate type semiconducor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5947766A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01280359A (en) * | 1988-05-06 | 1989-11-10 | Fuji Electric Co Ltd | Insulated-gate type semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5345978A (en) * | 1976-10-08 | 1978-04-25 | Hitachi Ltd | Insulated-gate-protective semiconductor device |
| JPS5664465A (en) * | 1979-10-29 | 1981-06-01 | Seiko Epson Corp | C-mos integrated circuit |
| JPS57143852A (en) * | 1981-03-03 | 1982-09-06 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor integrated circuit device |
-
1982
- 1982-09-10 JP JP57156655A patent/JPS5947766A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5345978A (en) * | 1976-10-08 | 1978-04-25 | Hitachi Ltd | Insulated-gate-protective semiconductor device |
| JPS5664465A (en) * | 1979-10-29 | 1981-06-01 | Seiko Epson Corp | C-mos integrated circuit |
| JPS57143852A (en) * | 1981-03-03 | 1982-09-06 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor integrated circuit device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01280359A (en) * | 1988-05-06 | 1989-11-10 | Fuji Electric Co Ltd | Insulated-gate type semiconductor device |
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