JPH0621364A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device enabling simplification of a process, by forming an electrode on a laminated ferroelectric film. CONSTITUTION:When a voltage of -Vcc is impressed on an electrode 15 and a silicon substrate 1 is grounded, the part of a P2T film 12 covered with the electrode 15 is polarized upward and, therefore, holes are induced in the surface of the silicon substrate 1 in the part of a P region 2 between a drain region 4 and a source region 5. When a voltage of +Vcc is impressed on an electrode 16 and the silicon substrate 1 is grounded likewise, the part of the P2T film 12 covered with the electrode 16 is polarized downward and, therefore, electrons are induced in the surface of the silicon substrate 1 having no impurities between the drain region 4 and the source region 5. Accordingly, a Pn junction is formed between the drain region and the source region by the holes and the electrons and a ferroelectric film in an isolating region can be prepared simultaneously when a gate ferroelectric film of FET is prepared. Therefore a process of isolating discrete FETs can be simplified.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device. More specifically, it relates to a semiconductor device using a ferroelectric film in an isolation region between individual FETs in a nonvolatile memory having a planar FET structure.

[0002]

2. Description of the Related Art Generally, when wiring between MOSFETs is performed on an insulating film, a similar MOS structure is formed between two MOSFETs. Channels may form below and leaks may occur. In order to eliminate this leak, nMOSFETs in conventional CMOS integrated circuits have been used.
The method of separating the pMOSFET from the pMOSFET has been used such as thickening the field insulating film and increasing the surface impurity density.

However, in the method of thickening the field insulating film, the insulating film becomes too thick and the step difference with the gate insulating film of the MOSFET becomes large, which may cause disconnection at the time of wiring. In addition, in order to separate the nMOSFET and pMOSFET by the method of increasing the surface impurity density, 2
It is necessary to dope impurities between two MOSFETs,
There is a problem that the number of manufacturing processes increases.

[0004]

Thus, according to the present invention, one surface layer of a semiconductor substrate having a first conductivity type has an impurity having a second conductivity type opposite to the first conductivity type. A region, and a pair of high-concentration impurity regions having a first conductivity type and arranged to face one surface layer of the impurity region,
An element having a ferroelectric film formed on the surface of the semiconductor substrate so as to straddle the first high-concentration impurity region and an electrode formed on the ferroelectric film; and having a second conductivity type. A pair of high-concentration impurity regions of the second conductivity type, which are arranged to face each other on one surface layer of the semiconductor substrate without contacting the impurity regions, and a high-concentration impurity region having the second conductivity type. A device formed of a ferroelectric film formed on the surface of the semiconductor substrate so as to stride and an electrode formed on the ferroelectric film, and a device formed on the semiconductor substrate so as to separate the devices from each other. There is provided a semiconductor device comprising a dielectric film and two electrodes formed on the ferroelectric film.

The substrate used is a semiconductor material.
If it is not particularly limited, a silicon substrate or the like is preferable.
Good One surface layer of n-type or p-type first conductivity type substrate
A second conductivity type opposite to the first conductivity type substrate.
An impurity region having is formed. With the implanted ions for that
Then, when the p-type conductive region is used, boron or the like is used.
In the case of an n-type conductive layer, P, As, etc. may be mentioned.
It Injection conditions are 30 to 150 KeV, 1 × 10 ¹²
~ 5 x 10¹³ions / cm²Ion-implanted at about the same concentration
Then, for example, in a non-oxidizing atmosphere at 600 to 1300 ° C for 5 minutes
It can be formed by annealing for about 1 hour.
You can

A pair of high-concentration impurity regions (source region and drain region) having the first conductivity type are formed in one surface layer of the impurity region having the second conductivity type. Boron or the like may be used as the implanted ions for that purpose when the p ⁺ type conductive region is used, and P and A are used when the n ⁺ type conductive layer is used.
s and the like. The injection conditions are 10 to 50 Ke.
V after ion implantation at a concentration of about 1 × 10 ^{15 to} 5 × 10 ¹⁶ ions / cm ² , for example, 600 to 13 in a non-oxidizing atmosphere.
It can be formed by annealing at 00 ° C. for about 5 minutes to 1 hour.

On one surface layer of the n-type or p-type first conductivity type substrate, a pair of high-concentration impurity regions (source region and drain) having the second conductivity type without being in contact with the second conductivity type region. Area) is formed. Boron or the like may be used as the implanted ions for forming the p ⁺ type conductive region, and P, As or the like may be used as forming the n ⁺ type conductive layer. The injection conditions are 10 to 50 KeV, 1 × 10 ¹⁵ to
After ion implantation at a concentration of about 5 × 10 ¹⁶ ions / cm ² ,
For example, in a non-oxidizing atmosphere at 600 to 1300 ° C. for 5 minutes to 1
It can be formed by annealing for about an hour.

Next, a ferroelectric film is laminated by MOCVD, sputtering or the like so as to straddle the high-concentration impurity region having the first conductivity type and the high-concentration impurity region having the second conductivity type, and at the same time, each of them is formed. It is laminated on a semiconductor substrate so as to separate the elements. Examples of the ferroelectric film that can be used include lead zirconate titanate (PZT) and PLZT. The ferroelectric film 9 can be formed by a known method, for example, when PZT is used, Pb (C ₂ H ₅ ) is formed by MOCVD. ₄ , Z
It is preferable to use n (DPM) ₄ and Ti (i-C ₃ H ₇ ) ₄ to form a film having a thickness of 0.1 to 10 μm.

Next, electrodes are formed on the laminated ferroelectric films. Here, two electrodes on the ferroelectric film laminated on the semiconductor substrate at the same time so as to separate the respective elements are formed at intervals of 5 to 10 nm with the boundary between the elements as the center. The electrode can be formed by a known method, for example, a sputtering method using a metal target, a CVD method, an evaporation method, or the like, and the thickness of the electrode is preferably about 0.1 to 10 μm. Further, as the material used for the electrodes, for example, Al, Pt, or other metals that are commonly used for electrodes can be used.

The semiconductor device of the present invention can be formed by the above steps.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A more detailed description will be given below with reference to FIG.
FIG. 1 is a view showing a sectional structure of a ferroelectric memory element of the present invention. 1 is an n-type silicon substrate having a first conductivity type,
2 is the second n-type silicon substrate surface layer doped with boron
Are p ⁺ regions 3 and 4 which are impurity regions having a conductivity type of n ⁺ high concentration impurity regions having a first conductivity type in which the silicon substrate surface layer of the p region 2 is heavily doped with phosphorus, and The drain regions 5 and 6 are source regions and drain regions which are p ⁺ high-concentration impurity regions having a second conductivity type in which the surface layer of the n-type silicon substrate is heavily doped with boron, and 7 and 9 are n ⁺ regions. And p ⁺ region source electrodes, 8 and 10 are n ⁺ region and p ⁺ region drain electrodes,
11, 12 and 13 are ferroelectric films formed on the surface of the silicon substrate 1 between the source electrode and the drain electrode, 14,
Reference numerals 15, 16 and 17 are electrodes laminated on the ferroelectric films 11, 12 and 13.

The manufacturing method is as follows. The n-type silicon substrate 1 was thermally oxidized to form an oxide film, and the oxide film in a desired region was removed by etching. Next exposed n
Type silicon substrate 1 has a surface layer of boron of 100 KeV, 1
Ions were implanted at × 10 ¹³ ions / cm ² and annealed at 1000 ° C. to form the p region 2. Next, an oxide film was formed in the exposed region by a thermal oxidation method, and the oxide film in a desired region was removed by etching. Next exposed p
Phosphorus is added to the surface layer of the region 2 at 50 KeV, 5 × 10 ¹⁵ ions / c
Ion implantation was performed at m ² and annealing treatment was performed at 1000 ° C. to form a source region 3 and a drain region 4 which are n ⁺ regions. Next, an oxide film was formed on the exposed region by a thermal oxidation method. Further, the oxide film in a desired region was removed by etching in order to implant ions into the region of the substrate 1 not in contact with the p region 2. Next, boron is ion-implanted into the exposed surface layer of the substrate 1 at 20 KeV and 5 × 10 ¹⁵ ions / cm ² ,
Annealing treatment was performed at 1000 ° C. to form a source region 5 and a drain region 6 which are p ⁺ regions, and an oxide film was formed on the exposed region by a thermal oxidation method.

Next, the oxide film between the source region 3 and the drain region 4, the source region 5 and the drain region 6 and between the source region 5 and the drain region 4 is removed by etching to form a film on the exposed surface of the silicon substrate 1. PZT film (P
t (Zr _1-X Ti _X ) O ₃ : X = 0.3 to 0.6) 11,
12 and 13 are formed by _{Pb (C 2 H 5) 4} , Zn (DPM) 4 and _{Ti (i-C 3 H 7} ) MOCVD method using _4, an oxide film was formed by the entire surface thermal oxidation.

Next, the source regions 3 and 5, the drain regions 4 and 6, the PZT films 11, 12 and 13 and the PZT film 1 are formed.
The oxide film on 2 was removed by etching, and Al electrodes 7, 8, 9, 10, 14, 15, 16 and 17 were formed to a thickness of 0.3 μm by the sputtering method. Here electrode 1
5 and 16 were laminated at intervals of 10 nm centering on the boundary between the n-type substrate 1 and the p-type diffusion region, and were manufactured so as to sufficiently cover the PZT film 12.

The operation of this device is as follows. Electrode 1
5 a voltage of -V _CC is applied to, by grounding the silicon substrate 1, the portion covered by the electrodes 15 of the PZT film 12 is polarized upward. Therefore, holes are induced on the surface of the silicon substrate 1 in the portion of the p region 2 between the drain region 4 and the source region 5. Similarly, the electrode 16
By applying a voltage of + V _CC to and grounding the silicon substrate 1, the portion of the PZT film 12 covered by the electrode 16 is polarized downward. For this reason, electrons are induced on the surface of the silicon substrate 1 where there is no impurity diffusion between the drain region 4 and the source region 5. A pn bond is formed between the drain region 4 and the source region 5 by the holes and electrons thus induced, and an effect equivalent to that of the conventional method of increasing the surface impurity density and separating is obtained.

[0016]

According to this element structure, the ferroelectric film in the isolation region can be formed at the same time when the gate ferroelectric film of the FET is formed. Therefore, the process for separating the individual FETs is simplified and the cost is reduced. realizable.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view of a semiconductor device of the present invention.

[Explanation of symbols]

1 n-type silicon substrate 2 p-type doped region 3 n ⁺ source region 4 n ⁺ drain region 5 p ⁺ source region 6 p ⁺ drain region 7, 8, 9, 10 electrodes 11, 12, 13 ferroelectric film 14, 15 , 16, 17 electrodes

Claims (1)

[Claims] 1. An impurity region having a second conductivity type opposite to the first conductivity type in one surface layer of a semiconductor substrate having a first conductivity type, and a surface region of the impurity region facing each other. And a pair of high-concentration impurity regions having a first conductivity type, a ferroelectric film formed on the surface of the semiconductor substrate so as to straddle the first high-concentration impurity region, and the ferroelectric film. An element formed of an electrode formed on a body film, and a second conductivity type disposed so as to face one surface layer of the semiconductor substrate without contacting the impurity region having the second conductivity type. From a pair of high-concentration impurity regions and a ferroelectric film formed on the surface of the semiconductor substrate so as to straddle the high-concentration impurity region having the second conductivity type, and an electrode formed on the ferroelectric film. Formed on the semiconductor substrate so as to separate the element and the element A semiconductor device comprising: a ferroelectric film formed on the ferroelectric film; and two electrodes formed on the ferroelectric film.