JPS5946051A - Insulated type semiconductor device - Google Patents

Insulated type semiconductor device

Info

Publication number
JPS5946051A
JPS5946051A JP15587982A JP15587982A JPS5946051A JP S5946051 A JPS5946051 A JP S5946051A JP 15587982 A JP15587982 A JP 15587982A JP 15587982 A JP15587982 A JP 15587982A JP S5946051 A JPS5946051 A JP S5946051A
Authority
JP
Japan
Prior art keywords
plate
semiconductor device
opening
resin
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15587982A
Other languages
Japanese (ja)
Inventor
Yasutoshi Kurihara
保敏 栗原
Tadashi Minagawa
皆川 忠
Komei Yatsuno
八野 耕明
Michio Ogami
大上 三千男
Takayuki Wakui
和久井 陽行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP15587982A priority Critical patent/JPS5946051A/en
Publication of JPS5946051A publication Critical patent/JPS5946051A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To obtain an insulated type semiconductor device, which is not deformed and damaged and radiation to a side surface thereof is also excellent, by soldering a semiconductor device on a metallic plate soldered on an Al2O3 plate, setting up the Al2O3 plate in the opening section of a protective plate made of copper and filling an air gap section with an insulating resin. CONSTITUTION:Openings 110a, 110b to which a stepped difference is formed are formed to the copper plate 1 in 10mm. thickness. On the other hand, the two metallic plates 3 in approximately 2mm. thickness are soldered on the metallized surface of the Al2O3 plate 2 in approximately 0.1mm. thickness, and SCRs 401 and diodes 402 are soldered 102 on the metallic plates 3, thus constituting a function section. The function section is bonded with the opening 110a of the copper plate 1 with Si resin adhesives 103, and an air gap between the function section and the opening section 110b is filled with the epoxy group insulating resin 6. According to the constitution, radiant property is improved while the insulated type semiconductor device hardly getting trouble due to thermal strain and thermal fatigue is obtained.

Description

【発明の詳細な説明】 〔利用分野〕 本発明は、絶縁型半導体装置に関するものであり、特に
、半導体基体と、前記半導体基体を支持するための支持
部材とが電気的にPHさhた構成の絶縁型半導体装置に
関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application] The present invention relates to an insulated semiconductor device, and particularly to a structure in which a semiconductor substrate and a support member for supporting the semiconductor substrate are electrically PH-depleted. The present invention relates to an insulated semiconductor device.

〔従来技術〕[Prior art]

従来、半導体装置の支持部Hに、半導体装(ifの一電
極を兼ねるように#’!成される場合が多かった。
Conventionally, #'! was often formed on the supporting portion H of a semiconductor device so as to also serve as one electrode of the semiconductor device (if).

1〜かし,近年、半導体装置の全ての電極を、金属支持
部材から電気的に絶縁し、これによって、半シハ体装#
tの回路適用上の自由度を増すことのできるように構成
されたものが出現している。
In recent years, all electrodes of semiconductor devices have been electrically insulated from metal supporting members, and this has made it possible to
A device has been developed that is configured to increase the degree of freedom in circuit application of t.

例えば、絶縁性トライアックは、双方向性3 1M5子
サイリスタ(トライアック)基体を、セラミックス板上
に*iし、このセラミックス板を、金属パッケージに封
入したものである。前記トライアツクの全ての電極は、
セラミックス板によりパッケージから絶縁されて外部へ
引出されている。
For example, an insulating triac is one in which a bidirectional 31M5 child thyristor (triac) substrate is mounted on a ceramic plate, and the ceramic plate is enclosed in a metal package. All electrodes of the triax are
It is insulated from the package by a ceramic plate and pulled out to the outside.

そのため、一対の主Tg、極を、回路上の接地電位から
電気的に浮かせて、電極電位とけ無関係に、パッケージ
を接地電位部に固定することができるので、半導体装置
の実装が容易になる。
Therefore, the pair of main Tg and poles can be electrically floated from the ground potential on the circuit, and the package can be fixed to the ground potential section regardless of the electrode potential, making it easy to mount the semiconductor device.

また、混成集積回路装置あるいは半導体モジーール装置
(以下混成ICと一括して略称する)では、一般に半導
体素子を含む、ある号と捷っだ電気回路が相通まれるた
め、その回路の少1. くとも一部と、混成ICの支持
部材、あるいは放熱部材等の金属部とを、電気的に絶縁
する必要がある。
In addition, in a hybrid integrated circuit device or a semiconductor module device (hereinafter collectively referred to as hybrid IC), a certain number of electrical circuits including a semiconductor element and a disconnected circuit are generally connected to each other. It is necessary to electrically insulate at least a part of the hybrid IC from a supporting member of the hybrid IC or a metal part such as a heat dissipating member.

代表的な混成’ICで42金属の支持部材上に、炸機質
あるいは有機質の絶縁層を配置し、この絶縁層上に所定
の電気回路を組立てることにより、上述の絶縁を達成し
ている。このような構成の混成ICもまた、絶縁型半導
体装置の一種である。
In a typical hybrid IC, the above-mentioned insulation is achieved by disposing an insulating layer of explosive material or organic material on a supporting member of 42 metal, and assembling a predetermined electric circuit on this insulating layer. A hybrid IC having such a configuration is also a type of insulated semiconductor device.

一方、半導体装置を、安全かつ安定(′−動作させるだ
めには、半導体装置の動作時に生ずる2−4、パッケー
ジの外部に有効に発散させる必要がある。
On the other hand, in order for a semiconductor device to operate safely and stably, it is necessary to effectively dissipate 2-4, which occurs during the operation of the semiconductor device, to the outside of the package.

この熱発散は、通常、発熱源である半導体基体から、こ
れに接着された各部材を通じ、気中へ熱伝達されること
で達成される。
This heat dissipation is normally achieved by transferring heat from the semiconductor substrate, which is the heat source, to the air through the members bonded to the semiconductor substrate.

したがって、絶縁型半導体装置の熱伝導経路中には、支
持部材、支持部材と絶縁層との間の後盾材層、前記絶縁
層、および前記絶縁層と半導体基体との間の接着材層等
が含1れる。
Therefore, in the heat conduction path of the insulated semiconductor device, there are a supporting member, a backing material layer between the supporting member and the insulating layer, the insulating layer, an adhesive layer between the insulating layer and the semiconductor substrate, etc. Includes 1.

寸た、半導体装置を含む回路の扱う電圧が、高くなれば
なるほど、あるいは、要求される信頼性(経時的安定性
、耐湿性、耐熱性等)が高くなればなるほど、完全な絶
縁性が要求される。
In fact, the higher the voltage handled by a circuit including a semiconductor device, or the higher the required reliability (stability over time, moisture resistance, heat resistance, etc.), the more perfect insulation is required. be done.

上述の耐熱性は、半導体装置の周囲の温度が外因により
上昇しまた場合の他、半導体装置の扱う電力が大きく、
また、半導体基体で発生する熱が大きくなった場合等に
も要求されるものである。
The above-mentioned heat resistance is effective when the temperature around the semiconductor device increases due to external causes, or when the semiconductor device handles a large amount of power.
It is also required when the heat generated in the semiconductor substrate increases.

絶縁型半導体装置内での発熱が比較的小さく、かつ、要
求される耐圧や信頼性がさほど高くない場合には、絶縁
層や接着利層としてどのようなものを用いても問題はな
い。
If the heat generated within the insulated semiconductor device is relatively small and the required voltage resistance and reliability are not very high, there is no problem in using any material as the insulating layer or adhesive layer.

しかし、発熱が大きい場合や信頼性に対する要求が高い
場合には、絶縁層として一般に、セラミックスのような
無機質材料が選択される。また、接着材層としては、例
えば、鉛−錫系はんだのような金属ろうが選択さハる0 しか(7々から、その場合、次のような解決すべき問題
点があった。一般に、絶縁型半導体装置では、絶縁層は
、前記絶縁層を機械的に保護し、かつ、絶縁層を経由し
て伝達された熱を吸収して、外部へ効果的に放出するだ
めの支持部材上に取付けられる。
However, in cases where heat generation is large or reliability requirements are high, inorganic materials such as ceramics are generally selected for the insulating layer. In addition, as the adhesive layer, for example, a metal solder such as lead-tin solder is selected. In an insulated semiconductor device, an insulating layer is provided on a support member that mechanically protects the insulating layer, absorbs heat transferred via the insulating layer, and effectively releases it to the outside. Installed.

この支持部利とl−ては、銅等の機械的強度が大きく、
かつ、高熱伝導性の金属が用いらil、る。ところが、
この全1f株と絶縁層とでは、熱心9イ系方文〃二大幅
に異なる。
The advantage of this support is that the mechanical strength of materials such as copper is high;
In addition, a metal with high thermal conductivity is used. However,
This total 1f strain and the insulating layer are significantly different.

例えば、絶縁層がアルミナの場合、熱膨張係数は6.3
 X 10−67Gであるのに対して、錆の熱膨張係数
は18 X 1 o”7℃と極めて大きい。
For example, if the insulating layer is alumina, the coefficient of thermal expansion is 6.3.
X 10-67G, whereas the coefficient of thermal expansion of rust is extremely large at 18 X 1 o"7°C.

問題の第]は、この熱膨張係数差によって起るものであ
り、61f1縁型半導体装置製造時に、絶縁層を上述の
支持部材上にはんだ付けする場合に生ずる。即ち、tし
んだ付けは、支持部材と絶縁層とな、はんだ層を介して
積層した後、はんだの融点以上まで温度を上昇させ、そ
の後室温まで冷却することによって行なわれる。
The first problem is caused by this difference in thermal expansion coefficients, and occurs when an insulating layer is soldered onto the above-mentioned support member during the manufacture of a 61f1 edge type semiconductor device. That is, t-soldering is carried out by laminating the supporting member and the insulating layer via the solder layer, raising the temperature to the melting point of the solder or higher, and then cooling them to room temperature.

前記冷却工程においては、はんだの凝固点で各部材が互
いに固定さhる。その後は、凝固したはんだにより固定
された状態で、各部層固有の熱膨張係数に従って収縮す
る。
In the cooling step, each member is fixed to each other at the solidification point of the solder. Thereafter, each layer contracts according to its own coefficient of thermal expansion while being fixed by solidified solder.

この時、上述の熱膨張係数の差によって 部利の収縮量
が異なり、各部拐の接着部にいわゆる熱歪が残留する。
At this time, the amount of shrinkage of the parts differs depending on the difference in the thermal expansion coefficients mentioned above, and so-called thermal strain remains in the bonded parts of each part.

熱歪はそれが比較的小さいときは、最も軟らかい部材で
あるはんだ層で吸収されるが、吸収しきノフないときK
は、後晒きれた各部材が変形するに至る。
When thermal strain is relatively small, it is absorbed by the solder layer, which is the softest member, but when there is no enough to absorb it, K
This results in deformation of each exposed member.

特に、支持部イ、イ゛の変形や反りは、半導体基体を気
W%封止する際の障害になったり、絶縁型半導体必t4
を、放熱手段′に11y付ける際の密着性を阻害したり
する。
In particular, deformation or warping of the supporting parts A and I may become an obstacle when encapsulating the semiconductor substrate with air, or the insulated semiconductor must be
This may impede the adhesion when attaching 11y to the heat dissipating means'.

問題点の第2は、この紳の半導体装置の使用時に生ずる
。即ち、半導体装置の通電、休止動作にf1′−って、
上述の接着@には、高温状態(約100〜15(1℃)
と低温状態(周囲温疫)が繰返し肋ノする。
The second problem arises when this gentleman's semiconductor device is used. In other words, f1'- is used for the energizing and resting operations of the semiconductor device.
For the above-mentioned adhesion@, high temperature conditions (approx.
The low temperature condition (ambient temperature epidemic) causes repeated pain.

このように、高幅−低潟状態が繰返す(その1周期をヒ
ートザーfクルと呼ぶ)母に、各部材はそゎ。
In this way, each member is in a state of repeating high width and low width (one cycle is called a heat cycle).

らの固有の熱膨張係数に基づいて膨張、収縮を繰返す。Expansion and contraction are repeated based on their unique coefficient of thermal expansion.

各部材は互いに固着されているから、各部材の熱膨張係
数の違いに基づく、膨張、収縮類の差は、最も軟かい部
材であるはんだ層に加わる熱歪となって現れる。
Since each member is fixed to each other, differences in expansion and contraction based on differences in thermal expansion coefficients of each member appear as thermal strain applied to the solder layer, which is the softest member.

そして、ヒートサイクル数が多く々ると、はんだ層には
、引張り歪、圧縮歪が周期的に度7Fなって生じて、次
第にもろくなり、ついには熱疲労力J象を生ずるに至る
As the number of heat cycles increases, tensile strain and compressive strain of 7 degrees Fahrenheit occur periodically in the solder layer, which gradually becomes brittle, eventually leading to the occurrence of a thermal fatigue stress J phenomenon.

例えば、はんだ層にクラックが生じ、接着力の低下、熱
伝導性の低下等を引起す。このような両11象は、はん
だ層の露出端面において特に顕著である0 第3番目に熱放散性に関する問題点があげられる。一般
に絶縁型半導体装置では、支持部材」−に塔載された半
導体基体や、その周辺の配線部材や絶縁層等を株うため
の気密封止手段がとられる。
For example, cracks occur in the solder layer, causing a decrease in adhesive strength, a decrease in thermal conductivity, and the like. These two conditions are particularly noticeable on the exposed end face of the solder layer.The third problem is related to heat dissipation. Generally, in an insulated semiconductor device, an airtight sealing means is used to seal a semiconductor substrate mounted on a support member, wiring members, insulating layers, etc. around the semiconductor substrate.

前記気密封止手段としては、通常は、支持部材上にエポ
キシ樹脂等からなる枠体を設け、さらに、この枠体と支
持部材とで形成される中空部にエポキシ樹脂等を充填し
ている。
The hermetic sealing means usually includes a frame made of epoxy resin or the like provided on the support member, and a hollow portion formed by the frame and the support member filled with epoxy resin or the like.

このような封止構造では、枠体の側面は直接空気に助れ
る構造となっているが、エポキシ樹脂等は熱伝導性がよ
〈々い−すなわち、熱抵抗が大きい。したがって、側面
からの効果的なりy熱シ、1あまり期待できず、主とし
て、エポキシ樹脂等に接していない面からhk 熱する
In such a sealing structure, the side surfaces of the frame are directly exposed to air, but epoxy resin and the like have very good thermal conductivity, that is, high thermal resistance. Therefore, it is not possible to expect much effective heating from the sides, and heat is mainly applied from the side that is not in contact with the epoxy resin or the like.

しかしながら、エポキシ樹脂等に接し々い面からの放熱
だけでは、熱放散性が著しく劣る。同時に、このような
封止M造をとるためには1、専用の枠体が必要になる。
However, if heat is radiated only from the surface that is in close contact with the epoxy resin, the heat dissipation performance is significantly inferior. At the same time, in order to use such a sealed M structure, 1. A dedicated frame is required.

〔目 的〕〔the purpose〕

本発明の目的V、11上述の問題点を解決し、製造時あ
るいは運転時に生ずる熱歪を低減し、各部材の変形、変
性、あるいは破損の恐れがなく、側面方向への放熱性も
改善された絶縁型半導体装置を提供することにある。
Objectives V and 11 of the present invention: Solve the above-mentioned problems, reduce thermal distortion that occurs during manufacturing or operation, eliminate the risk of deformation, degeneration, or damage of each member, and improve heat dissipation in the lateral direction. An object of the present invention is to provide an insulated semiconductor device.

〔概 要〕〔overview〕

前記の目的を達成するために本発明は、無機質絶縁部材
上に金属ろうを用いて金属板を接着し、さらに、この金
にバ板上に、全国ろうを月1いてず7.1’i。
In order to achieve the above object, the present invention adheres a metal plate to an inorganic insulating member using a metal solder, and furthermore, the metal plate is bonded to the metal plate using a metal solder. .

体基体を接着して機@p、部と、平板金属に、その両主
面を貫通するように開1]部苓一般けて稈t・k部材と
を用い、前記保護部材の開[1部に、上記機能部を装着
し、上記保詐部用の開口部と機能部との間に形成される
空間に、絶縁樹脂を充填した点に特徴がある。
Glue the protective member to the protective member and open the protective member so as to penetrate through both main surfaces of the flat metal plate. The feature is that the functional section is attached to the section, and the space formed between the opening for the security section and the functional section is filled with an insulating resin.

また、本発明は、前記機能部を4苛成する無用q’f絶
縁部材の周辺部と平板金属の開1]部の円曲とを樹脂接
着剤によって接着し7た点に特徴がある。
Further, the present invention is characterized in that the peripheral part of the useless q'f insulating member for forming the functional part and the circular part of the opening 1 of the flat metal are bonded together with a resin adhesive.

本発明において、金属板は、半導体基体に対する導電路
、および半導体基体で発生し/ζ熱を1.jl)i。
In the present invention, the metal plate serves as a conductive path to the semiconductor substrate and 1.ζ heat generated in the semiconductor substrate. jl)i.

縁部材と、仁れに連なって配置fi(さ)する、例え(
1、放熱フィンpj;の放熱手段へ効果的に伝達する熱
拡散板として働く。
For example (
1. Works as a heat diffusion plate that effectively transmits heat to the heat dissipation means of the heat dissipation fin pj;

甘だ、絶縁部材は、上述の機能部を放熱剖力・C)電気
絶縁するとともに、放熱手段への主要な導熱路を形成す
る。
The insulating member not only electrically insulates the above-mentioned functional parts from heat dissipation force, but also forms a main heat conduction path to the heat dissipation means.

そして保6φ部材は、機能部を外界から電気的、機械的
に保穫する(−例えば、通常の外力に耐えられる程度に
イ〉;護する)とともに、半導体基体で発生した熱を、
側面から気中へ放散するだめの放熱手段として働く。
The protection member 6φ electrically and mechanically protects the functional part from the outside world (for example, protects it to the extent that it can withstand normal external forces), and also protects the functional part from the heat generated in the semiconductor substrate.
It acts as a means of dissipating heat from the sides into the air.

本発明においては、後述するように、上述の第1、第2
、および第3の問題を解決するために、以下に述べるよ
うな対策を講じた。
In the present invention, as described later, the above-mentioned first and second
, and in order to solve the third problem, the following measures were taken.

(1)放熱性向上の観点から、放熱路の多面化を図った
(1) From the perspective of improving heat dissipation, the heat dissipation path was made multifaceted.

(2)各部拐の熱1j”j’張張機数差よる熱歪低減の
観点から、機能部、保護部材間の一体化面積(接触部分
の面積)を極力小さくした。
(2) From the viewpoint of reducing thermal distortion caused by the difference in the number of tensioners in each part, the integrated area (area of the contact part) between the functional part and the protective member was made as small as possible.

〔実施例〕〔Example〕

以下、本発明を混成■Cf例にとり、更に詳細に説明す
る。
Hereinafter, the present invention will be explained in more detail by taking an example of hybrid ■Cf.

第1図に、本発明の一実施例の、1200■、60A級
混成ICの要部分解斜視図を、第2図に前記実施例の回
路図を示す。図においては、アルミナ4月2上に2枚の
金属板3が並んで接χfさねている。
FIG. 1 is an exploded perspective view of the main parts of a 1200-60A class hybrid IC according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of the embodiment. In the figure, two metal plates 3 are lined up and in contact with an alumina plate 2.

前記金属板3上には、サイリスタ4叫、フライホイル用
ダイオード402が、それぞれの、んだ(;Iけされて
いる。前記アルミナ板2、金ル1板3、ツイリスタ40
1およびフライホイル用ダイオード402で機能部5が
構成さ)1.ている。
On the metal plate 3, a thyristor 4 and a flywheel diode 402 are soldered, respectively.
1 and a flywheel diode 402 constitute a functional section 5)1. ing.

前記機能部5は、板状金属の両主面を貫通して設けられ
た第1、第2開口部110FK110b を有する保護
部材1に装着される。前記第2開口部110b と、こ
れに装着された機能部5とで形成さシ1、る空間には絶
縁樹脂が充填さflている○尚、第1図では、図面を簡
略化するために、各部材間の接着材(はんだ付は用金属
ろう)や充填用樹脂は図示されていない。
The functional section 5 is attached to the protection member 1 having first and second openings 110FK110b provided through both main surfaces of the plate metal. The space formed by the second opening 110b and the functional part 5 attached thereto is filled with an insulating resin. Adhesive materials (metal soldering for soldering) and filling resin between each member are not shown.

上述の金属板3上には、第2図に示すような回路が組立
てらハでいる。即ち、サイリスタ401、フライホイル
用イオード402は第1図に示す配線用ワイヤ440、
配線用金属片430によって、第2図に示すように接続
されている。
A circuit as shown in FIG. 2 is assembled on the metal plate 3 mentioned above. That is, the thyristor 401 and the flywheel iode 402 are connected to the wiring wire 440 shown in FIG.
They are connected by a wiring metal piece 430 as shown in FIG.

41旧、4j02 および4103はそれぞれ外部端子
である。前記外部端子4101は金属板3上に直接配設
されている。前記外部端子4102および4103け、
金属板3上に接着された絶縁用アルミナ板420の上に
接着さり、た配線用金属片430の上に配設さhでいる
41 old, 4j02 and 4103 are external terminals, respectively. The external terminal 4101 is placed directly on the metal plate 3. The external terminals 4102 and 4103,
It is glued onto an insulating alumina plate 420 glued onto the metal plate 3, and placed on a metal piece 430 for wiring.

第3図に前記本発明の一実施例の棚1略断面図を示す。FIG. 3 shows a schematic cross-sectional view of the shelf 1 according to one embodiment of the present invention.

第3図において、図を簡略化するために、機能部5のう
ち外部端子4101.4102 および4103、配線
用ワイヤ440、金属片430および絶縁用アルミナ板
420は省略されている。
In FIG. 3, external terminals 4101, 4102 and 4103, wiring wire 440, metal piece 430, and insulating alumina plate 420 are omitted from functional section 5 to simplify the drawing.

保1;りθ部材1は厚さJoy、の銅板であり、幅40
闘、長さ92龍の大きさを有し、同部材lの中央部には
、幅36mmz長さ7I闘、心さ0.5關の第1開口部
110a と、幅29闘、長さ68朋、ljiさ9.5
闘の第2開口部月Ob とが形成さね1、第] )i1
0部110aと第21シ)10部110bとで1“1通
孔が形FJvされている。
1; Ri θ Member 1 is a copper plate with a thickness of Joy, and a width of 40
The center part of the same member has a first opening 110a with a width of 36 mm, a length of 7 mm, and a height of 0.5 mm, and a width of 29 mm and a length of 68 mm. Tomo, ljisa 9.5
The second opening of the battle is formed by the moon Ob and the 1st opening]
A 1"1 through hole is formed in the shape FJv between the 0 part 110a and the 21st part 110b.

一方、機fil壬部5の−rルミナ板2の一方の面JJ
t−2枚の金iri 41j 3が40φ、鉛−60L
l)(”’、Hの自’!、 I Ir1んだ層101に
より接着され、ている。i)!l 1ltF第1 II
んだ層101のJ’7 iは約0.1 mmである。
On the other hand, one side JJ of the -r lumina plate 2 of the machine fil bottom part 5
T-2 pieces of gold iri 41j 3 is 40φ, lead-60L
l) ('',H's own'!, I Ir1 bonded by layer 101. i)!l 1ltF 1st II
J'7i of solder layer 101 is approximately 0.1 mm.

アルミナ板2の接着面には、周知のメタライズ処理が施
され、(riんだに対するぬれ性が何カさ)9ている。
The adhesion surface of the alumina plate 2 is subjected to a well-known metallization process (wettability against rind)9.

アルミナ板2は幅35關、長さ70丁、厚さ0.41f
f7!であり、金属板3は幅26mm、、gさ31間、
厚さ2朋である。
Alumina plate 2 has a width of 35 mm, a length of 70 mm, and a thickness of 0.41 f.
f7! , the metal plate 3 has a width of 26 mm, a width of 31 mm,
It is 2mm thick.

金属板3上には、サイリスタ401とダイオード402
とが、−に述の第1はんだ層101と同じ組成で、かつ
、同じ厚さの第2はんだ層102により、導電的に接着
さノ1.ている。
A thyristor 401 and a diode 402 are placed on the metal plate 3.
are electrically conductively adhered by a second solder layer 102 having the same composition and thickness as the first solder layer 101 described in -1. ing.

ここで、サイリスタ401は面積が15×10−で厚さ
が0.36mmであり、ダイオード402は面積が5×
5−で厚さが0.2 mytである。このように構成さ
れた機能部5は、上述した幅36m、、、長さ71間、
厚さ05龍の第1開口部110aに樹脂接着材103に
より接着さり、ている。
Here, the thyristor 401 has an area of 15 x 10- and a thickness of 0.36 mm, and the diode 402 has an area of 5 x
5- and a thickness of 0.2 myt. The functional unit 5 configured in this manner has the above-mentioned width of 36 m, length of 71 m,
It is bonded to the first opening 110a of the 05 mm thick plate with a resin adhesive 103.

機能部5と第2開口部110bとで形成される空間には
、絶縁樹脂6が充填されている。前記樹脂接着材103
はシリコーン系樹脂であり、絶縁樹脂6はエポキシ系樹
脂である。
The space formed by the functional section 5 and the second opening 110b is filled with an insulating resin 6. The resin adhesive 103
is a silicone resin, and the insulating resin 6 is an epoxy resin.

アルミナ板2および保護部月1の底面には放熱フィン1
11が設けられている。
A heat dissipation fin 1 is provided on the bottom of the alumina plate 2 and the protective part 1.
11 are provided.

この構成において重要な点は、機能部5とF′に伝27
ケ性に優れた金属製の保設部材1とが、アルミナ板2の
周縁の微少領域で、軟らかい樹脂接着材103により一
体化されていて、熱歪が生じにくい構造に々っている点
である0 また、アルミナ板2の、機能部50回路が構成された側
の面は、前記金属製の保騨部材1の第2開口部110b
に埋没するように装着され、この部分に絶縁樹脂6を充
填して回路を電気的、m ′4m的に保護している点で
ある。
The important point in this configuration is that it is transmitted to the functional section 5 and F'.
The holding member 1 made of metal with excellent compatibility is integrated with a soft resin adhesive 103 in a small area around the periphery of the alumina plate 2, which is suitable for a structure that does not easily cause thermal distortion. In addition, the surface of the alumina plate 2 on the side where the functional section 50 circuit is formed is connected to the second opening 110b of the metal support member 1.
This part is filled with insulating resin 6 to protect the circuit electrically and m'4m.

さらに、前記保逆部材lおよび前記アルミナ板2の雷、
気回路が形成された面の反対側の面にin接接触するよ
うに設けられた放熱手段−す彦わち、放熱フィン111
で多面的に放熱するようにした点である。
Furthermore, the lightning of the reversibility member l and the alumina plate 2,
A heat dissipation means, that is, a heat dissipation fin 111, provided to be in direct contact with the surface opposite to the surface on which the air circuit is formed.
This is because heat is dissipated from multiple sides.

本実施例に基づいて行なった実験例では、放熱性を向上
すると同時に熱歪や熱疲労による故障をも低減すること
ができた。その具体例を以下に説明する。
In experiments conducted based on this example, it was possible to improve heat dissipation and at the same time reduce failures due to thermal strain and thermal fatigue. A specific example thereof will be explained below.

まず、本実施例の混成ICにおけるサイリスタ401か
ら放熱手段に接するアルミナ板2に至る熱抵抗は015
℃/Wであった。
First, the thermal resistance from the thyristor 401 to the alumina plate 2 in contact with the heat dissipation means in the hybrid IC of this example is 0.15
℃/W.

この値は、本実施例と同一の機能部5を、幅40朋、長
さ92間、厚さ3.2・朋の銅板(支持部材)上にはん
だ付けして塔載し、機能部5を樹脂ケースで籾い、同ケ
ースに樹脂を充填した混成IC(比較例)の場合より、
およそ40%低い。
This value is determined by mounting the same functional unit 5 as in this example on a copper plate (supporting member) with a width of 40 mm, a length of 92 mm, and a thickness of 3.2 mm. Compared to the case of a hybrid IC (comparative example) in which the liquid is packed in a resin case and the same case is filled with resin,
Approximately 40% lower.

また、本実施例混成ICのサイリスタ401に200W
の電力損失を生じさせたときの温度上昇は約30℃であ
り、比較例の場合は約50℃であった○ 即ち、本実施例混成ICでは、充填した絶峠樹1、i6
の周囲を、熱伝導性のよい保6ψ部材1で包囲する構造
になっていて、実鞠的に、保舵(部材1が放熱手段と同
様の働きをすることにより、熱放散が効率的かつ多面的
になされる結果、上述の性能が得ら1+た。
In addition, the thyristor 401 of the hybrid IC of this embodiment has a power of 200W.
The temperature rise when power loss occurred was about 30°C, and in the case of the comparative example it was about 50°C. In other words, in the hybrid IC of this example, the filled
It has a structure in which the periphery of the rudder is surrounded by a retaining member 1 with good thermal conductivity, and in practical terms, the rudder retainer (member 1 functions similarly to a heat dissipation means, so heat dissipation is efficient and As a result of multifaceted efforts, the above-mentioned performance was obtained.

次に、¥、4図は本実施例混成ICの熱抵抗を、ヒート
サイクルを与え外から追跡した結果を示したものである
Next, Figure 4 shows the results of externally tracking the thermal resistance of the hybrid IC of this embodiment by applying a heat cycle.

図の柊軸にはヒートサイクル数、縦軸には熱抵抗がとら
れている。ヒートサイクルは一55℃から+150℃ま
での温度変化を与えて行なった。
The number of heat cycles is plotted on the axis of the figure, and the thermal resistance is plotted on the vertical axis. The heat cycle was performed by varying the temperature from -55°C to +150°C.

同図において、線Aは本実施例の混成ICの結果、そし
て純Bは上述の比較例の結果を示したものである。
In the figure, line A shows the result of the hybrid IC of this example, and line B shows the result of the above-mentioned comparative example.

図から明らかなように、前述した本実施例の?11゜成
ICでは、ヒートサイクル数700回までU1熱抵抗の
増大は見られない。これに対し、比較例の混成ICでは
、ヒートサイクル数200回を過きると、熱抵抗の増大
が見られ、両者間の差異が明確に見出されている。
As is clear from the figure, the ? In the 11° IC, no increase in U1 thermal resistance was observed up to 700 heat cycles. On the other hand, in the hybrid IC of the comparative example, an increase in thermal resistance was observed after 200 heat cycles, and a difference between the two was clearly found.

本実施例の場合は、前述した比較例の構造のように、熱
疲労破壊を生じやすいアルミナ択一支持部材間の、大面
積にわたる接着部を有しておらず、熱抵抗を増大させる
要因の1つが取除かれている。
In the case of this example, unlike the structure of the comparative example described above, there is no adhesive part over a large area between the alumina support members that are likely to cause thermal fatigue failure, and this is a factor that increases thermal resistance. One has been removed.

そして、アルミナ板2は軟かい樹脂接着剤103により
保護部材1と一体化されていて、アルミプ板2と保護部
材1との間の熱膨張係数差に基づく熱歪を、樹脂接着材
103が効果−的に吸収する。
The alumina plate 2 is integrated with the protection member 1 by a soft resin adhesive 103, and the resin adhesive 103 is effective in reducing thermal distortion due to the difference in coefficient of thermal expansion between the alumina plate 2 and the protection member 1. - to absorb.

その結果、アルミナ枦2そのものの内部応力が軽減さね
1、副次的効果として、はんだ層101に対する影響も
緩和される。上述のヒートサイクルによる結果に明らか
な差異が見出されたのdlこのようなJk情による。
As a result, the internal stress of the alumina resin 2 itself is reduced 1, and as a secondary effect, the influence on the solder layer 101 is also reduced. The obvious difference found in the results due to the heat cycle described above is due to these circumstances.

捷た、本実li例の混成ICは、反りの点および封止の
気密性の点でも優れていた。例えば、放熱手段に直接接
触するアルミナ板2の反り(アルミナ板2の露出平面の
曲率半径)は380 cmと長かっ/こ。
The shredded hybrid IC of this example was also excellent in terms of warpage and airtightness of the seal. For example, the warpage of the alumina plate 2 that comes into direct contact with the heat dissipation means (the radius of curvature of the exposed plane of the alumina plate 2) is as long as 380 cm.

オだ、混成ICを相対湿度90%、流度6o℃の雰囲気
下でIn(10時間通軍、しても、混成ICの電気的性
能には異常なかった。
Even when the hybrid IC was exposed to In in an atmosphere with a relative humidity of 90% and a flow rate of 6oC for 10 hours, there was no abnormality in the electrical performance of the hybrid IC.

唄に、本実Afli例の混成ICでは、機能部5と保f
JQ部用1とで形成さtする空間に絶縁樹脂6を充填し
た。
In the song, in the hybrid IC of the real Afli example, the functional unit 5 and the
The space formed by the JQ part 1 was filled with an insulating resin 6.

つまり、機能部5と保護部材1が樹脂充填のための容器
を兼ねるため、専用の枠体が不要である。
In other words, since the functional section 5 and the protective member 1 also serve as a container for resin filling, a dedicated frame is not required.

この点も本実施例混成ICで4!) A)tqた副次的
効果である。
This point is also 4 for the hybrid IC of this embodiment! ) A) It is a side effect of tq.

以下、本発明の各種変形例について例示する。Various modifications of the present invention will be illustrated below.

本発明は上述した実施例の列、以下のような種々の態様
にて実施することが可能である。
The present invention can be implemented in various ways in addition to the embodiments described above.

オす、本実施例において、金属1113として組板を用
いた。しかし、こり、に限定さり、るものではなく、混
成ICの放熱性をある程度低下させても、第1、第2d
んだM]、01.102の熱疲労を緩和して信頼性を一
層高めるために、PAjll張係数がアルミナ板2や半
導体基体のそれに近い金属を用いてもよい。
In this example, a composite plate was used as the metal 1113. However, this is not limited to stiffness, and even if the heat dissipation of the hybrid IC is reduced to some extent, the first and second d
In order to further improve the reliability by alleviating the thermal fatigue of solder M], 01.102, a metal whose PAjll tensile coefficient is close to that of the alumina plate 2 or the semiconductor substrate may be used.

例えば、モリブデン、タングステン、あるいは錨1−イ
ンバーa4クラッド複合金鳩や甲−炭素繊維接合金属の
如き物を用いることは好寸しいことである。
For example, it is preferable to use materials such as molybdenum, tungsten, or anchor 1-invar A4 clad composite gold dove or instep-carbon fiber bonded metal.

また、上述の全国板3のシー1んだ付は面に、はんだの
ぬれ性をμくするためにニッケル等の金属膜をめっき法
等により形成しておくことは好ましい。
Further, it is preferable to form a metal film of nickel or the like on the soldering surface of the seam 1 of the above-mentioned national board 3 by plating or the like in order to reduce solder wettability.

つぎに、無ml絶縁部材としては、アルミナの外、窒化
アルミニウム(AIN)、9化刷り素(BN)、炭化シ
リコン(SiC)、窒化シリコン(Si3N4)、酸化
ベリリウム(Bed)等、あるいはこれらを成分として
含む焼成物が使用できる。
Next, as the ml-free insulating material, in addition to alumina, aluminum nitride (AIN), bromine ninede (BN), silicon carbide (SiC), silicon nitride (Si3N4), beryllium oxide (Bed), etc. A fired product containing it as an ingredient can be used.

この場合、熱抵抗の低減、あるいけ第1はんだ層101
の熱疲労を軽減する観点から、無機質絶縁部材を薄くす
ることも可能である。
In this case, the first solder layer 101 can reduce the thermal resistance.
From the viewpoint of reducing thermal fatigue, it is also possible to make the inorganic insulating member thinner.

機能部5において用いられるはんだとしては、40%鉛
−60係錫の組成の外、例オば、95チ鉛−5%錫のも
の、あるいはこれに第3成分として銀、インジウム、亜
鉛、ビスマス等を含むものが使用できる。その厚さも0
.1 mmに限られず、それより厚くても薄くてもよい
In addition to the composition of 40% lead-60 tin, the solder used in the functional part 5 may be, for example, 95 titanium lead-5% tin, or a third component of the solder may be silver, indium, zinc, or bismuth. etc. can be used. Its thickness is also 0
.. The thickness is not limited to 1 mm, and may be thicker or thinner.

金属板3上に搭載さねる半導体基体としては、任意の半
導体素子(シリコン以外の半導体、例えばゲルマニウム
、ひ化ガリウム等を用いたものを含む)を用いることが
できる。寸た、回路構成も任意の回路を構成することが
できることは言う寸でもない。
As the semiconductor substrate mounted on the metal plate 3, any semiconductor element (including those using semiconductors other than silicon, such as germanium, gallium arsenide, etc.) can be used. It goes without saying that any circuit configuration can be constructed.

さらに、金属板3上に塔載される回路素子は、半導体素
子に限らり、るものではなく、例えば抵4A体、コンデ
ンサ等の受動素子を猪載しても伺咎支障はない。
Further, the circuit elements mounted on the metal plate 3 are not limited to semiconductor elements, and passive elements such as resistors and capacitors may also be mounted without any problem.

さらに、金属板3上に塔載される半導体基体は必ずしも
複数である必要はない。
Furthermore, the number of semiconductor substrates mounted on the metal plate 3 does not necessarily have to be plural.

無機質絶縁部材と保進部材との一体化に用いる接着材は
、両部材相互間の歪を緩和する上で、シリコーン樹脂の
如き軟かい樹脂を用いることが、より好ましい。しかし
、必ずしもこf]、 K III(る必爽はなく、例メ
ば、エボギシ系接着利やシリコーンゲルのようなものて
もよい。
As the adhesive used to integrate the inorganic insulating member and the securing member, it is more preferable to use a soft resin such as silicone resin in order to alleviate strain between the two members. However, it is not necessarily necessary to use KIII, and for example, adhesives such as Evogishi adhesive or silicone gel may be used.

機能部5と第2開口部110b とで形成される9間部
に充填される絶縁樹脂6と[7ては、エポキシ系樹脂に
限定されるものではなく、例えば、シリコーン樹脂、シ
リコーンゲル等、あるいは必要に応じこれらの絶縁樹脂
を層状に充填した構成にしてもよい。
The insulating resin 6 and [7 filled in the space between the functional part 5 and the second opening 110b are not limited to epoxy resins, and include, for example, silicone resin, silicone gel, etc. Alternatively, if necessary, a structure in which these insulating resins are filled in a layered manner may be used.

促W!シ部材1とし2てけ、機械的強度および熱伝導性
の病魚から銅を用いるのがよいが、絶縁型半導体装置に
要求さhる性能に応じて、例えば、アルミニウム、鉄、
真鍮等、鉄−ニッケル系合金、シリコンカーバイド等、
他の金属を選定してもよい。
Prompt W! It is preferable to use copper for mechanical strength and thermal conductivity for the first and second parts, but depending on the performance required of the insulated semiconductor device, for example, aluminum, iron,
Brass, iron-nickel alloy, silicon carbide, etc.
Other metals may also be selected.

この場合、側面方向への放熱性を向上させるため、仇N
!:i部材1に、表面積を拡大°する手段を施こすこと
もできる。
In this case, in order to improve heat dissipation in the lateral direction,
! : It is also possible to provide the member 1 with a means for enlarging its surface area.

〔効果〕〔effect〕

本発明は、す、上に説明したように、無機質絶縁部材上
に金属ろうを用いて金属板を接着し、さらに、凸1[記
金屈板」二に、金属ろうを用いて半導体基体を接着して
構成さ)1.た機能部を、平板金属を貫通しCINN 
lj部が形成さ、fまた保護部月の前記開口部に装着し
7、前記開口部と機能部どの間に形成σiする空間に絶
縁樹脂を充j11シ、かつ、耐riL頌8.根乍」絶縁
部材の周辺部と平板金属の開cBτ1(の内:(jIと
トイ91脂接着剤によって接着するようにしたので、r
弘放散性を良好にし1、熱歪による部材の変性あるいl
Z1破壊の恐れをなくすことができるという利点がある
As explained above, the present invention adheres a metal plate onto an inorganic insulating member using a metal solder, and further attaches a semiconductor substrate to the protrusion 1 [metallic bending plate] 2 using a metal solder. (Constructed by gluing) 1. CINN
lj part is formed, f is also attached to the opening of the protective part 7, and the space σi formed between the opening part and the functional part is filled with an insulating resin, and 8. The opening between the peripheral part of the insulating member and the flat metal cBτ1
Improves dissipation properties 1, prevents degeneration or deterioration of parts due to thermal strain
This has the advantage of eliminating the fear of Z1 destruction.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の要γ’411分解1;゛1
杉−11,<11第2図は前記実施例の回路■)、第3
1’J:↓第1図の概略断面図、第4図は前記実JA例
に基づいてイー1なった実験例の結果を現わす図である
。 ■・・・(♀一部部用2・・・アルミナ板、3・・・金
属板、5・・・枦能部、6・・・絶縁樹脂、101・・
・第Jはんだ層、102・・・第2はんだ層、103・
・・樹脂接冶剤、401・・・サイリスタ、402・・
・フライホイル用ダイオード 計 1 囲 牙 2 囮 4]○3 沖 3 口 牙 4 図
FIG. 1 shows the essential γ′411 decomposition 1;゛1 of an embodiment of the present invention.
Sugi-11, <11 Figure 2 shows the circuit of the above embodiment (■), 3rd
1'J: ↓A schematic sectional view of FIG. 1, and FIG. 4 is a diagram showing the results of an experimental example in which E1 was obtained based on the actual JA example. ■・・・(♀For some parts 2...Alumina plate, 3...Metal plate, 5...Driving part, 6...Insulating resin, 101...
・Jth solder layer, 102...Second solder layer, 103・
...Resin adhesive, 401...Thyristor, 402...
・Diode meter for flywheel 1 Surrounding fang 2 Decoy 4]○3 Oki 3 Oral fang 4 Diagram

Claims (2)

【特許請求の範囲】[Claims] (1)無機質絶縁部材上に、金属ろうを用いて金属板が
接着され、さらに、前記金、用板上1;1金属ろうを用
いて半導体基体が接着された構造の機能部と、平板金属
の両主面を貰通ずるように開口部が設けらhた保砕部材
とを有し、この開口部に上配機能部を固着し、上記保護
部材の開口部と機能部とで形成される空間に、絶縁樹脂
を充填したことを特徴とする絶縁型半導体装置。
(1) A functional part having a structure in which a metal plate is bonded on an inorganic insulating member using a metal solder, and a semiconductor substrate is bonded using a metal solder on the gold plate, and a flat metal plate. A crushing member is provided with an opening extending through both main surfaces of the protection member, an upper functional part is fixed to the opening, and the protection member is formed by the opening of the protective member and the functional part. An insulated semiconductor device characterized in that a space is filled with an insulating resin.
(2)上記機能部を構成する無機質絶縁部材の周辺部分
が、樹脂接着剤によって平板金属の開口部の内面に接着
されたことを特徴とする特許 範囲第1項記載の絶縁型半導体装置。
(2) The insulated semiconductor device according to item 1 of the patent scope, wherein a peripheral portion of the inorganic insulating member constituting the functional section is bonded to the inner surface of the opening of the flat metal plate using a resin adhesive.
JP15587982A 1982-09-09 1982-09-09 Insulated type semiconductor device Pending JPS5946051A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15587982A JPS5946051A (en) 1982-09-09 1982-09-09 Insulated type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15587982A JPS5946051A (en) 1982-09-09 1982-09-09 Insulated type semiconductor device

Publications (1)

Publication Number Publication Date
JPS5946051A true JPS5946051A (en) 1984-03-15

Family

ID=15615498

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15587982A Pending JPS5946051A (en) 1982-09-09 1982-09-09 Insulated type semiconductor device

Country Status (1)

Country Link
JP (1) JPS5946051A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0661748A1 (en) * 1993-12-28 1995-07-05 Hitachi, Ltd. Semiconductor device
US6956615B2 (en) * 2000-01-28 2005-10-18 Pentax Corporation Structure for mounting a solid-state imaging device
US20120077317A1 (en) * 2005-10-14 2012-03-29 Ibiden Co., Ltd. Multilayered printed circuit board and method for manufacturing the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0661748A1 (en) * 1993-12-28 1995-07-05 Hitachi, Ltd. Semiconductor device
US6956615B2 (en) * 2000-01-28 2005-10-18 Pentax Corporation Structure for mounting a solid-state imaging device
US20120077317A1 (en) * 2005-10-14 2012-03-29 Ibiden Co., Ltd. Multilayered printed circuit board and method for manufacturing the same
US9027238B2 (en) * 2005-10-14 2015-05-12 Ibiden Co., Ltd. Multilayered printed circuit board and method for manufacturing the same

Similar Documents

Publication Publication Date Title
US6380621B1 (en) Semiconductor device and manufacturing method thereof
US4670771A (en) Rectifier module
JPS6038867B2 (en) Isolated semiconductor device
JPS61292949A (en) Semiconductor module for power
JPH11195680A (en) Semiconductor device connection structure and method
JPH04192552A (en) Package for semiconductor use
JPS6146061B2 (en)
JP3417297B2 (en) Semiconductor device
JPS5946051A (en) Insulated type semiconductor device
JP7203214B2 (en) Power semiconductor device with floating mounting
JPH07176664A (en) Semiconductor device and fabrication thereof
JPS60253248A (en) Heat conductive cooling module device
US7521795B2 (en) Semiconductor package
JP3522975B2 (en) Semiconductor device
JPH0815189B2 (en) Method for manufacturing semiconductor device
JPH0661368A (en) Flip chip type semiconductor device
JPS62781B2 (en)
JP3372169B2 (en) Semiconductor package
JPS5952853A (en) Semiconductor device
JPH08222652A (en) Semiconductor device and production thereof
JPH0374035B2 (en)
JPS5852859A (en) Insulated semiconductor device
JP3036484B2 (en) Semiconductor device and manufacturing method thereof
JPS5848927A (en) Insulated type semiconductor device
JP3410298B2 (en) Semiconductor device and method for forming bump electrode