JP3417297B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin mold insulation type semiconductor device.

[0002]

2. Description of the Related Art Heretofore, a member for supporting a semiconductor element substrate has often served as an electrode of a non-insulating semiconductor device.
For example, a power transistor chip on a copper base with Pb
In a power transistor device integrally mounted with -Sn solder material, the copper base (metal supporting member) serves as the collector electrode and supporting member of the transistor. In such a semiconductor device, a collector current of several amperes or more flows and the transistor chip generates heat. In order to avoid instability of characteristics and deterioration of life due to this heat generation, the copper base also serves as a member for heat dissipation. Further, when a semiconductor chip having a high breakdown voltage and a high frequency and capable of passing a large current is directly soldered and mounted on the copper base, the role of the copper base as a heat dissipation relay member becomes more important.

Further, in an insulated semiconductor device in which all the electrodes of the semiconductor device are electrically insulated from the metal supporting member, and thus the degree of freedom in circuit application of the semiconductor device can be increased, all electrodes are made of insulating members. It is insulated and drawn out from all the package members including the metal supporting member. Therefore, even in the use example in which the pair of main electrodes are floated from the ground potential on the circuit, the package can be fixed to the ground potential portion regardless of the electrode potential, so that the semiconductor device can be easily mounted.

Also in the insulated semiconductor device, in order to operate the semiconductor element safely and stably, it is necessary to efficiently dissipate the heat generated during the operation of the semiconductor device to the outside of the package. This heat dissipation is usually achieved by transferring heat from the semiconductor substrate, which is a heat source, to the air through each member bonded thereto. In the insulating semiconductor device, the heat transfer path includes an adhesive material layer used for a portion for adhering the insulator and the semiconductor substrate.

Further, as the electric power handled by a circuit including a semiconductor device increases, or the required reliability (stability over time, moisture resistance, heat resistance, etc.) increases, complete insulation is required. The heat resistance referred to here includes not only the case where the ambient temperature of the semiconductor device rises due to an external cause but also the case where the electric power handled by the semiconductor device is large and the heat generated in the semiconductor substrate is large.

On the other hand, in a hybrid integrated circuit device or a semiconductor module device, since a certain electric circuit including a semiconductor element is generally incorporated, at least a part of the circuit and a metal part such as a supporting member or a heat radiating member of these devices. And must be electrically isolated. For example, the first
"MIST Substrate" by Akira Kazemi as an example of prior art: Industrial Materials (Vol. 30, No. 3), pp. 22-26 (1983)
Years), on one surface of an aluminum substrate (1-2 mm) with thin alumite layers (14-30 μm) formed on both surfaces,
Copper foil (35μ) through the epoxy insulating resin layer (28μm)
A substrate for a hybrid integrated circuit device in which m) is formed is disclosed. Further, there is disclosed a hybrid integrated circuit device in which a power semiconductor element and a passive element are mounted by soldering on the substrate for the hybrid integrated circuit device in which the copper foil is selectively etched to provide circuit wiring.

In Japanese Patent Laid-Open No. 64-5092 as a second prior art example, an aluminum foil and a copper foil (35 to 1500 μm) are provided on a metal substrate made of aluminum via an epoxy type insulating layer (20 μm or more). There is disclosed a high-power circuit board in which the. There is also disclosed a hybrid integrated circuit in which a plurality of power transistor elements are mounted on the copper foil of the circuit board by soldering.

The circuit board and the hybrid integrated circuit device based on the prior art examples 1 and 2 are excellent in mass productivity and have many economical advantages, and are widely used in the field of semiconductor mounting.

The circuit board and the hybrid integrated circuit device based on the above-mentioned prior art examples 1 and 2 are usually formed in order to accelerate heat dissipation.
It is used by being mechanically attached to a heat sink such as an aluminum fin.

On the other hand, JP-A-8-3 as a third prior art example
In the 16370 publication, an insulating substrate is fixed on a metal radiator plate,
A semiconductor device is disclosed in which a semiconductor element is provided on a conductive layer provided on an insulating substrate, and the surface of the semiconductor element is sequentially coated with an epoxy resin and a silicone gel. In particular, since the epoxy resin is made of a material having a low moisture permeability, it is possible to prevent moisture from entering the inside of the semiconductor device and avoid deterioration of electrical characteristics.

[0011]

In the case of the circuit board and the hybrid integrated circuit device based on the above-mentioned prior art examples 1 and 2, mounted components having a small coefficient of thermal expansion, for example, semiconductor element substrate: 3.
5ppm / ° C (Si), chip resistor: 7ppm / ° C (alumina), chip capacitor: 10ppm / ° C (barium titanate) is a circuit board with a large coefficient of thermal expansion (Al: 25ppm /
C) and is fixed by soldering a Pb-Sn alloy material. The soldering part serves to fix the mounted component at a predetermined position on the board and also to serve as a wiring and a heat dissipation path of the semiconductor device.

However, thermal stress is repeatedly applied to the above semiconductor device during operation or at rest, which eventually causes thermal fatigue failure of the soldered portion. In particular, if the solder material is not properly selected, or if the thermal expansion coefficient of the mold resin for the circuit board is not properly adjusted, excessive residual stress will be present at the joint interface between the two, When the thermal stress during the operation of the semiconductor device is superimposed on this, thermal fatigue fracture of the soldered portion is further accelerated. When this thermal fatigue failure progresses, there are adverse effects such as disconnection and interruption of the heat dissipation path. As a result, the semiconductor device loses its circuit function.

Further, in the case of the circuit board and the hybrid integrated circuit device based on the above-mentioned prior art examples 1 and 2, the semiconductor element substrate which generates a great amount of heat is directly soldered and mounted on the circuit board, and the semiconductor element substrate emits. Makes efficient external dissipation of heat difficult. As a result, the heat dissipation of the device is impaired.

On the other hand, in the case of the prior art example 3, the semiconductor element is directly mounted on the insulating substrate fixed to the metal radiator plate. The insulating substrate in this case is probably ceramic,
Since the difference in coefficient of thermal expansion between the semiconductor element and the ceramic insulating substrate is small, and the thermal conductivity of the ceramic insulating substrate is relatively high, there are not many problems that occur in the prior art examples 1 and 2. However, this technical example requires an expensive ceramic insulating substrate, which is economically disadvantageous.

Therefore, an object of the present invention is to provide a resin-molded insulation type semiconductor device which is excellent in heat dissipation and reliability of a solder connection portion, by compensating for the drawbacks of the prior art examples.

[0016]

The semiconductor device according to the present invention which achieves the above object is characterized in that a semiconductor substrate is heated on an insulating substrate having a copper wiring formed on the main surface of an aluminum plate via an epoxy insulating layer. Mounted via a diffusion member, the difference in coefficient of thermal expansion between the semiconductor substrate and the thermal diffusion member is 10 ppm.
/ ℃ less, and the thermal expansion coefficient difference between the heat diffusing member and the insulating substrate is adjusted to below 18.5 ppm / ℃, between the semiconductor substrate and the heat diffusion member is a Sn on 9 0w t% or less Sb, A
It is fixed by an alloy material to which one or more metals selected from the group of g, Zn, In, Bi and Cu are added, and Sn between the heat diffusion member and the insulating substrate is 35 wt% or more 60
It is fixed by an alloy material containing less than wt% and the balance is substantially Pb, the semiconductor substrate is sequentially coated with an epoxy resin and a silicone gel resin, and the thermal expansion coefficient of the epoxy resin is adjusted to 13 to 21 ppm / ° C. There is something to do.

According to the present invention, the heat dissipation property is improved by the effect of the heat absorption property and the transfer property of the heat diffusion member. Further, the rigidity and the thermal strain absorbing property of the heat diffusion member are compatible with the thermal expansion property of the resin as the sealing material, and the reliability of the solder connection portion is improved.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION The above configuration will be described with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor device of the present invention. The insulating substrate 10 includes a copper wiring layer 3 and an epoxy insulating resin layer 2 on one main surface of an aluminum plate 1 which is a base material.
Are selectively formed. On the insulating substrate 10, the semiconductor element substrate 21, the chip resistor 22 and the chip capacitor 2 are provided.
The passive element composed of 3 and the terminal 24 are alloy materials 25 containing Sn as a main component and one or more kinds of metals selected from the group of Sb, Ag, Zn, In, Bi and Cu added thereto.
It is fixed by 25 '. A heat diffusion member 27 is interposed between the insulating substrate 10 and the semiconductor element base 21. An Al wire (diameter: 300 μm) 26 is wired between the semiconductor element substrate 21 and the copper wiring layer 3 by ultrasonic bonding. Further, the semiconductor element substrate 21 and the mounting portion of the passive element are covered with an epoxy resin 31 having a coefficient of thermal expansion adjusted to 13 to 21 ppm / ° C. by a potting method. The epoxy resin 31 is covered with a silicone gel resin 32. The structure with the above configuration,
A resin case 33 that also serves as an envelope is provided.

The alloy material 25 in the present invention is for electrically and firmly fixing the semiconductor element base body 21, the passive element, and the terminal 24, and it is necessary to have essentially high thermal fatigue fracture resistance. . FIG. 2 is a diagram showing the thermal fatigue fracture resistance of the alloy material. The thermal fatigue fracture resistance of the alloy materials 25 and 25 'is expressed as the temperature cycle number dependence of the thermal resistance between the heat radiation paths from the semiconductor element base 21 to the aluminum plate 1. Here, in order to evaluate the intrinsic resistance of the alloy material,
As shown in FIG.
Soldered directly on top. As the alloy material 25, the curve A is a Sn-5 wt% Sb material (alloy material A), the curve B is a Pb-60 wt% Sn material (alloy material B), and the curve C is a Pb-5 wt% Sn material. The case where (alloy material C) is applied is shown. In the case of the alloy material A, there is almost no variation in thermal resistance up to 300 temperature cycles. On the other hand, in the case of the alloy materials B and C, fluctuations (increase in thermal resistance) have begun to occur around 50 times. The increase in thermal resistance is brought about by the fact that the heat dissipation path is blocked due to the fatigue breakdown of the solder layer due to the temperature change.

As described above, when the alloy material A according to the present invention is applied, the thermal fatigue fracture resistance is superior to that when the conventional solder materials (alloy materials B and C) are applied.
This is because the rigidity of Sn-5 wt% Sb material is Pb-60 wt.
% Sn material and Pb-5 wt% Sn material, and is based on the fact that it is a material that is less likely to undergo plastic deformation.

As an alternative to the Sn-5 wt% Sb material as the alloy material A, for example, Sn-3.5 wt% Ag, S
n-3.5 wt% Ag-1.5 wt% In, Sn-8.5
wt% Zn-1.5 wt% In, Sn-4 wt% Ag-
2 wt% Zn-2 wt% Bi, Sn-4.5 wt% C
u, Sn-0.5 wt% Cu-3 wt% Ag, Sn-2
wt% Sb-0.5 wt% Cu-2 wt% Ag-2 wt
% Zn etc. are mentioned.

Here, the alloy material A will be described.

In the Sn-Sb type alloy material, the composition capable of obtaining a liquidus line at 250 ° C. or lower is in the range of 90 wt% Sn or higher. The higher the liquidus, the higher the soldering process temperature. In this case, the epoxy insulating resin layer 2 formed on the insulating substrate 10 and responsible for insulating the circuit is chemically deteriorated, and good electrical insulation cannot be obtained. Generally, in semiconductor devices, it is desirable to be able to work at processing temperatures as low as possible. From this point of view, it can be said that the Sn-Sb-based alloy material is suitable as a solder material in the composition range of 90 wt% Sn or more so that the liquidus of 250 ° C. or less can be obtained.

However, in the composition region in which the Sn content is close to 90 wt%, the Sn—Sb alloy financial liquid is solid-solidified as a solid solution, and then Sb is formed in the vicinity of the grain boundary of the Sn—Sb alloy crystal.
It is easy to form a peritectic region containing a large amount of. This peritectic region is mechanically brittle and lacks spreadability. Therefore, Sn-Sb is generated in a portion where large thermal stress or thermal strain is likely to occur.
Mechanical damage such as cracks is likely to occur in the area of the base alloy solder material. As a result, the circuit function of the semiconductor device deteriorates. On the other hand, in a composition region in which the Sn content is higher than 90 wt%, the formation of peritectic regions is suppressed, and the ductility of the solder material is secured. As a result, even in a portion where a large thermal stress or thermal strain is likely to occur, mechanical damage such as cracks is less likely to occur, and the circuit function of the semiconductor device is maintained. The Sn concentration selected from the above viewpoint is preferably 95 w.
It can be said that the range is t% or more. This point was also confirmed by various tests described later.

When it is necessary to provide a temperature hierarchy with the alloy material 25 like the alloy material 25 'in the semiconductor device of the present invention, it has a melting point different from that of the alloy material A,
Moreover, a material having excellent thermal fatigue resistance is required. As a second solder material suitable for such a case, Sn is contained in an amount of 35 wt% or more and 60 wt% or less and the balance is substantially P
b alloy material, particularly preferably Pb-50 wt% Sn
Alloy materials such as

In the present invention, the difference in the coefficient of thermal expansion between the semiconductor substrate 21 and the thermal diffusion member 27 is 10 ppm / ° C. or less, and the difference in the coefficient of thermal expansion between the thermal diffusion member 27 and the insulating substrate 10 is 16.
It is adjusted to 5ppm / ℃ or less. Here, the heat diffusion member 27 spreads the heat flow generated in the semiconductor substrate 21 and efficiently transfers it to the insulating substrate 10, and relaxes the difference in the coefficient of thermal expansion between the semiconductor substrate 21 and the insulating substrate 10 to form the connection portion. Is to maintain the reliability of. Here, when a conventionally known Cu material or Mo material is used as the heat diffusion member, it is difficult to secure sufficient connection reliability.
On the other hand, when the thermal diffusion member 27 of which the coefficient of thermal expansion is adjusted according to the present invention is used, sufficient connection reliability can be secured. This point will be described below.

FIG. 3 shows the coefficient of thermal expansion of the thermal diffusion member of the solder connection life of the semiconductor device. Here, the semiconductor device has the structure shown in FIG. 1 (the semiconductor substrate 21 is Si, and the base material of the insulating substrate 10 is the aluminum plate 1).
However, in order to clearly read the influence of the coefficient of thermal expansion of the heat diffusion member, the epoxy resin 31 or the silicone gel resin 3
2 is not provided. In addition, the thermal resistance has an initial value of 1.
It is represented by the number of temperature cycles when it reaches 5 times. The solder connection life tends to increase as the coefficient of thermal expansion of the heat diffusion member increases, and tends to decrease when it exceeds 10 ppm / ° C. For example, the life of the heat diffusion member is Mo material (5.1 ppm).
In the case of Cu material (16.5 ppm / ° C.), it is as short as about 750 times. Heat diffusion member 2 for Mo material
Of the solder layer 25 'between the substrate 7 and the substrate 10 (mode A),
In the case of Cu material, the destruction (mode B) of the solder layer 25 between the semiconductor substrate 21 and the heat diffusion member 27 is the dominant factor for increasing the thermal resistance. On the other hand, in the case of the thermal expansion coefficient region between the Mo material and the Cu material, the life is longer than these. In this case, the damage observed after reaching the life is
Both modes A and B are mixed. By adjusting the coefficient of thermal expansion of the heat diffusion member, the progress of the destruction of modes A and B is suppressed, respectively, and as a result, both joints 25, 25 '.
The effect of extending the life of is obtained.

The life of the semiconductor device as a whole is preferably 1000 times or more when the epoxy resin 31 is not covered. The thermal expansion coefficient range selected from this point of view is 6.5 to 13.5 ppm / ° C. In other words,
The difference in the coefficient of thermal expansion between the semiconductor substrate 21 and the heat diffusion member 27 is 1
0ppm / ℃ or less, and the heat diffusion member 27 and the insulating substrate 1
It is desirable that the difference in the coefficient of thermal expansion between 0 is adjusted to 18.5 ppm / ° C or less.

The coefficient of thermal expansion of the heat diffusion member 27 according to the present invention is adjusted. FIG. 4 shows a schematic view of the heat diffusion member.
(a) is a schematic cross-sectional view showing an example of the heat diffusion member.
71-invar material 272-Cu material 271 has a three-layer structure. Depending on the desired coefficient of thermal expansion and thermal conductivity,
The thickness ratio of the Cu material 271 and the invar material 272 is adjusted.
Here, the Cu material 271 is selected mainly from the viewpoint of enhancing thermal conductivity, and the invar material 272 is selected from the viewpoint of controlling the coefficient of thermal expansion. As a substitute material for the invar material 272,
Iron, 42 alloy, etc. are selected. Although not shown in the figure, it is preferable that the surface of the heat diffusion member 27 is plated with Ni or the like. Further, (b) is a schematic sectional view showing another example of the heat diffusion member. As shown in the schematic plan view of (d), this is a flat plate composed of a Cu material 271 and an Invar material 272 which are alternately joined in a stripe shape. (c) is a schematic cross-sectional view showing another example of the heat diffusion member. This is as in the schematic plan views shown in (d) and (e),
The flat plate is laminated and integrated by rotating the stripe direction by 90 degrees. The number of stacked flat plates may be three or more as required.

The heat diffusion member 27 in the present invention is not limited to the composite material described in FIG. For example, Al
Alternatively, SiC powder, C powder, Si powder, SiC fibers, a composite material in which C fibers are dispersed in a Cu matrix, a composite material in which Cu powder and Mo or W powder are sintered, and the like can be cited as alternative materials. These alternative materials have isotropic physical properties.

Incidentally, the epoxy resin 3 in the present invention
1 plays a role for mechanical protection and hermetic sealing of mounted parts. Therefore, it is desirable that the epoxy resin 31 does not generate an excessive internal stress on the integrated surface with the substrate 10. The first reason is that mounted components (21, 21,
(22, 23, 24, 25, 26) are mounted by soldering, and if excessive internal stress is introduced into the alloy material 25, 25 'that fixes these parts, it will be caused by the temperature change during the subsequent operation. This is because the stress that occurs is superimposed, and thermal fatigue failure is likely to occur. The second reason is that when the epoxy resin 31 causes excessive internal stress on the integrated surface with the substrate 10, peeling occurs on the integrated surface, and the mounting components corrode due to the infiltration of water through this interface, This is because the normal circuit function of the semiconductor device 40 is impaired.

FIG. 5 is a graph showing the amount of warpage of an integrated product of an epoxy resin and an insulating substrate according to one embodiment of the present invention. Here, the size of the substrate 10 is 20.5 mm × 38 mm × 1.
5 mm, the maximum thickness of the epoxy resin 31 is about 2 mm. Further, the vertical axis of FIG. 5 is the warpage amount of the substrate 10 in the longitudinal direction,
A plus sign means a convex shape on the substrate 10 side, and a minus sign means a convex shape on the epoxy resin 31 side. The horizontal axis represents the coefficient of thermal expansion of the epoxy resin 31.

The warpage amount shows a positive large value as the coefficient of thermal expansion of the epoxy resin 31 increases.
On the other hand, the initial warpage amount of the substrate 10 is 25 μm. In the figure, considering the amount of warpage, in order to prevent the internal stress from being introduced into the interface, the amount of warpage after providing the epoxy resin 31 is approximated to the initial amount of warpage (preferably ± 10 μm).
Must be within). Judging from this point of view, it is desirable that the range indicated by R, that is, the coefficient of thermal expansion of the epoxy resin 31 is in the range of 13 to 21 ppm / ° C.

The silicone gel resin 32 according to the present invention is
It has a role of preventing moisture from entering through the epoxy resin 31 itself or an integrated surface with the substrate 10.

(Examples) The present invention will be described in detail with reference to Examples.

In this embodiment, a MOS as a heating element is used.
A semiconductor device equipped with the FET element substrate and the chip resistor will be described.

The insulating substrate 10 is, as shown in FIG. 1, an aluminum plate 1 having a thickness of 1.5 mm and an area of 40.7 mm × 22 mm.
A copper wiring layer 3 having a thickness of 70 μm is selectively formed on one of the main surfaces via an epoxy insulating resin layer 2 having a thickness of 150 μm.

MOS FET element substrate (7 mm × 7 mm, 4
21) are soldered onto the copper wiring layer 3 via the heat diffusion member 27. 70 μm thick Sn-5 wt% Sb is provided between the MOS FET element base 21 and the heat diffusion member 27.
Solder layer 25, and heat diffusion member 27 and insulating substrate 10
70 μm thick Pb-50 wt% Sn solder layer 2 between
They are fixed by 5 '. Heat diffusion member 27
(8 mm x 8 mm) has a thickness of 0.6 mm, and Cu material 271 (thickness: 0.0
2 mm) -Invar material 272 (thickness: 0.2 mm) -Cu material 271
It has a three-layer structure (thickness: 0.2 mm). On the other hand, the chip resistors (3.2 mm × 1.6 mm, 4 pieces) 22 are the copper wiring layers 3
An Sn-5 wt% Sb solder layer 25 is electrically conductively fixed on the top.

MOS FET element base 21 and copper wiring layer 3
An Al wire 26 having a diameter of 300 μm is ultrasonically bonded between them. Further, the terminal 24 is conductively fixed to the region of the copper wiring layer 3 by the solder layer 25. A resin case 33 is attached around the insulating substrate 10 by a resin adhesive.

The MOS FET element substrate 21, the heat diffusion member 27, the Al wire 26, and the chip resistor 22 are covered with an epoxy resin 31 whose thermal expansion coefficient is adjusted to 16 ppm / ° C., and the epoxy resin 31 is further silicone gel. Resin 32
It is covered with.

The semiconductor device thus obtained constitutes a power supply circuit composed of a MOS FET element 21 and a resistor 22, as shown in FIG. Here, the Al wire 26 plays a role of a fuse that is blown when an overcurrent is generated.

FIG. 7 is a graph showing changes in the thermal resistance of the MOS FET element mounting portion. Curve A in the figure is for the semiconductor device of this example, and curves B and C as comparative examples are for the case where the heat diffusion member is a Cu material and a Mo material, respectively. Also in the case of the comparative example, the constitution of the solder layers 25 and 25 ', and the epoxy resin 31 and the silicone gel resin 32
The configuration is similar to that of this embodiment.

The curve A shows no increase in thermal resistance in the test up to 20,000 temperature cycles. On the other hand, curves B and C show an increase in thermal resistance after 2000 times and 4000 times, respectively. In this way, in the case of this embodiment, the long life is obtained by (1) the solder layers 25, 2
5'has excellent thermal fatigue resistance, and (2)
Since the thermal expansion coefficient of the epoxy resin 31 is properly adjusted, in addition to being able to reduce the internal stress at the integrated interface with the substrate 10 and the soldering interface, (3) the thermal expansion coefficient of the thermal diffusion member 27. Is properly adjusted (semiconductor substrate 21 and heat diffusion member 27
Difference in thermal expansion coefficient between the thermal diffusion member 27 and the insulating substrate 10 is 16.5 ppm or less.
/ ° C. or less), the destruction of the solder layer due to modes A and B does not proceed so much, and as a result, the effect of extending the life of both joints 25 and 25 ′ is obtained.

On the other hand, in the case of the curve B (Cu thermal diffusion member),
Since the effects (1) and (2) described above are obtained, the life value itself is significantly improved as compared with the case of FIG. 3 (about 400 times). However, since the effect of (3) above cannot be obtained,
Mode B destruction (destruction between the heat diffusion member and the insulating substrate) progresses quickly, and the life value is significantly shorter than 20,000 times or more in this embodiment. Also in the case of the curve C (Mo heat diffusion member),
Since the effect of (2) is obtained, the life value is as shown in Fig. 3 (about 75
However, since the effect of (3) cannot be obtained, the destruction of mode A (destruction between the semiconductor substrate and the heat diffusion member) progresses quickly, and the life value is 40,000 of this embodiment. It is much less than the number of times.

[0046]

[Table 1]

Table 1 shows the durability performance of the semiconductor device by various tests. An epoxy resin 31 having a coefficient of thermal expansion of 6 to 25 ppm / ° C. is applied to the semiconductor device used in this test. In the temperature cycle test, the semiconductor device has −55 to 1
A temperature change of 50 ° C. is applied to trace the deterioration of the circuit function due to the destruction of the solder layers 25 and 25 ′. Coefficient of thermal expansion 6
In the range of up to 11 ppm / ° C. and in the case of 25 ppm / ° C., the circuit function is deteriorated by the temperature cycle of 5000 times or less. On the other hand, in the range of 13 to 21 ppm / ° C, no deterioration of the circuit function was observed in any of the samples even after applying the temperature cycle of 10,000 times or more.

Further, in the high temperature and high humidity bias test, the semiconductor device is subjected to an atmospheric stress of 85 ° C. and 85% RH, and a 6-bit gap is applied between the source and drain of the MOS FET element 21.
A DC voltage of 0 V is applied to track the deterioration of the electrical performance of the device 21. In the range of the coefficient of thermal expansion of 6 to 11 ppm / ° C. and the case of 25 ppm / ° C., deterioration occurred in 2000 hours or less. On the other hand, 13-21ppm / ℃
In the range of 1, no deterioration was observed in any of the samples by the test for 5000 hours or more.

When the above various tests are comprehensively evaluated, the desirable coefficient of thermal expansion of the epoxy resin 31 is 13 to 21 ppm.
It can be said that it is in the range of / ° C.

By the way, the present invention can be applied to other than the ranges described in the above embodiments. The epoxy resin 31 is a filler such as SiO ₂ (fused silica, crystalline silica) or Zn.
A phenol-curable epoxy resin containing O powder is used. In this case, the filler is added in an amount of 50 to 90%, but it is possible to select any composition depending on the desired coefficient of thermal expansion and the molding temperature. Even when a rubber-modified epoxy resin is used, its coefficient of thermal expansion is 13 to 21.
The effects of the present invention can be obtained as long as the range is ppm / ° C.

As the semiconductor element substrate 21, MOS FE is used.
In addition to the T element, IGBT (Insulated Gate Bipolar Transistor)
istor), a transistor, a thyristor, a diode, etc. can be applied, and the effect of the present invention can be enjoyed even when the base material is, for example, GaAs or SiC other than Si.

[0052]

As described above, according to the present invention, it is possible to provide a semiconductor device which is excellent in heat resistance fatigue resistance and airtightness of a fixed portion.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a semiconductor device of the present invention.

FIG. 2 is a characteristic diagram showing the thermal fatigue fracture resistance of an alloy material.

FIG. 3 is a characteristic diagram showing the thermal expansion coefficient dependence of the life of a solder joint in a semiconductor device, of a thermal diffusion member.

FIG. 4 is a schematic cross-sectional view of a heat diffusion member.

FIG. 5 is a graph showing a warp amount of an integrated product of an epoxy resin and an insulating substrate according to an example.

FIG. 6 is a diagram showing an electric circuit of a semiconductor device of the present invention.

FIG. 7 is a graph showing changes in thermal resistance of a MOS FET element mounting portion.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Aluminum plate, 2 ... Epoxy insulating resin layer, 3 ... Copper wiring layer, 10 ... Insulating substrate, 21 ... Semiconductor element base | substrate, 22
… Chip resistance, 23… Chip capacitor, 24… Terminal,
25, 25 '... Alloy material, solder layer, 26 ... Al wire,
27 ... Thermal diffusion member, 31 ... Epoxy resin, 32 ... Silicone gel resin, 271 ... Cu material, 272 ... Invar material.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI H01L 23/40 (72) Inventor Kenji Koyama 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Hitachi Ltd. Semiconductor Division ( 72) Inventor Toshiharu Niitsu 5-20-1, Kamisuimoto-cho, Kodaira-shi, Tokyo Inside Semiconductor Division, Hitachi, Ltd. (56) Reference JP 10-135377 (JP, A) JP 63-29562 (JP) , A) JP 59-113649 (JP, A) JP 10-118783 (JP, A) JP 7-201895 (JP, A) Actual flat 2-44339 (JP, U) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 23/29 H01L 21/52 H01L 23/31 H01L 23/36 H01L 23/373 H01L 23/40

Claims (3)

(57) [Claims] 1. A semiconductor substrate is mounted via a heat diffusion member on an insulating substrate having copper wiring formed on the main surface of an aluminum plate via an epoxy insulating layer, and the heat diffusion member is made of Cu.
A laminated structure of a material and an Invar material, the difference in coefficient of thermal expansion between the semiconductor substrate and the heat diffusion member is 10 ppm / ° C. or less, and
The thermal expansion coefficient difference between the heat diffusion member and the insulating substrate is 18.5 ppm.
/ ℃ is adjusted to, between the semiconductor substrate and the heat diffusion member 9 to 0w t% or more on the Sn, Sb, Ag, Zn, In,
A semiconductor device characterized by being fixed by an alloy material to which one or more kinds of metals selected from the group of Bi and Cu are added. 2. The thermal diffusion member according to claim 1, wherein the thermal diffusion member and the insulating substrate are fixed to each other by an alloy material containing 35 wt% to 60 wt% of Sn and the balance being substantially Pb. Semiconductor device. 3. A semiconductor device according to claim 1, wherein the semiconductor substrate is successively coated with an epoxy resin and a silicone gel resin, and the coefficient of thermal expansion of the epoxy resin is adjusted to 13 to 21 ppm / ° C. .