JPS5945996A - Vapor growth of semiconductor - Google Patents
Vapor growth of semiconductorInfo
- Publication number
- JPS5945996A JPS5945996A JP15376982A JP15376982A JPS5945996A JP S5945996 A JPS5945996 A JP S5945996A JP 15376982 A JP15376982 A JP 15376982A JP 15376982 A JP15376982 A JP 15376982A JP S5945996 A JPS5945996 A JP S5945996A
- Authority
- JP
- Japan
- Prior art keywords
- single crystal
- film
- silicon
- substrate
- polysilicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/02—Elements
- C30B29/06—Silicon
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
Landscapes
- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は表面に絶縁膜のパターンを有する単結晶シリコ
ン基板上に、シリコンエピタキシャル膜を気相で成長さ
せる方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for growing a silicon epitaxial film in a vapor phase on a single crystal silicon substrate having an insulating film pattern on its surface.
絶縁基板上の単結晶半導体膜を能動層として用いた集積
回路は、素子間の分離が容易であり、また寄生容量を低
減することかできることから高密度化、高速化に通しで
いる。絶縁基板上に単結晶半導体膜を形成する方法とし
ては、シリコンオンサファイアやシリコンオンスピネル
のように単結晶絶縁物基板上に単結晶半導体膜を形成す
る方法、非晶質絶縁基板上に多結晶あるいは非晶質のシ
リコンを堆積し、レーザ等のビームアニール法用いて再
結晶化する方法、非晶質絶縁基板上に多結晶あるいは非
晶質のシリコンを堆積し、ヒーターで溶かして再結晶化
する方法などがある。これらのうち、単結晶絶縁物基板
あるいけtit結晶絶縁股上にシリコンをエピタキシャ
ル成長させるヘテロエピタキシャル法は基本的には一層
のシリコンエピタキシャル膜を得る方法であり、単結晶
シリコンを絶縁物の上に形成することの1つの大きな狙
いであるデバイスの上に更にデバイスを積み重ねる、い
わゆるデバイスの三次元化を図る場合には適当でない。Integrated circuits using a single crystal semiconductor film on an insulating substrate as an active layer can be easily separated between elements, and parasitic capacitance can be reduced, allowing for higher density and higher speed. Methods of forming a single crystal semiconductor film on an insulating substrate include forming a single crystal semiconductor film on a single crystal insulator substrate such as silicon on sapphire or silicon on spinel, and forming a single crystal semiconductor film on an amorphous insulating substrate. Alternatively, a method of depositing amorphous silicon and recrystallizing it using a beam annealing method such as a laser, or depositing polycrystalline or amorphous silicon on an amorphous insulating substrate and melting it with a heater to recrystallize it. There are ways to do this. Among these, the heteroepitaxial method, in which silicon is epitaxially grown on a single-crystal insulator substrate or on top of a crystal insulator, is basically a method to obtain a single-layer silicon epitaxial film, and single-crystal silicon is formed on an insulator. It is not suitable for one of the major aims of stacking devices on top of each other, so-called three-dimensional devices.
また前述の方法のうち再結晶を利用する方法ではシード
を用いる方法にしてもシードを用いない方法にしても単
結晶領域の大きさは大きくても数ミクロンから数十ミク
ロンであり、それ以上の大きな単結晶膜を得るのは非常
に困難であるのが現状である。Furthermore, among the methods mentioned above, in the method using recrystallization, the size of the single crystal region is from several microns to several tens of microns at most, regardless of whether the method uses a seed or the method does not use a seed. At present, it is extremely difficult to obtain a large single crystal film.
シードを用いることができる場合に制限されるが、シリ
コン気相成長法によってもシードよシ大きな単結晶域を
得ることが可能である。この方法はビームアニール法に
くらべ、シリコンオンサファイアやシリコンオンスピネ
ルのようにバッチ処理が可能であること、及びビームア
ニール法のように積層構造にすることが可能である等両
者の利点を兼ね備えている。しかしながら、この方法は
通常のエピタキシャル条件で成長させればシード部分と
ほとんど同じくらいの大きさの単結晶域しか得られない
。また、表面KSi02膜のパターンを備えた単結晶シ
リコン基板を用いて5tO2膜上にはSt を堆積させ
ずシード部分即ち基板の露出部分からシリコン単結晶膜
が横方向す寿わち5iO1膜上へ拡大していくという成
長方法を利用すると、必要な寸法(横方向)゛の単結晶
域を得るのにはその2/3位のエビ厚さを必要とする欠
点があった。Although it is limited to cases where seeds can be used, it is also possible to obtain a larger single crystal region by silicon vapor phase epitaxy than by seeds. Compared to the beam annealing method, this method combines the advantages of both methods, such as batch processing like silicon on sapphire and silicon on spinel, and the ability to create a laminated structure like the beam annealing method. There is. However, if this method is grown under normal epitaxial conditions, only a single crystal region almost as large as the seed portion can be obtained. In addition, using a single crystal silicon substrate with a pattern of KSi02 film on the surface, without depositing St on the 5tO2 film, the silicon single crystal film is grown laterally from the seed part, that is, the exposed part of the substrate, that is, on the 5iO1 film. When the growth method of enlarging is used, there is a drawback that in order to obtain a single crystal region of the required size (in the lateral direction), a thickness of approximately 2/3 of the required size (in the lateral direction) is required.
この理由は8102と争結晶シリコンの接触角が大きく
、伸びようとするシリコン単結晶に対しSin。The reason for this is that the contact angle between 8102 and the silicon crystal is large, and the silicon single crystal that is about to stretch has a large contact angle with the silicon.
がそれを防げる働きをするためと考えられる。This is thought to be because it acts to prevent this.
本発明は、このような、シードを用臂た気相成長法で絶
縁膜上へ単結晶シリコンを成長させる上での問題を解決
し、大面積の単結晶域を得る方法を提供するものである
。すなわち、開口部を有するSin、膜によって被覆さ
れたシリコン基板に対し、単結晶シリコンの成長前にシ
ード部分には単結晶シリコンを、Sin、、膜上にはポ
リシリコン膜を気相成長法を用いて薄くコートし、その
後厚さ方向の成長速度および化学平衡条件を、圧力、温
度、5t10A?比を適当な条件に設定することにより
、厚さ方向の単結晶シリコンの堆積速度よりはるかに速
い横方向の単結晶域の拡大速度を得るものである。The present invention solves these problems in growing single crystal silicon on an insulating film by vapor phase growth using seeds, and provides a method for obtaining a large single crystal region. be. That is, for a silicon substrate covered with a Sin film having an opening, before growing single crystal silicon, single crystal silicon is deposited on the seed portion, and a polysilicon film is grown on the Sin film using a vapor phase growth method. After that, the growth rate in the thickness direction and the chemical equilibrium conditions were adjusted using pressure, temperature, 5t10A? By setting the ratio to an appropriate condition, it is possible to obtain a rate of expansion of the single crystal region in the lateral direction which is much faster than a deposition rate of single crystal silicon in the thickness direction.
以下に本発明を実施例に従って詳細に説明する。The present invention will be explained in detail below according to examples.
実施例
納1図〜第3図は本発明の詳細な説明する図ソ、シード
となるシリコン単結晶基板からSin。Embodiment Figures 1 to 3 are detailed illustrations of the present invention.
膜上に単結晶シリコン膜を成長させるときの主な工程に
おける模式的断面を順次示す図である。まずP−(10
010zウエーハ1の表面をWe を酸化し、厚さ約5
00Xの酸化膜2を形成した。−次に、通常のフォトリ
ソグラフィーの技術によってウェーハー全面に直径10
μmφ縦横のピクチ1001trnで基板シリコンを露
出させた(第1図)。このときシリコンの露出面積はウ
ェハー片面の全面積に対して3.14%であった。次に
、赤外線加熱減圧エピタキシャル成長装置にローディン
グしポリシリコン膜3を堆積させた(第2図)。堆積条
件は、圧力50TO几R,J(2キヤリア一ガス流量5
ol/min 、 S iH2012ンースガス流−1
ii 600 c c/1nin 。FIG. 2 is a diagram sequentially showing schematic cross-sections in main steps when growing a single crystal silicon film on a film. First, P-(10
The surface of the 010z wafer 1 is oxidized with We to a thickness of about 5
An oxide film 2 of 00X was formed. -Next, the entire surface of the wafer is coated with a diameter of 10 mm using conventional photolithography techniques.
The substrate silicon was exposed by a picture 1001trn of μmφ length and width (FIG. 1). At this time, the exposed area of silicon was 3.14% of the total area of one side of the wafer. Next, it was loaded into an infrared heating and reduced pressure epitaxial growth apparatus to deposit a polysilicon film 3 (FIG. 2). The deposition conditions were: pressure 50 TO R, J (2 carriers - gas flow rate 5
ol/min, S iH2012 gas flow-1
ii 600cc/1nin.
基板温度825℃であった。このときSin、膜上には
ポリシリコン膜が堆積するが、シード部分のシリコン基
板上には単結晶膜が成長する。単結晶膜の部分で測定し
て堆積厚さを約500Xとしだ後堆積を中止し、設定条
件を圧力50 ’l’oI’tR,H2キャリアーガス
流量851/min 、 S iH20131ソースガ
ス流量560 cc/min 、 Hog流fl O,
713/mln、基板温度950℃にした。この設定条
件で単結晶シリコン膜4を成長させると堆積速度は0.
06μm/minであった。とのとき横方向の単結晶域
の拡大速度は約0.29〜0.32μm/minであっ
た。このときウェーハー断面の透過電子顕微鏡観察によ
ねげ、シリコン単結晶膜の下のポリシリコンHJは単結
晶シリコン膜5となっていた(第3図)。本発明の場合
5i02との界面における接触角が問題に々らないため
に、横方向の単結晶域拡大速度が増した他に、エピシリ
コン単結晶膜の拡大と共にポリシリコン膜が単結晶化す
ることが拡大速度の増大に寄与していると考えられる。The substrate temperature was 825°C. At this time, a polysilicon film is deposited on the Sin film, but a single crystal film is grown on the silicon substrate at the seed portion. After measuring the deposition thickness on the single crystal film to about 500X, the deposition was stopped, and the setting conditions were: pressure 50'l'oI'tR, H2 carrier gas flow rate 851/min, SiH20131 source gas flow rate 560 cc. /min, Hog style fl O,
713/mln, and the substrate temperature was 950°C. When the single crystal silicon film 4 is grown under these setting conditions, the deposition rate is 0.
The speed was 06 μm/min. The expansion rate of the single crystal region in the lateral direction was about 0.29 to 0.32 μm/min. At this time, transmission electron microscope observation of the cross section of the wafer revealed that the polysilicon HJ under the silicon single crystal film had become a single crystal silicon film 5 (FIG. 3). In the case of the present invention, since the contact angle at the interface with 5i02 is not satisfactory, not only the speed of lateral single crystal region expansion increases, but also the polysilicon film becomes single crystal as the episilicon single crystal film expands. It is thought that this contributes to the increase in the expansion speed.
シード部分から離れた部分にはポリシリコン膜の上には
やはりポリシリコン膜が堆積した。得られる単結晶域の
大きさは成長条件、どくにエピシリコン膜の成長速バr
に依存した。す寿わちあらかじめつけてポリシリコン膜
およびその上に堆積するポリシリコンの合計厚さが厚く
なり、単結晶膜の拡大と共に単結晶化しにくくなると急
激に拡大速度が遅くなった。従って、より大きな単結晶
域を得るには、ポリシリコン膜をできるだけ簿くかつ均
一にあらかじめ堆積させておくと共に、単結晶シリコン
膜の形成時にその成長速度をできるだけ遅くする方が良
い。本実施例における成長速度、0.06μm/min
、では30分の成長時間でシード部分の境界から8.7
〜9.Fμm横方向に伸びた単結晶域が得られた。A polysilicon film was still deposited on the polysilicon film in a portion away from the seed portion. The size of the single crystal region obtained depends on the growth conditions, especially the growth rate of the episilicon film.
depended on. In other words, the total thickness of the pre-applied polysilicon film and the polysilicon deposited thereon became thicker, and as the single crystal film expanded, it became difficult to form a single crystal, and the expansion speed suddenly slowed down. Therefore, in order to obtain a larger single crystal area, it is better to deposit the polysilicon film as thinly and uniformly as possible in advance and to slow down the growth rate as much as possible when forming the single crystal silicon film. Growth rate in this example: 0.06 μm/min
, the growth time of 30 minutes is 8.7 from the border of the seed part.
~9. A single crystal region extending in the lateral direction by Fμm was obtained.
また、電子顕微鐘観察の結果によれば、 5in2と
単結晶化したポリシリコン膜の界面から発生している多
数の積層欠陥のうち、その多くはエピシリコン璽結晶膜
との界面セ止っており、エビ膜の結晶性が向上していた
。Furthermore, according to the results of electron microscope observation, many of the stacking faults that occur at the interface between the 5in2 and the single-crystalline polysilicon film are stuck at the interface with the episilicon crystal film. , the crystallinity of shrimp membranes was improved.
本実施例では酸化膜の形成方法としてWe t 9化法
を用いたが、他の酸化膜形成法でも結果は同様であシ、
#化方法の違いは全く問題ではない。本実施例ではSi
n、膜厚さを500にとしたが、絶縁膜厚さに制約はな
い。本実施例では絶縁膜として熱酸化8i02膜を用い
たがs CI V D 810□膜あるいはS i 3
N4膜でも大きな差はない。又本実施例ではポリシリ
コン膜ど単結晶シリコン膜の形成を同時に行った。これ
を分す、コし、ポリシリコン膜をコートしてからフ=+
−tリソグラフィー技術で基板シリコンな露出させてか
ら単結晶シリコン膜を堆積させても同様の納采を?する
ことかできるが、プロセスの数が増すため工業的には本
実施例の方が適している。また、シード部分の側壁にS
in。In this example, the Wet9 method was used as the method for forming the oxide film, but the results may be similar with other oxide film forming methods.
The difference in # encoding method is not a problem at all. In this example, Si
n, and the film thickness was set to 500, but there is no restriction on the thickness of the insulating film. In this example, a thermally oxidized 8i02 film was used as the insulating film;
There is no big difference even with N4 film. Further, in this example, a polysilicon film and a single crystal silicon film were formed at the same time. Separate this, coat it with a polysilicon film, and then
- Is the same solution possible even if the substrate silicon is exposed using lithography technology and then a single crystal silicon film is deposited? However, this embodiment is more suitable from an industrial perspective because the number of processes increases. Also, S on the side wall of the seed part.
in.
が露出しているだめ、その部分の結晶性が悪くなる。If it is exposed, the crystallinity of that part will deteriorate.
以上述べたように本発明は、従来の気相成長法によるシ
リコンオンインシュレーターの問題点であった5in2
とSt の接触角か大きいことによる横方向の拡大速度
が遅いこと、Sin、上のエピシリコン膜の結晶イ生の
悪さを解決するものであり、その工業的価値は大きい。As described above, the present invention solves the problems of silicon-on-insulators using the conventional vapor phase growth method.
This solution solves the problem of slow lateral expansion rate due to the large contact angle between Si and St, and poor crystallization of the episilicon film on Sin and St, and its industrial value is great.
第1図〜第3図は本発明の実施レリを説明するだめの模
式的断面図で、1はシリコン単結晶基板、2は酸化シリ
コン膜、3はポリシリコン膜、4はエヒタキシャル単結
晶膜、5はポリシリコンfil、3がエビ成長中に単結
晶化したシリコン単結晶膜である。
3+I 凹
−)P 2 閑
勿3 図1 to 3 are schematic cross-sectional views for explaining the implementation of the present invention, in which 1 is a silicon single crystal substrate, 2 is a silicon oxide film, 3 is a polysilicon film, 4 is an epitaxial single crystal film, 5 is a polysilicon film, and 3 is a silicon single crystal film that has been monocrystalized during shrimp growth. 3+I concave-)P 2 Kannazu 3 Figure
Claims (1)
、次いで気相成長法を用いて該絶縁11−上にはポリシ
リコン膜を、前記開口部に露出した基板上には単結晶シ
リコン膜を同時に堆積させ、次いで気相成長法によって
少なくとも前記単結晶シリコン膜上及びその周囲の前記
絶縁膜上に単結晶シリコン膜を堆積し、該堆積中に該単
結晶シリコン膜の下の前記ポリシリコン膜を単結晶化す
ることを特徴とする半導体の気相成長方法。An insulating film having an opening is formed on a silicon single crystal substrate, and then a polysilicon film is formed on the insulating film 11 by using a vapor phase growth method, and a single crystal silicon film is formed on the substrate exposed in the opening. is simultaneously deposited, and then a single crystal silicon film is deposited by vapor phase growth at least on the single crystal silicon film and on the surrounding insulating film, and during the deposition, the polysilicon under the single crystal silicon film is deposited. A semiconductor vapor phase growth method characterized by forming a film into a single crystal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15376982A JPS5945996A (en) | 1982-09-03 | 1982-09-03 | Vapor growth of semiconductor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15376982A JPS5945996A (en) | 1982-09-03 | 1982-09-03 | Vapor growth of semiconductor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5945996A true JPS5945996A (en) | 1984-03-15 |
Family
ID=15569729
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15376982A Pending JPS5945996A (en) | 1982-09-03 | 1982-09-03 | Vapor growth of semiconductor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5945996A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4861418A (en) * | 1986-03-07 | 1989-08-29 | Kozo Iizuka, Director General, Agency Of Industrial Science And Technology | Method of manufacturing semiconductor crystalline layer |
JPH02191319A (en) * | 1988-10-17 | 1990-07-27 | Sanyo Electric Co Ltd | Method of forming soi structure |
JPH02211616A (en) * | 1989-02-10 | 1990-08-22 | Sanyo Electric Co Ltd | Formation of soi structure |
US5364815A (en) * | 1987-03-27 | 1994-11-15 | Canon Kabushiki Kaisha | Crystal articles and method for forming the same |
JP2007329200A (en) * | 2006-06-06 | 2007-12-20 | Toshiba Corp | Method of manufacturing semiconductor device |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5544789A (en) * | 1978-09-27 | 1980-03-29 | Nec Corp | Formation of mono-crystal semiconductor layer |
JPS5635412A (en) * | 1979-08-31 | 1981-04-08 | Toshiba Corp | Manufacture of single crystal semiconductor film |
-
1982
- 1982-09-03 JP JP15376982A patent/JPS5945996A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5544789A (en) * | 1978-09-27 | 1980-03-29 | Nec Corp | Formation of mono-crystal semiconductor layer |
JPS5635412A (en) * | 1979-08-31 | 1981-04-08 | Toshiba Corp | Manufacture of single crystal semiconductor film |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4861418A (en) * | 1986-03-07 | 1989-08-29 | Kozo Iizuka, Director General, Agency Of Industrial Science And Technology | Method of manufacturing semiconductor crystalline layer |
US5364815A (en) * | 1987-03-27 | 1994-11-15 | Canon Kabushiki Kaisha | Crystal articles and method for forming the same |
JPH02191319A (en) * | 1988-10-17 | 1990-07-27 | Sanyo Electric Co Ltd | Method of forming soi structure |
JPH02211616A (en) * | 1989-02-10 | 1990-08-22 | Sanyo Electric Co Ltd | Formation of soi structure |
JP2007329200A (en) * | 2006-06-06 | 2007-12-20 | Toshiba Corp | Method of manufacturing semiconductor device |
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