JPS59128292A - Method for crystallizing thin film - Google Patents

Method for crystallizing thin film

Info

Publication number
JPS59128292A
JPS59128292A JP33783A JP33783A JPS59128292A JP S59128292 A JPS59128292 A JP S59128292A JP 33783 A JP33783 A JP 33783A JP 33783 A JP33783 A JP 33783A JP S59128292 A JPS59128292 A JP S59128292A
Authority
JP
Japan
Prior art keywords
thin film
substrate
film
crystallizing
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP33783A
Other languages
Japanese (ja)
Other versions
JPH0442358B2 (en
Inventor
Masafumi Shinpo
新保 雅文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP33783A priority Critical patent/JPS59128292A/en
Publication of JPS59128292A publication Critical patent/JPS59128292A/en
Publication of JPH0442358B2 publication Critical patent/JPH0442358B2/ja
Granted legal-status Critical Current

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Classifications

    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B1/00Single-crystal growth directly from the solid state
    • C30B1/02Single-crystal growth directly from the solid state by thermal treatment, e.g. strain annealing
    • C30B1/023Single-crystal growth directly from the solid state by thermal treatment, e.g. strain annealing from solids with amorphous structure

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  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Thermal Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

PURPOSE:To crystallize semiconductor films left on the flat surface of a substrate in the form of rectangles or stripes, by depositing an insulating film such as a silicon oxide film or a silicon nitride film and by carrying out beam annealing. CONSTITUTION:Thin films 2 of an amorphous or polycrystalline semiconductor are left on a flat glass substrate 1 in the form of rectangles each having <=mum width. An insulating film 4 having 0.1-1mum thickness such as a silicon oxide film or a silicon nitride film is deposited on the whole surface of the substrate 1 by CVD or other method, and beam annealing with laser or electron beams is carried out to crystallize the thin films 2. At this time, edges 5 of the films 2 act as positions where nuclei for growth by recrystallization are stable, so the thin films 2 are converted into crystallized thin films 20 each consisting of coarse grains.

Description

【発明の詳細な説明】 本発明は半導体薄膜の結晶化方法に関し、特にs、6エ
(Sem1conductor On工n5u1ato
r)構造実現の方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for crystallizing a semiconductor thin film, and in particular to a method for crystallizing a semiconductor thin film.
r) Concerning the method of realizing the structure.

S’OIは半導体装置の筒性能化、面密度化、低価格化
を可能にする技術として注目されている。
S'OI is attracting attention as a technology that enables improved cylindrical performance, increased areal density, and lower cost of semiconductor devices.

その技術には、例えば半導体単結晶基板上の酸化l模上
の半導体薄膜を基板を種結晶として饅化膜上に結晶化す
る方法、グラフオエピタキシーなどの方法がある。グラ
フオエピタキシーはガラス等の基板上に単結晶成長層が
得られるという画期的なもので、第1図にての工程例を
示す。第1図(a)は例えばガラス基板1の表面に溝5
を形成した断面を示す。溝6の形状は結晶化する薄膜の
結晶方位によって所望のものが選ばれる。ψ1」えは、
(100)のときには矩形やヌトライグ状の平面形状、
矩形の断面形状に義はれる。鉤の幅は2〜50μmに、
深さは13.1〜1μmにm%のフォトリソグラフイド
ライエッチなとで作成gtする。次に、第1図(b)の
如く基板1辰面に非晶質シリコン(a−8i)や多結晶
シリコン等の半導体薄膜2を堆積する。
Techniques for this include, for example, a method in which a semiconductor thin film on an oxide model on a semiconductor single-crystal substrate is crystallized on an oxidized film using the substrate as a seed crystal, and a method such as graph-o-epitaxy. Graphoepitaxy is an epoch-making method that allows a single crystal growth layer to be obtained on a substrate such as glass, and an example of the process is shown in FIG. FIG. 1(a) shows, for example, grooves 5 on the surface of a glass substrate 1.
A cross-section of the formed part is shown. A desired shape of the groove 6 is selected depending on the crystal orientation of the thin film to be crystallized. ψ1”Eha,
When it is (100), it has a rectangular or nutrig-like planar shape,
It has a rectangular cross-sectional shape. The width of the hook is 2 to 50 μm,
The depth is 13.1 to 1 μm and is created by photolithographic dry etching at m%. Next, as shown in FIG. 1(b), a semiconductor thin film 2 of amorphous silicon (a-8i), polycrystalline silicon, or the like is deposited on the side surface of the substrate 1.

さらに、レーザ、鬼子線、ラング元、ヒーター等を用い
たいわゆるビームアニール法で薄膜を急速に溶融、再結
晶化する。その際、基板1の溝5が再結晶成長核を安定
させる働きをして、再結晶薄膜20の結晶方向がぞろう
というものである(第1図(C)参照)。
Furthermore, the thin film is rapidly melted and recrystallized by a so-called beam annealing method using a laser, Oniko ray, Lang source, heater, etc. At this time, the grooves 5 of the substrate 1 function to stabilize the recrystallized growth nuclei, so that the crystal direction of the recrystallized thin film 20 is aligned (see FIG. 1(C)).

しかしながら、この方法では、まず基板1に形成する溝
3の深さを制御するのにエンチング時間によらなければ
いけないこと、全面を一度に結晶化するため薄膜2の歪
が大きく、場合によればクランクが入ってし1うことな
ど問題がある。
However, in this method, the depth of the groove 3 formed in the substrate 1 must be controlled by etching time, and since the entire surface is crystallized at once, the strain in the thin film 2 is large, and in some cases There are problems such as the crank not engaging.

本発明は、叙上の問題点に鑑みなされたものであシ、容
易に結晶化された半導体薄膜を得ることを目的としてい
る。本発明においては、平坦な表面をMする基板上に、
半導体薄膜を矩形やヌトライズ状に残し、さらに吊化硅
素膜や窒化硅索模の様な絶縁膜を堆積し、ビームアニー
ルすることによって半導体薄膜を結晶化しようとするも
のである。この際、牛導体薄膜端部の絶縁膜がグラフオ
エピタキシーの基板の溝と同様な作用をするので成長核
の結晶方向をそ・うえることが可能になる。
The present invention was made in view of the above-mentioned problems, and an object of the present invention is to obtain a semiconductor thin film that is easily crystallized. In the present invention, on a substrate having a flat surface,
This method attempts to crystallize the semiconductor thin film by leaving the semiconductor thin film in a rectangular or nutrified shape, then depositing an insulating film such as a suspended silicon film or a silicon nitride cord pattern, and beam annealing. At this time, the insulating film at the end of the conductor thin film acts in the same manner as the grooves in the substrate of graphite epitaxy, making it possible to change the crystal direction of the growth nuclei.

以下に図面を参照しながら本発明を詳バする。The present invention will be described in detail below with reference to the drawings.

第2図は、本発明による薄膜の結晶化方法ジこついての
各工程毎の模式図を示す。第2図(a)は模式的平面図
で、パイレツクスや石英等のガラス基板1の上に、a 
−Si や多結晶Si の半導体薄膜2を矩形状に残し
たものである。基板1には前述のガラスの他に、絶R膜
で被覆した81等の半導体ウェハ、子テンレヌ。乍化ア
ルミニウム堂その化合物などを目的に応じて使うことが
できる。薄膜2は、第2図(a)の様にそろった矩形に
限らす各辺が平行もしくはip交する矩形の各種の組み
合わせや種々の太ささ、または7トライプ状のものが使
える。その揚台、薄膜2の少なくとも一万の幅はグラフ
オエピタキシーの溝の幅程度例えば50μm以下に選り
:れる。後工程の再結晶イヒのしやすさ7J為らいえば
、この幅は狭い程望廿しく最大2−・10μmが選ばれ
る。薄膜2の端面5は、基板1表面と垂直である程望ま
しく、イオンエッチ、反応性イオンエッチなどの方法で
薄膜2は選択エッチきれる。この際、基板1と薄膜2の
物質が異なるので選択エッチ比が大きくとれfcす、自
動的にエッチ終点検出が可能となる利点がある。薄膜2
の厚みは、グラフオエピタキシーにおける溝の深さ程度
が望ましく、例えばo、 1〜1.11μmiC選ばね
、る。絹2図(b)には、第2図(a)の如き基板1上
に全面絶縁膜4を堆積した断面を示す。絶縁@4は通常
酸化w<5jo2)や窒化膜、もしくはその多層膜が使
われ、CVD等でo、 1〜1μm程度の厚みに形成さ
れる。この絶縁膜4の堆積によって、薄@2の端面5に
は絶縁物の壁ができたことになり、グラフオエピタキシ
ーの溝端部の働きを成ス。絶縁膜4け、′半導体′vw
膜2が溶融しても変形しにくいもの、ま′fcldニア
ニールビームに対して透明なものが4寸しく、他に酸化
アルミニウム等も使うことができる。第2図(b)の工
程の後、ビームアニールすると、薄膜2は結晶化して一
結晶i嗅20.!:□なる(第2図(C))。ビームア
ニールは前述の如くレーザー(cwiたはバルク)、ラ
ンプ、ヒータ、電子線等が有効で、薄膜2を一度溶融し
て再結晶化する必要がめる。その際、絶縁膜4と薄膜2
端面5が再結晶成長核の安定位置として動くため、薄膜
2は粒径のJ、り大きい結晶薄膜2oに変換する。場合
によれば島状のN映2が全部単結晶化することができ、
その場合、薄膜の幅が10μm以]が4首しい。その後
、島状結晶漕1fi 20 tK−トランジヌタ等牛導
体装置をつくり込み、SOI構造のICが実現できる。
FIG. 2 shows a schematic diagram of each step of the thin film crystallization method according to the present invention. FIG. 2(a) is a schematic plan view, in which a
-Si or polycrystalline Si semiconductor thin film 2 is left in a rectangular shape. In addition to the above-mentioned glass, the substrate 1 includes a semiconductor wafer such as No. 81 coated with an anti-reflection film, and a semiconductor wafer. Compounds of aluminum chloride and the like can be used depending on the purpose. The thin film 2 is limited to a rectangular shape as shown in FIG. 2(a), but various combinations of rectangular shapes with parallel or ip-intersecting sides, various thicknesses, or a seven-tripe shape can be used. The width of at least 10,000 of the thin film 2 is selected to be about the width of a graphite epitaxy groove, for example, 50 μm or less. Considering the ease of recrystallization in the post-process 7J, the narrower the width, the more desirable it is, and a maximum of 2-10 μm is selected. It is preferable that the end surface 5 of the thin film 2 be perpendicular to the surface of the substrate 1, and the thin film 2 can be selectively etched by a method such as ion etching or reactive ion etching. At this time, since the substrate 1 and the thin film 2 are made of different materials, there are advantages that a large selective etch ratio can be achieved and that the etch end point can be automatically detected. Thin film 2
The thickness is desirably about the depth of a groove in graphoepitaxy, and is selected, for example, from 1 to 1.11 μm. FIG. 2(b) shows a cross section of a substrate 1 as shown in FIG. 2(a) with an insulating film 4 deposited over the entire surface. The insulation @4 is usually made of oxide w<5jo2), nitride film, or a multilayer film thereof, and is formed to a thickness of about 1 to 1 μm by CVD or the like. By depositing this insulating film 4, an insulating wall is formed on the end face 5 of the thin@2, which functions as the groove end of graphoepitaxy. 4 insulating films, 'semiconductor'vw
A material that does not easily deform even when the film 2 is melted, or a material that is transparent to the fcld near-anneal beam is suitable, and aluminum oxide or the like may also be used. After the process shown in FIG. 2(b), when beam annealing is performed, the thin film 2 is crystallized into a single crystal. ! : becomes □ (Figure 2 (C)). As mentioned above, beam annealing is effective using a laser (CWI or bulk), a lamp, a heater, an electron beam, etc., and it is necessary to melt the thin film 2 once and recrystallize it. At that time, the insulating film 4 and the thin film 2
Since the end face 5 moves as a stable position for recrystallization growth nuclei, the thin film 2 transforms into a crystalline thin film 2o whose grain size is J larger. In some cases, all of the island-shaped N-2 can be made into a single crystal,
In that case, the width of the thin film is preferably 10 μm or more. Thereafter, a conductor device such as an island crystal cell 1fi 20 tK-transinuta is fabricated, and an IC having an SOI structure can be realized.

本発明は、さらに次の様な発展もある。第2図(C)の
工程の後、絶縁膜4を除去してさらに簾2半導体薄膜(
a−8j、または多結晶5i)12を堆積する(第2図
(d))。必要に応じ第2洩膜12と結晶薄膜20とは
別の不純物または異なる密度にドーピングされていても
よいし、結晶薄膜2oに選択的に不純物添加を行なった
後でもよい。その後、第2図(θ)に示す様VC、アニ
ールによって結晶薄膜20を成長核として第1薄嗅12
を結晶化し、基板1上全而に結晶薄膜22を形成する。
The present invention has further developments as follows. After the process shown in FIG. 2(C), the insulating film 4 is removed and the semiconductor thin film 2 (
a-8j, or polycrystalline 5i) 12 (FIG. 2(d)). If necessary, the second leakage film 12 and the crystalline thin film 20 may be doped with different impurities or at different densities, or the crystalline thin film 2o may be doped with impurities selectively. Thereafter, as shown in FIG. 2 (θ), the first thin film 12 is grown using the crystal thin film 20 as a growth nucleus by VC and annealing.
is crystallized to form a crystal thin film 22 all over the substrate 1.

アニールは前述のビーム照射または熱炉アニールが使え
、必ずし溶融する必要がなく固相エピタキシーにより第
2薄嗅12を結晶化できる。溶融する場合は、結晶化薄
1臭20の少なくとも1部が固体で残る様、ビーム波長
、出力、時間、膜厚が選はれる。島状結晶薄1漠20の
間隔は通常この薄膜200幅と同程度もしくはそれ以下
に選ばれ、狭い程、第2薄膜12の結晶化のアニールに
要する時間、結晶性が良好となる。このアニールは前記
幅が10μmのとき例えばレーザアニールする場合、A
u0Wレーザーでヌポント径50μmル−ザ出力10W
1ス糸ヤン速度1Q □ mm/see で行なえるし
、熱炉アニールでは例えば水素中で1100℃30分で
行える。本発明によれば、第1回目ビームアニールによ
って薄膜2を結晶化する際、薄膜2は島状に分かれてい
るので結晶化薄Il#¥20に生じる歪は小さく、クラ
ンク等の欠陥が発生しにくい。また、第2回目のアニー
ルにより第2薄嘆12を結晶化する場合、同相エビによ
れば温度を低くすることができるので歪の発生はやはり
少なく、たとえ基板上全面に半導体薄膜を結晶化しても
クランク等の欠陥が生じにくい利点かある。また、例と
して、Slを主に述べてきたが、[11−4,II−V
1等他の半導体材料にも適用される。
For annealing, the aforementioned beam irradiation or thermal furnace annealing can be used, and the second thin film 12 can be crystallized by solid phase epitaxy without necessarily needing to be melted. In the case of melting, the beam wavelength, output, time, and film thickness are selected so that at least a part of the crystallized thin 1 odor 20 remains as a solid. The spacing between the island crystal thin films 1 and 20 is usually selected to be about the same or smaller than the width of the thin film 200, and the narrower the distance, the better the time required for annealing the crystallization of the second thin film 12 and the better the crystallinity. This annealing is performed when the width is 10 μm, for example, when laser annealing is performed, A
U0W laser with a diameter of 50μm and a laser output of 10W
It can be carried out at a yarn yarn speed of 1Q □ mm/see, and thermal furnace annealing can be carried out, for example, in hydrogen at 1100° C. for 30 minutes. According to the present invention, when the thin film 2 is crystallized by the first beam annealing, the thin film 2 is divided into islands, so the strain that occurs in the crystallized thin Il#20 is small, and defects such as cranks do not occur. Hateful. In addition, when crystallizing the second thin film 12 by the second annealing, the temperature can be lowered according to the in-phase shrimp, so there is less distortion, even if the semiconductor thin film is crystallized over the entire surface of the substrate. It also has the advantage that defects such as cranks are less likely to occur. In addition, as an example, although we have mainly discussed Sl, [11-4, II-V
It also applies to other semiconductor materials such as 1st class.

本発明にエリ、SOI構造の実現が比較的容易に行なえ
るので、半導体装置の性能向上、集積度向上、低価格化
が実現されるため、工業的に非常に重要である。
The present invention is industrially very important because it is relatively easy to realize an SOI structure, which improves the performance, increases the degree of integration, and lowers the cost of semiconductor devices.

【図面の簡単な説明】[Brief explanation of the drawing]

嶋1図(a)〜(c)は従来のグラフオエピタキシーの
工程例を説明するための断面図。 第2図(a)〜(、)は本発明の詳細な説明するだめの
図で、第2図(a)は平jlllJ図で99、第2図(
b) 〜(e)は断面図である。 1・・・ガラ7基板、  2・・・半導体薄膜、5・・
・溝、      4・・・絶縁模、5・・・薄膜端面
、    20・・・結晶化薄1虞、12・・・第2半
導体薄膜。 第 Im (α゛) 閣 Cb) (C) 第2  L、:i ″′−I
Shima 1 Figures (a) to (c) are cross-sectional views for explaining an example of a conventional graphoepitaxy process. Figures 2(a) to 2(,) are diagrams for explaining the present invention in detail.
b) to (e) are cross-sectional views. 1... Glass 7 substrate, 2... Semiconductor thin film, 5...
- Groove, 4... Insulating pattern, 5... Thin film end face, 20... Crystallized thin film, 12... Second semiconductor thin film. No. Im (α゛) Cabinet Cb) (C) No. 2 L, :i ″′-I

Claims (2)

【特許請求の範囲】[Claims] (1)  非晶質もしくは多結晶半導体薄1漠を50μ
m以下の幅を有するヌトライプ状もしくは矩形に島状に
前記薄膜と異なる物質から成る基板の表面に残す工程、
前記薄膜及び基板上に絶縁膜を堆積する工程、光線もし
くは電子線もしく(は熱線等のビームを照射することに
より前記薄膜を溶融し再結晶化する際に前記薄膜と前記
絶縁膜の境界部の少なくとも一部を成長核形成の安定位
置として作用せしめ前記薄膜の結晶化を行なう工程とよ
り成る薄膜の結晶化方法。
(1) 50 μm of amorphous or polycrystalline semiconductor thin film
a step of leaving a nutripe-like or rectangular island-like shape having a width of m or less on the surface of a substrate made of a substance different from the thin film;
In the step of depositing an insulating film on the thin film and the substrate, the boundary between the thin film and the insulating film is A method for crystallizing a thin film, comprising the step of crystallizing the thin film by causing at least a portion of the thin film to act as a stable position for forming growth nuclei.
(2)  前記薄膜の結晶化の後前記絶縁嗅を除去する
工程、さらに非晶質もしくは多結晶の第2半導体薄li
!Qを堆積する工程、ビーム照射もしくはアニールによ
って前記結晶化した薄膜を核として前記第2薄嗅を結晶
化する工程とJ:り成る特許請求の範囲第1項記載の薄
膜の結晶化方法。
(2) removing the insulating layer after crystallizing the thin film, and further adding a second semiconductor thin film that is amorphous or polycrystalline;
! The method for crystallizing a thin film according to claim 1, comprising: depositing Q, crystallizing the second thin film using the crystallized thin film as a nucleus by beam irradiation or annealing;
JP33783A 1983-01-05 1983-01-05 Method for crystallizing thin film Granted JPS59128292A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33783A JPS59128292A (en) 1983-01-05 1983-01-05 Method for crystallizing thin film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33783A JPS59128292A (en) 1983-01-05 1983-01-05 Method for crystallizing thin film

Publications (2)

Publication Number Publication Date
JPS59128292A true JPS59128292A (en) 1984-07-24
JPH0442358B2 JPH0442358B2 (en) 1992-07-13

Family

ID=11471067

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33783A Granted JPS59128292A (en) 1983-01-05 1983-01-05 Method for crystallizing thin film

Country Status (1)

Country Link
JP (1) JPS59128292A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60260492A (en) * 1984-06-05 1985-12-23 Sony Corp Crystallization method of semiconductor thin film
US4667391A (en) * 1984-06-29 1987-05-26 Commissariat A L'energie Atomique Process for the production of thin film hall effect transducers
US5893948A (en) * 1996-04-05 1999-04-13 Xerox Corporation Method for forming single silicon crystals using nucleation sites
KR100397762B1 (en) * 2000-10-09 2003-09-13 (주)쎄미시스코 Method for crystallizing amorphous silicon thin film

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60260492A (en) * 1984-06-05 1985-12-23 Sony Corp Crystallization method of semiconductor thin film
JPH0536394B2 (en) * 1984-06-05 1993-05-28 Sony Corp
US4667391A (en) * 1984-06-29 1987-05-26 Commissariat A L'energie Atomique Process for the production of thin film hall effect transducers
US5893948A (en) * 1996-04-05 1999-04-13 Xerox Corporation Method for forming single silicon crystals using nucleation sites
KR100397762B1 (en) * 2000-10-09 2003-09-13 (주)쎄미시스코 Method for crystallizing amorphous silicon thin film

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