JPS59184517A - Manufacture of lamination-type semiconductor device - Google Patents

Manufacture of lamination-type semiconductor device

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Publication number
JPS59184517A
JPS59184517A JP58058732A JP5873283A JPS59184517A JP S59184517 A JPS59184517 A JP S59184517A JP 58058732 A JP58058732 A JP 58058732A JP 5873283 A JP5873283 A JP 5873283A JP S59184517 A JPS59184517 A JP S59184517A
Authority
JP
Japan
Prior art keywords
islands
island
single crystal
semiconductor
insulator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58058732A
Other languages
Japanese (ja)
Other versions
JPH0136972B2 (en
Inventor
Shigenobu Akiyama
秋山 重信
Koichi Kugimiya
公一 釘宮
Shigeji Yoshii
吉井 成次
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
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Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP58058732A priority Critical patent/JPS59184517A/en
Publication of JPS59184517A publication Critical patent/JPS59184517A/en
Publication of JPH0136972B2 publication Critical patent/JPH0136972B2/ja
Granted legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02664Aftertreatments
    • H01L21/02667Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02683Continuous wave laser beam
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02488Insulating materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02587Structure
    • H01L21/0259Microstructure
    • H01L21/02598Microstructure monocrystalline
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02664Aftertreatments
    • H01L21/02667Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02689Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using particle beams
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02664Aftertreatments
    • H01L21/02667Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02691Scanning of a beam

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To obtain the high-performanc three-dimensional integrated circuit by realizing an island of single-crystal semiconductor in which there is substantially little distortion and defect by a method wherein islands of non-single crystal semiconductor are formed on a surface of an insulator being isolated completely and energy beam is projected to single-crystallize the semiconductor islands and the insulator around said islands excluding the insulator under the bottoms of the islands to form semiconductor elements. CONSTITUTION:CW laser beam 4 is projected onto the islands of non-single crystal semiconductor isolated completely with being scanned in direction of the arrow X so as to single-crystallize the islands 3 of non-single crystal semiconductor. After a non-single crystal silicon layer is formed on a single crystal silicon substrate 1 through an insulator such as SiO2 or Si3N4, SiO2 or the like is buried so as to form islands 3 of non-single crystal silicon isolated completely and surrounded with the insulator 2 such as SiO2 or Si3N4. This islands 3 are then irradiated with laser beam 4. After that, SiO2 21 around the silicon islands 3 are removed, for example by HF buffer solution and a distortion region 31 formed by the irradiation with laser is simultaneously removed. After that, MOS transistors are formed on the recrystallized silicon islands 3, for example, by an usual manufacturing method.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は一般に三次元ICとして知られている積層型半
導体装置の製造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a stacked semiconductor device generally known as a three-dimensional IC.

従来例の構成とその問題点 三次元XCといわれる積層型半導体装置における積層型
単結晶を形成する製造方法については、ここ数年来、多
くの提案がなされている。以下にこれら技術について簡
単に説明を行うと共に、問題とがっている点を挙げる。
Conventional Structures and Problems Many proposals have been made over the past few years regarding a manufacturing method for forming a stacked single crystal in a stacked semiconductor device called three-dimensional XC. Below, we will briefly explain these technologies and point out their problems.

種結晶を用いる結晶化の方法としてブリッジングエピタ
キシー法やラテラルシープイドビームアニーリング法が
公知であり、これらの方法は、種結晶としての半導体基
板の開口部より結晶成長が生ずるために、結晶方位が制
御されると同時に良好外結晶が得られ易いという報告が
ある。しかし開口部より周辺に結晶成長が生ずるだめ、
開口部3 t、− を中心に、菊花状に単結晶がバラバラに成長し完全な単
結晶が得られないし、開口部周辺の絶縁膜上へ結晶が成
長してゆくときに結晶欠陥や乱れが生じ易いなどの欠点
が指摘されておQ1大面積化には困難である。
Bridging epitaxy and lateral sheeped beam annealing are well-known crystallization methods using seed crystals. In these methods, crystal growth occurs from an opening in a semiconductor substrate serving as a seed crystal, so the crystal orientation does not change. There are reports that it is easy to obtain good outer crystals while being controlled. However, crystal growth occurs in the periphery of the opening.
The single crystal grows apart in a chrysanthemum-like pattern around the opening 3t,-, making it impossible to obtain a perfect single crystal, and crystal defects and disturbances occur when the crystal grows on the insulating film around the opening. It has been pointed out that it is difficult to increase the area of Q1 due to drawbacks such as easy occurrence.

また、種結晶を用いない結晶化の一つの方法としてグラ
フオエピタキシー法が公知であり、KClの水溶液から
の単結晶成長ではいくつかの成功例が報告されている。
Furthermore, a graphoepitaxy method is known as a crystallization method that does not use a seed crystal, and several successful examples of single crystal growth from an aqueous solution of KCl have been reported.

しかしながらSi などの半導体膜の結晶化については
満足な結果は得られておらず、半導体素子をつくり込む
に足る技術にまでなり得ていない。種結晶を用い々い結
晶化のもう一つの方法として、島状非単結晶のビームア
ニール法がある。この方法は、絶縁基板(例えばSiO
□や813N4)上に通常の半導体素子製造法により、
完全絶縁分離して非単結晶半導体の島を形成し、その後
エネルギービーム(例えば、CWやパルスレーザ、電子
ビーム々ど)を照射することによシ、単結晶化ないし大
結晶粒化した結晶島を形成する技術である。この方法に
てかなり良好な単結晶島が得られているが、種結晶がな
いために、結晶の核形成制御が困難々ことから結晶方位
の制御は難しいこと、また、結晶化された島の周辺絶縁
物との界面では残された未結晶化領域や歪による欠陥が
存在し易いこと、さらに、島の形状や大きさにより結晶
化に最適々ビームエネルギーが変化するため結晶化にむ
らが出来る可能性があることなど問題がある。
However, satisfactory results have not been obtained regarding the crystallization of semiconductor films such as Si, and the technology has not yet become sufficient for fabricating semiconductor devices. Another method for crystallization using seed crystals is a beam annealing method for island-shaped non-single crystals. This method uses an insulating substrate (e.g. SiO
□ or 813N4) using normal semiconductor device manufacturing methods.
By completely insulating and separating a non-single crystal semiconductor island, and then irradiating it with an energy beam (e.g. CW, pulsed laser, electron beam, etc.), crystal islands can be made into single crystals or have large crystal grains. It is a technology that forms Although fairly good single crystal islands have been obtained using this method, since there is no seed crystal, it is difficult to control the crystal nucleation, so it is difficult to control the crystal orientation. At the interface with the surrounding insulator, residual uncrystallized regions and defects due to strain are likely to exist, and furthermore, the optimal beam energy for crystallization changes depending on the shape and size of the island, resulting in uneven crystallization. The problem is that it is possible.

発明の目的 本発明は、完全絶縁分離した非単結晶半導体の島をエネ
ルギービーム照射により熔融再結晶化せしめる方法にお
いて、再結晶化半導体と絶縁物との界面の歪や欠陥を除
去し、捷だ、再結晶化半導体の島の形状とエネルギービ
ーム照射の関係を一様にすることにより、従来のような
欠点をなくし、結晶性のすぐれた半導体の島を形成し、
三次元IC々る積層型半導体装置のすぐれた製造方法を
提供するものである。
Purpose of the Invention The present invention provides a method for melting and recrystallizing completely insulated non-single crystal semiconductor islands by energy beam irradiation, by removing distortions and defects at the interface between the recrystallized semiconductor and the insulator. By making the relationship between the shape of the recrystallized semiconductor island and the energy beam irradiation uniform, the conventional drawbacks are eliminated and semiconductor islands with excellent crystallinity are formed.
The present invention provides an excellent method for manufacturing a three-dimensional IC stacked semiconductor device.

発明の構成 本発明は、半導体素子の作り込まれた半導体基板5ベー
S 表面に絶縁物を形成したのち、絶縁物表面上に非単結晶
半導体の島をたとえば選択酸化法や絶縁物理め込み法な
どを用いて完全絶縁分離して形成し、前記非単結晶半導
体の島をエネルギービーム照射によシ熔融再結晶化せし
めたのち、前記再結晶化した半導体の島の底面部を除く
周辺の絶縁物を除去し、前記再結晶化した半導体の島に
通常の半導体素子製造工程によシ半導体素子を形成する
ものである。また、完全絶縁分離半導体の島を大きさ及
び形状がほぼ同一のものに形成し、さらに形状について
は矩形とすることにより、再結晶層の結晶性を更に改善
できると共に素子形成上好都合と彦るものである。
Structure of the Invention The present invention provides an insulator formed on the surface of a semiconductor substrate 5S in which a semiconductor element is built, and then islands of a non-single crystal semiconductor are formed on the surface of the insulator by, for example, a selective oxidation method or an insulation physical inlay method. After the non-single crystal semiconductor island is melted and recrystallized by energy beam irradiation, insulation is formed around the recrystallized semiconductor island except for the bottom part. After removing the material, a semiconductor element is formed on the recrystallized semiconductor island by a normal semiconductor element manufacturing process. In addition, by forming completely insulating and isolated semiconductor islands with almost the same size and shape, and by making them rectangular in shape, it is possible to further improve the crystallinity of the recrystallized layer and it is convenient for device formation. It is something.

実施例の説明 本発明の一実施例にかかる積層型半導体ICの製造工程
を第1図に従って説明する。
DESCRIPTION OF EMBODIMENTS The manufacturing process of a stacked semiconductor IC according to an embodiment of the present invention will be described with reference to FIG.

第1図の(&)は、完全絶縁分離された非単結晶半導体
の島3にCWレーザビーム4を矢印Xの方向に走査しな
がら照射して、前記非単結晶半導体の島3を単結晶化せ
しめるときの平面概念図である。
(&) in FIG. 1 shows that a CW laser beam 4 is irradiated onto a non-single crystal semiconductor island 3 that is completely insulated and separated while scanning in the direction of the arrow FIG.

6”’ 半導体素子(図示せず)が作如込まれた単結晶シリコン
基板1上に5j−0,やS i3N4々どの絶縁物を介
して、たとえば、低圧気相成長法によシ、非単結晶シリ
コン層を形成したのち、選択酸化法もしくはメサエッチ
ング後に8102々とを埋め込むことによシ、底面がS
iO2やSi3N4などの絶縁物2、周辺が5i022
1で囲まれた完全絶縁分離された非単結晶シリコンの島
3を形成する。
6"' A semiconductor element (not shown) is formed on a single crystal silicon substrate 1 through which an insulator such as 5j-0 or Si3N4 is formed by, for example, a low-pressure vapor phase epitaxy method. After forming a single-crystal silicon layer, the bottom surface becomes S by embedding 8102 after selective oxidation or mesa etching.
Insulator 2 such as iO2 or Si3N4, surrounding area is 5i022
A completely insulated and isolated non-single crystal silicon island 3 surrounded by 1 is formed.

第1図ノ(b)は、レーザビーム4の照射により、単結
晶化した場合のシリコン島3の断面構造図である。レー
ザビーム4の照射は、この場合CWArレーザを用い、
レーザ出力約18W、ビーム径約80μm、走査速度1
m&、  ビーム走査の重ね合わせ約30%とし、基板
はたとえば真空吸着ステージに載せ、4 rs O’C
VrC加熱した。このとき、シリコン島3の巾は20μ
m とし、上記レーザ照射方法により、ある−回の走査
で各シリコン島3は完全に熔融していることになる。3
1はシリコン島3の再結晶化に際し、シリコン島3と周
辺の5iO221の界面に発生する歪領域である。
FIG. 1(b) is a cross-sectional structural diagram of the silicon island 3 when it is single-crystalized by irradiation with the laser beam 4. In this case, a CWAr laser is used for irradiation with the laser beam 4,
Laser output approximately 18W, beam diameter approximately 80μm, scanning speed 1
m&, the beam scanning overlap is about 30%, the substrate is placed on a vacuum suction stage, and 4 rs O'C
VrC heating. At this time, the width of silicon island 3 is 20μ
m, and each silicon island 3 is completely melted in a certain number of scans by the laser irradiation method described above. 3
1 is a strain region generated at the interface between the silicon island 3 and the surrounding 5iO221 when the silicon island 3 is recrystallized.

7 l  ′ 第1図の(0)はレーザ照射後、たとえば、HF緩衝液
によシ、シリコン島3の周辺5iO221を除去したと
きの断面構造図であり、レーザ照射により形成された歪
領域31も同時に除去できている。
7 l' (0) in FIG. 1 is a cross-sectional structural diagram when the peripheral 5iO221 of the silicon island 3 is removed by, for example, an HF buffer solution after laser irradiation, and the strained region 31 formed by the laser irradiation is removed. can also be removed at the same time.

カお、こののち、再結晶化時に生じた欠陥、歪等を除去
する熱処理を加えてもよい。
After this, heat treatment may be applied to remove defects, distortions, etc. generated during recrystallization.

第1図の(d)は、この後、たとえば通常のMO8素子
製造方法により、再結晶シリコン島3にMOSトランジ
スタを形成したときの断面構造図である。
FIG. 1(d) is a cross-sectional structural diagram when a MOS transistor is subsequently formed on the recrystallized silicon island 3 by, for example, a normal MO8 element manufacturing method.

51は島3と反対導電型のソース及びドレイン領域、5
2は絶縁膜53を介して形成したゲート電極、54は配
線絶縁分離用5102.55は配線金属である。かくし
て形成したMO8素子は、歪や欠陥の殆んど々い単結晶
シリコン島3につくり込まれているため、非常にすぐれ
た特性を示す。
51 is a source and drain region having a conductivity type opposite to that of the island 3;
2 is a gate electrode formed through an insulating film 53, 54 is a wiring insulation isolation part 5102, and 55 is a wiring metal. The MO8 element thus formed exhibits very excellent characteristics because it is built into the single crystal silicon island 3, which has almost all the distortions and defects.

レーザ照射により、たとえば多結晶シリコン島3を再結
晶して単結晶とするとき、多結晶シリコン島3の形状、
大きさにより、結晶化の最適レーザ照射条件は微妙に変
化してくる。この状況の概念を第2図に従って説明する
When the polycrystalline silicon island 3 is recrystallized into a single crystal by laser irradiation, for example, the shape of the polycrystalline silicon island 3,
The optimal laser irradiation conditions for crystallization vary slightly depending on the size. The concept of this situation will be explained with reference to FIG.

レーザ4のビーム径に対し走査方向Xに対する多結晶シ
リコン島3(A、B、C,D)のl〕が2種類ある場合
、即ち、シリコン島A、Dの1]はレーザ4のビーム径
に対して十分小さく4たとえばビーム径の80チ程度、
シリコン島B、Cのl]はレーザ4のビーム径の約2倍
の大きさの場合に、第2図の(a)に示すように、レー
ザ4をX方向に走査する。第2図の(b)に示すように
、第1回目のビーム走査後では、シリコン島3のAはこ
の一回の走査で完全に熔融し再結晶化して単結晶と々る
が、シリコン島3のBでは、ビーム4は島の約半分のみ
が熔融するのみであるから、そのレーザ照射部分はシリ
コン島30Bのレーザの未照射部の多結晶シリコンを種
として細かい多くの微結晶が成長してしまう。
When there are two types of polycrystalline silicon islands 3 (A, B, C, D) with respect to the beam diameter of the laser 4 in the scanning direction For example, about 80 inches of beam diameter,
When the silicon islands B and C] are approximately twice the beam diameter of the laser 4, the laser 4 is scanned in the X direction as shown in FIG. 2(a). As shown in FIG. 2(b), after the first beam scan, A of the silicon island 3 is completely melted and recrystallized in this one scan, becoming a single crystal. At 3 B, the beam 4 melts only about half of the island, so many fine microcrystals grow in the laser irradiated area using the polycrystalline silicon in the non-laser irradiated area of the silicon island 30B as seeds. I end up.

その次のレーザ走査後では、第2図の(C)に示すよう
に、シリコン島30人はレーザは照射されないので、第
1回目の走査で形成した単結晶のま捷で残っている。シ
リコン島3のBけ、第1回目のレーザ走査で未照射部分
を含んで約半分の部分が9べ 2 熔融するが、全体として、1回目と2回目のレーザ照射
で部分的には重複して照射されてはいるものの別々に再
結晶化したものであるために、小さい結晶粒の集合体と
々ってしまう。このときシリコン島3のC,Dは末だレ
ーザ未照射のままでいる。
After the next laser scan, as shown in FIG. 2C, the 30 silicon islands are not irradiated with the laser, so they remain as single crystals formed in the first scan. In B of silicon island 3, approximately half of the area including the unirradiated area is melted by the first laser scan, but as a whole, some parts overlap between the first and second laser irradiation. Although the crystals are irradiated, they are recrystallized separately, resulting in agglomerations of small crystal grains. At this time, C and D of the silicon island 3 remain unirradiated with the laser.

第2図の(d)に示すように、4回目のレーザ照射の走
査が終了した時点では、シリコン島3の巾の狭いA、D
では島全体が殆んど単結晶となっているのに対し、シリ
コン島3の巾の広いB、Cでは、細かい結晶粒の集合体
としての島に々っている。
As shown in FIG. 2(d), at the end of the fourth laser irradiation scan, the silicon island 3 has narrow widths A and D.
In contrast, in B and C, where the width of the silicon island 3 is wide, the entire island is almost a single crystal, whereas the island is made up of an aggregate of fine crystal grains.

したがって、第2図に述べた方法では、島全体が殆んど
単結晶の鳥人、Dと小さい単結晶粒の集合体の島B、C
ができてしまう。
Therefore, in the method described in FIG.
is created.

又再結晶化に際して再結晶化シリコン島に生ずる歪もし
くは欠陥の入り方は島の形状や大きさにより異るために
、再結晶化後に島周辺をエツチングして歪や欠陥領域を
除去する場合、島の形状や大きさによって除去のやり方
を変える必要がでてくる。だとえば、第2図の大きさの
異々る島A。
Furthermore, the way in which strains or defects occur in recrystallized silicon islands during recrystallization differs depending on the shape and size of the islands. The removal method will need to be changed depending on the shape and size of the island. For example, islands A of different sizes in Figure 2.

1o/ Bについて、レーザ照射による再結晶化後の歪。1o/ Regarding B, strain after recrystallization by laser irradiation.

欠陥の入シ方およびエツチングによるそれらの除去後の
結晶性についての概要を、第3図に従って説明する。
An overview of how defects are introduced and the crystallinity after their removal by etching will be explained with reference to FIG.

第3図の(alは、第2図の((1)に示したレーザ照
射後の再結晶化島A、Bに導入される歪、欠陥領域(第
3図のX印で示す)および結晶粒界(島内の実線で示す
)の概念図である。1]の狭い島Aでは島全体が殆んど
単結晶になっているが、周辺部での歪および欠陥の入る
領域は熱膨張係数等のちがいによる応力の入り方が大き
いために広くなる。
(al in FIG. 3) is the strain introduced into the recrystallized islands A and B after laser irradiation shown in (1) in FIG. This is a conceptual diagram of a grain boundary (indicated by a solid line inside the island).In the narrow island A shown in [1], the entire island is almost single crystal, but the area where distortion and defects occur at the periphery has a coefficient of thermal expansion. It becomes wider due to the large amount of stress that is applied due to differences in

一方、11の広い島Bでは、周辺部での歪および欠陥領
域は小さく彦るが、前述の如く、島全体は小さい結晶粒
の集合体になると同時に、島Bの中央部のレーザ走査の
重なりの部分では歪や欠陥が入ってしまう。したがって
第3図の(blに示すように、島Bの周辺歪領域を除去
するようにエツチングしても島Aの周辺では歪、欠陥が
残存してしまう。
On the other hand, in the case of the 11 wide islands B, the strain and defect areas at the periphery are small, but as mentioned above, the entire island becomes an aggregation of small crystal grains, and at the same time, the overlap of the laser scans in the central part of the island B Distortions and defects occur in the parts. Therefore, as shown in (bl) of FIG. 3, even if etching is performed to remove the strained area around island B, the strain and defects will remain around island A.

さらに第3図の(0)に示すように島Aの周辺歪をも全
て除去すれば島A、Bとも周辺部については歪。
Furthermore, as shown in (0) in Figure 3, if all the peripheral distortion of island A is removed, the peripheral parts of both islands A and B become distorted.

11ぺ2 欠陥を除去できるが、この場合、残った島Aは巾が狭く
なシすぎるとともに、島Bにおいては中央部の欠陥領域
は残ってしまう。
11P2 The defect can be removed, but in this case, the remaining island A will be too narrow in width, and the defective area in the center of island B will remain.

もちろん、レーザビーム径を大きくして、1回の走査で
島B、Cが完全に熔融せしめるようにすれば上記問題は
解消されるが、一般的にレーザビーム径を大きくすれば
ビーム中央部のパワー密度は大きくなってしまうために
、巾の狭い島A、Dでは、エネルギー密度が大きすぎて
シリコンが熔融し周囲へ飛び散シあるいは蒸発してしま
い、島の一部あるいは全てからシリコンが欠損してしま
うことになシ好ましくない。しだがって、同一基板上に
形成するシリコン島は、はぼ同一の形状。
Of course, the above problem can be solved by increasing the laser beam diameter so that islands B and C are completely melted in one scan, but generally speaking, if the laser beam diameter is increased, the central part of the beam will melt. Since the power density becomes large, the energy density on the narrow islands A and D is too large and the silicon melts and scatters or evaporates to the surrounding area, causing silicon to be lost from part or all of the islands. I don't like what you end up doing. Therefore, silicon islands formed on the same substrate have almost the same shape.

大きさを有している方が望ましい。こうしたことに鑑み
て、シリコン島を形成したいくつかの望ましい実施例を
以下に示す。
It is desirable to have a large size. In view of this, some preferred embodiments in which silicon islands are formed are shown below.

第4図の(alは多結晶シリコン島3を全て正方形で一
定の間隔に並べて形成し、その−辺の大きさよシ2o%
程度大きいビーム径をもつレーザ4をX方向にビームの
中心が島の中央付近を通るように走査し々から照射した
場合である。第4図の(b)は同一の大きさの正方形を
45°傾けて一定の間隔で配置形成したシリコン島を1
回の走査のレーザ照射で各シリコン島は熔融するように
レーザ照射した場合である。第4図のFC)は、同一の
大きさの長方形を一定の間隔で並べてシリコン島3とし
た場合でアシ、長方形の短い辺はレーザ4のビーム径よ
シやや小さくシ、長い辺は所望の長さこの場合はたとえ
ば短辺の5倍の長さとし、レーザ4のビームの走査方向
は長方形の長辺に平行に々るよう又走査位置は長方形の
はゾ中夫になるように設定した。
In FIG. 4, (al) is formed by arranging all the polycrystalline silicon islands 3 in a square shape at regular intervals, and the size of the side is 20%.
This is a case where a laser 4 having a relatively large beam diameter is scanned and irradiated in the X direction so that the center of the beam passes near the center of the island. Figure 4(b) shows silicon islands formed by tilting squares of the same size at a 45° angle and arranging them at regular intervals.
This is a case in which laser irradiation is performed so that each silicon island is melted by laser irradiation in multiple scans. FC) in Fig. 4 is a silicon island 3 formed by arranging rectangles of the same size at regular intervals.The short side of the rectangle is slightly smaller than the beam diameter of the laser 4, and the long side is The length in this case is, for example, five times the length of the short side, and the scanning direction of the beam of the laser 4 is set to be parallel to the long side of the rectangle, and the scanning position is set to be in the middle of the rectangle.

以上の3例のようにシリコン島3の大きさ、形状をほぼ
揃えて、ビームの走査方向、走査位置を適宜設定するこ
とにより、各島について島全体をはゾ単結晶とすること
ができた。
By making the size and shape of the silicon islands 3 almost the same as in the three examples above, and appropriately setting the scanning direction and position of the beam, it was possible to make the entire island of each island a single crystal. .

次に、上記の如く、再結晶化によシ得られた単結晶のシ
リコン島を素子を形成する基板とするだめの実施例を第
6図、第6図に従って説明する。
Next, an embodiment in which a single-crystal silicon island obtained by recrystallization as described above is used as a substrate for forming an element will be described with reference to FIGS.

第5図ノ(+!L)はSin、、21で囲まれた2 0
11m X13 l−” 100μmの長方形の多結晶シリコン島3にビーム径3
0μmのレーザをXの方向に走査する場合の平面概念図
である。このとき1回のビーム走査で多結晶シリコン島
3は完全に熔融し単結晶の島になる。第6図の(b)は
再結晶化後の断面構造図である。単結晶化シリコン島3
と周辺sio、 21の境界部分には再結晶化の際に発
生した歪、欠陥領域31が存在している。レーザ照射後
、周辺sio□21を除去し歪を除いた状態を第6図の
(C1に示す。
Figure 5 (+!L) is 20 surrounded by Sin,,21
11m x 13 l-” 100μm rectangular polycrystalline silicon island 3 with beam diameter 3
FIG. 3 is a conceptual plan view when scanning with a 0 μm laser in the X direction. At this time, the polycrystalline silicon island 3 is completely melted by one beam scan and becomes a single crystal island. FIG. 6(b) is a cross-sectional structural diagram after recrystallization. Single crystal silicon island 3
A defective region 31 due to strain generated during recrystallization is present at the boundary between the wafer and the surrounding sio, 21. After laser irradiation, the peripheral sio□ 21 is removed to remove distortion, and the state is shown in (C1) in FIG.

さらに第5図の(d)に示すように単結晶化シリコン島
3の表面部分を除去し、続いて素子を形成するのに適当
な大きさたとえば158mX30μmの大きさにエツチ
ングにより分割した島3′とした。
Further, as shown in FIG. 5(d), the surface portion of the single-crystal silicon island 3 is removed, and then the island 3' is divided by etching into a size suitable for forming a device, for example, 158 m x 30 μm. And so.

その後、分割した単結晶化シリコン島3′の間をCVD
法々どでたとえばSiO□22で埋め込むことによシ表
面を平坦化しく第5図の(e))、分割した単結晶化シ
リコン島3′に半導体素子を形成した。
After that, CVD is applied between the divided single crystal silicon islands 3'.
The surface was planarized by filling with, for example, SiO□22 (FIG. 5(e)), and semiconductor elements were formed on the divided single-crystal silicon islands 3'.

また第6図の(atは素子形成に適した大きさの多結晶
シリコン島3を複数個形成したのち、レーザ4の1回の
走査で完全熔融再結晶化によシ、単結14)  ゛ 晶化する平面概念図である。第6図の(b)はレーザ照
射後の断面構造図であわ、歪、欠陥領域31が存在して
いる。次に、単結晶化シリコン島3と周辺5in221
の歪、欠陥領域31を含む境界領域をエツチング除去す
る。このときの平面概念図と断面構造図を第6図の(C
1及び(d)にそれぞれ示す。かくして得られた単結晶
化シリコン島3に素子を形成する。
In addition, in FIG. 6 (at is a single crystal 14) after forming a plurality of polycrystalline silicon islands 3 of a size suitable for element formation, complete melting and recrystallization is performed with one scan of the laser 4. It is a conceptual plan view of crystallization. FIG. 6(b) is a cross-sectional structural view after laser irradiation, and there are distortions and defect areas 31. Next, the single crystal silicon island 3 and the surrounding area 5in221
The boundary area including the distortion and defect area 31 is removed by etching. The conceptual plan view and cross-sectional structure diagram at this time are shown in Figure 6 (C
1 and (d), respectively. Elements are formed on the monocrystalline silicon island 3 thus obtained.

本発明においては、レーザ以外に電子ビーム、赤外線ビ
ーム等を用いてもよい。
In the present invention, an electron beam, an infrared beam, etc. may be used in addition to a laser.

発明の効果 以上の説明で明らかなように、本発明により、歪や欠陥
の極めて少々い良質の所望の大きさの単結晶半導体の島
が実現でき、高性能三次元ICを提供することができる
Effects of the Invention As is clear from the above explanation, the present invention makes it possible to realize a high-quality single crystal semiconductor island of a desired size with very few distortions and defects, and to provide a high-performance three-dimensional IC. .

【図面の簡単な説明】[Brief explanation of drawings]

第1図はレーザ照射による単結晶化島作製の本発明の一
実施例を示す工程図で、(a)はレーザ照射の平面概念
図、(bl 、 (c) 、 (d)は断面構造図、第
2図(at 、 (b) 、 (cl 、 (d)は、
島の大きさとレーザビームの151−z・ 大きさによる再結晶化のされ方の違いを示す平面概念図
、第3図(a) 、 (b) 、 (clは再結晶化島
の大きさによる歪、欠陥の入り方のちがいを示す概念図
、第4図(al 、 (bl 、 (cl it島の大
きさ、形状、配置を同一にした場合のレーザ照射の実施
例を示す平面概念図、第5図は単結晶化島を形成したの
ち所望の大きさに分割する場合の一実施例の工程図で、
(a)は平面図概念図、(b) 、 FC+ 、 (d
) 、 (1111は断面構造図、第6図は単結晶化島
の周辺5102  との境界を除去する場合の一実施例
の工程図で、(a) 、 (c)は平面概念図、 (b
l 、 (d)は断面構造図である。 1・・・・・・下地単結晶シリコン基板、2・・・・・
・下地フ11  FfI 衿t?1シ 第1図 3 第2図   DD 第3図 第4図 2/ 第4図 第60    。
FIG. 1 is a process diagram showing an embodiment of the present invention for producing single crystallized islands by laser irradiation, in which (a) is a conceptual plan view of laser irradiation, and (bl, (c), and (d) are cross-sectional structural diagrams). , Figure 2 (at, (b), (cl, (d)) is
Conceptual plan view showing the difference in recrystallization depending on the size of the island and the 151-z size of the laser beam, Figure 3 (a), (b), (cl depends on the size of the recrystallized island) Conceptual diagram showing the difference in the way distortion and defects are introduced, Figure 4 (al, (bl, (bl), (plan conceptual diagram showing an example of laser irradiation when the size, shape, and arrangement of clit islands are the same, FIG. 5 is a process diagram of an example in which single crystallized islands are formed and then divided into desired sizes.
(a) is a conceptual plan view, (b), FC+, (d
), (1111 is a cross-sectional structural diagram, FIG. 6 is a process diagram of an example of removing the boundary with the periphery 5102 of the single crystallized island, (a) and (c) are conceptual plan views, (b)
1, (d) is a cross-sectional structural diagram. 1... Base single crystal silicon substrate, 2...
・Base F11 FfI Collar t? Figure 1 Figure 1 Figure 2 Figure 2 DD Figure 3 Figure 4 Figure 2/ Figure 4 Figure 60.

Claims (3)

【特許請求の範囲】[Claims] (1)半導体基板表面上に、完全絶縁分離した非単結晶
半導体の島を形成する工程と、前記非単結晶半導体の島
にエネルギービームを照射して結晶化する工程と、前記
結晶化した半導体の島の底面部を除く周囲の絶縁物を除
去する工程と、前記結晶化した半導体の島に半導体素子
を形成する工程とを備えたことを特徴とする積層型半導
体装置の製造方法。
(1) A step of forming a completely insulated non-single crystal semiconductor island on the surface of a semiconductor substrate, a step of crystallizing the non-single crystal semiconductor island by irradiating the island with an energy beam, and a step of crystallizing the non-single crystal semiconductor island. 1. A method for manufacturing a stacked semiconductor device, comprising the steps of: removing an insulator around the island except for the bottom surface of the island; and forming a semiconductor element on the crystallized semiconductor island.
(2)絶縁物の除去と同時に、結晶化した半導体の島の
底面部を除く周囲の未結晶化領域を除去することを特徴
とする特許請求の範囲第1項に記載の積層型半導体装置
の製造方法。
(2) The stacked semiconductor device according to claim 1, characterized in that, at the same time as removing the insulator, the surrounding uncrystallized region other than the bottom part of the crystallized semiconductor island is removed. Production method.
(3)完全絶縁分離した非単結晶半導体の島が、太き官
及び形状がほぼ同一に複数個形成されていることを特徴
とする特許請求の範囲第1項に記載の積層型半導体装置
の製造方法。 2 パ (41完全絶縁分離した非単結晶半導体の島の形状が矩
形であることを特徴とする特許請求の範囲第1項に記載
の積層型半導体装置の製造方法。
(3) A stacked semiconductor device according to claim 1, characterized in that a plurality of completely insulated and isolated non-single crystal semiconductor islands are formed with substantially the same diameter and shape. Production method. 2. The method for manufacturing a stacked semiconductor device according to claim 1, wherein the island of the completely insulated non-single crystal semiconductor has a rectangular shape.
JP58058732A 1983-04-05 1983-04-05 Manufacture of lamination-type semiconductor device Granted JPS59184517A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58058732A JPS59184517A (en) 1983-04-05 1983-04-05 Manufacture of lamination-type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58058732A JPS59184517A (en) 1983-04-05 1983-04-05 Manufacture of lamination-type semiconductor device

Publications (2)

Publication Number Publication Date
JPS59184517A true JPS59184517A (en) 1984-10-19
JPH0136972B2 JPH0136972B2 (en) 1989-08-03

Family

ID=13092675

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58058732A Granted JPS59184517A (en) 1983-04-05 1983-04-05 Manufacture of lamination-type semiconductor device

Country Status (1)

Country Link
JP (1) JPS59184517A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004006725A (en) * 2002-03-26 2004-01-08 Semiconductor Energy Lab Co Ltd Semiconductor device, its fabricating and designing method
JP2004006741A (en) * 2002-03-26 2004-01-08 Semiconductor Energy Lab Co Ltd Semiconductor circuit and its fabricating method
US7704812B2 (en) 2002-03-26 2010-04-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor circuit and method of fabricating the same
US8093593B2 (en) 2001-12-21 2012-01-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having multichannel transistor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5837918A (en) * 1981-08-28 1983-03-05 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5837918A (en) * 1981-08-28 1983-03-05 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8093593B2 (en) 2001-12-21 2012-01-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having multichannel transistor
JP2004006725A (en) * 2002-03-26 2004-01-08 Semiconductor Energy Lab Co Ltd Semiconductor device, its fabricating and designing method
JP2004006741A (en) * 2002-03-26 2004-01-08 Semiconductor Energy Lab Co Ltd Semiconductor circuit and its fabricating method
US7704812B2 (en) 2002-03-26 2010-04-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor circuit and method of fabricating the same

Also Published As

Publication number Publication date
JPH0136972B2 (en) 1989-08-03

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