JPS5944887A - Semiconductor light emitting device - Google Patents

Semiconductor light emitting device

Info

Publication number
JPS5944887A
JPS5944887A JP57157206A JP15720682A JPS5944887A JP S5944887 A JPS5944887 A JP S5944887A JP 57157206 A JP57157206 A JP 57157206A JP 15720682 A JP15720682 A JP 15720682A JP S5944887 A JPS5944887 A JP S5944887A
Authority
JP
Japan
Prior art keywords
layer
semiconductor layer
semi
semiconductor
light emitting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57157206A
Other languages
Japanese (ja)
Inventor
Tsugunori Takahashi
鷹箸 継典
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57157206A priority Critical patent/JPS5944887A/en
Publication of JPS5944887A publication Critical patent/JPS5944887A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/20Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/227Buried mesa structure ; Striped active layer
    • H01S5/2275Buried mesa structure ; Striped active layer mesa created by etching

Landscapes

  • Semiconductor Lasers (AREA)
  • Led Devices (AREA)

Abstract

PURPOSE:To improve integration density by blocking reactive current by using a semi-insulation semiconductor layer as the semiconductor layer which decides the division of a current passage to the light emitting region. CONSTITUTION:The semi-insulation InP layer 12 doped with chrome by vapor growing method is grown on an N type InP substrate 11. Using the mask, a groove 20 in stripe form of the width of approx. 3mum is mixture-formed to the depth enough for reaching the substrate 11 by penetrating the layer 12. The first N type InP clad layer 13, a non-doped InGaAsP active layer 14, a second P type InP clad layer 15 and a P type InGaAsP cap layer 16 are successively grown by LPE method to the thickness whereby the upper surfaces thereof become nearly the same plane as the upper surface of the layer 12. Then, the stripe region is sandwiched only between the layers 12, resulting in current stricture, and therefore the problem of the dispersion of the relative positional relation between the semiconductor layer of the stripe region and that of the current block region is not generated.

Description

【発明の詳細な説明】 (a)  発明の技術分野 本発す」は半導体発光装置の構造、特に闇値電流が減少
し、無効電流が阻止され、特性の分散が減少して再机性
が向上する半導体発光装置の構造に一関する。
[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to the structure of a semiconductor light emitting device, in particular, the dark value current is reduced, the reactive current is blocked, the dispersion of characteristics is reduced, and the reworkability is improved. This invention relates to the structure of a semiconductor light emitting device.

(b)  従来技術と四組点 光を情報4N号の媒体とする光フアイバ通信及びその他
の産業、民生分野において、光信号を発生する半導体発
光装置は最も重要な機能全果しておシ、その特性が安定
し、かつ信頼度が優れていることが強く要求されている
(b) Conventional technology and four-point combination In optical fiber communications and other industrial and consumer fields where light is used as the medium of information No. 4N, semiconductor light emitting devices that generate optical signals fulfill the most important functions and their characteristics. There is a strong demand for stability and reliability.

半導体発光装置の構造に関しては既に数多くの提案がな
されているが、活性層等が半導体層内に設けられた溝内
に形成されている埋め込み構造半導体レーザの従来例を
第1図(a)及び(b)に示す断面図を参照して説明す
る。
Although many proposals have already been made regarding the structure of semiconductor light emitting devices, a conventional example of a buried structure semiconductor laser in which an active layer etc. is formed in a groove provided in a semiconductor layer is shown in FIGS. 1(a) and 1(a). This will be explained with reference to the cross-sectional view shown in (b).

第1図(a)に示す如<、n型インジウム・燐(InP
)基板1上にp型InP層2が液相エピタキシャル成長
法(以下LPE法と略称する〕などの方法によって形成
されている。pfflInP層2に接して設けられた二
酸化シリコン(5i02 )膜によってマスク3″f:
形成して選択的エツチングを行ない、n型InP基&1
に達する深さのストライプ状の溝4が設けられる。
As shown in Figure 1(a), n-type indium phosphorus (InP)
) A p-type InP layer 2 is formed on a substrate 1 by a method such as liquid phase epitaxial growth (hereinafter abbreviated as LPE).A mask 3 is formed by a silicon dioxide (5i02) film provided in contact with the pfflInP layer 2. ″f:
Formed and selectively etched to form an n-type InP group &1
A striped groove 4 is provided with a depth reaching .

次いで第1図(b)に示す如く、マスク3′lt除去し
た後にLPE法によって、n型InP第一クラッド層5
、ノンドーグのインジウムΦガリウム嗜砒素−g (I
nGaAsP)活性層6、p型InP第2クラッドrV
J7及びp型InGaAaPキャップ層8が11「」次
形成される。この際に溝4外のp型1nP層2上にn型
InP層5 ’及びノンドープのInGaAsP層6′
が成長する。次いでn型InP基板1の厚さを調整した
後にp側電極9及びn側%、極1oが設けられる0 以上の如き構造の半導体レーザにおいて、n型InPm
1クラツド層5及びp型InP第2クラッドN7の禁制
帯幅はInGaAsP活性層6よp大きく、キャリアは
InGaAsP活性層6に閉じ込められ、また両クラッ
ド層5及び7のル(折率はI nGaAsP活性As上
シ小さく、光も活性層6に閉じ込められる。
Next, as shown in FIG. 1(b), after removing the mask 3'lt, an n-type InP first cladding layer 5 is formed by LPE.
, non-dorg indium Φ gallium arsenide-g (I
nGaAsP) active layer 6, p-type InP second cladding rV
J7 and a p-type InGaAaP cap layer 8 are formed 11 times later. At this time, an n-type InP layer 5' and a non-doped InGaAsP layer 6' are formed on the p-type 1nP layer 2 outside the trench 4.
grows. Next, after adjusting the thickness of the n-type InP substrate 1, a p-side electrode 9, an n-side electrode 9, and a pole 1o are provided.
The forbidden band width of the first cladding layer 5 and the p-type InP second cladding N7 is p larger than that of the InGaAsP active layer 6, and carriers are confined in the InGaAsP active layer 6. The active As layer is small and light is also confined in the active layer 6.

また、p側電極9を正、11側電極10を負の宙、位と
して流される%H流は、n型InP贋5′とp型InP
層2とによって形成されるn−p接合界面によって、ス
トライプ領域外の経路が阻止されているO しかしながら前Me従来例の構造においては電流密度を
増大するどきに、InGaAsP活性層6を通過せずに
、p型InP第2クラッド層7→p型InP層2→n型
InP基板1の電流経路にょるレーザ発振に寄与しない
無効電流が発生する。
In addition, the %H flow flowing with the p-side electrode 9 as positive and the 11-side electrode 10 as negative is between n-type InP counterfeit 5' and p-type InP.
The path outside the stripe region is blocked by the n-p junction interface formed by the InGaAsP layer 2. However, in the previous Me conventional structure, when the current density is increased, the current does not pass through the InGaAsP active layer 6. In addition, a reactive current that does not contribute to laser oscillation is generated along the current path from the p-type InP second cladding layer 7 to the p-type InP layer 2 to the n-type InP substrate 1.

しかもこの無効電流はInGaAsP活性層6と前記n
−p接合界面との相対的位置関係によって変化して、こ
の構造の半導体レーザの特性のばらつきの要因の一つと
なっている。
Moreover, this reactive current flows between the InGaAsP active layer 6 and the n
It changes depending on the relative positional relationship with the -p junction interface, and is one of the causes of variations in the characteristics of semiconductor lasers with this structure.

またこの特性のばらつきの要因としては、エピタキシャ
ル成長層形成の際の半導体領域界面、例えは前記溝4の
表出面、近傍における不純物の拡散などが挙げられる。
Factors contributing to this variation in characteristics include the diffusion of impurities at the semiconductor region interface during the formation of the epitaxial growth layer, for example at the exposed surface of the trench 4, and in the vicinity.

以上の如き特性のばらつき’e、LPE成長の際の制御
の改善によって抑制することは極めて困1111Gであ
シ、また無効電流の抑制は量子効率の向上のみならず信
頼度の向上にも必要であることがら、上記問題点を解決
する半導体レーザの油しい44jJ造の提案が要望され
ている。
It is extremely difficult to suppress the above-mentioned variations in characteristics by improving control during LPE growth, and suppression of reactive current is necessary not only to improve quantum efficiency but also to improve reliability. For certain reasons, there is a demand for a proposal for a 44JJ semiconductor laser that solves the above-mentioned problems.

(c)  発明の目的 本発明は、無効電流が阻止され、かつ活性層その他の半
導体層の相対的位置関係等による特性の分散が抑制され
た半導体発光装置を提供することを目自勺とする。
(c) Purpose of the Invention The present invention aims to provide a semiconductor light emitting device in which reactive current is prevented and dispersion of characteristics due to the relative positional relationship of the active layer and other semiconductor layers is suppressed. .

(d)  発明の構成 本発明の前記目的は、発光領域への笥、流路を画定する
半導体層として半絶縁性半導体層を用いた半導体発光装
置。
(d) Structure of the Invention The object of the present invention is to provide a semiconductor light emitting device using a semi-insulating semiconductor layer as a semiconductor layer defining a receptacle and a flow path to a light emitting region.

特に、光電変換部全構成する半導体層及び該半導体層と
−の電極との間に設けられた半導体層の側端部が、半絶
縁性半導体層に当接して終端してなる半導体発光装置に
より達成される0すなわち従来の半導体発光装置におい
ては活性層等の側端部を導電性を有する半導体層で終端
し、pn接合及びビルトインポテンシャルの差などによ
って電流狭窄を行なうのに対して、本g6QLJの半導
体発光装置においては基板に格子整合する半絶縁性半導
体層、特に活性層よシ屈折率が小なる半絶縁性半導体層
によって電流狭窄を行なうことによって、その特性の向
上と構造の簡素化″f:達成するものである。
In particular, a semiconductor light emitting device in which a semiconductor layer constituting the entire photoelectric conversion section and a side end portion of the semiconductor layer provided between the semiconductor layer and the negative electrode are terminated by contacting a semi-insulating semiconductor layer. In conventional semiconductor light emitting devices, the side edges of the active layer and the like are terminated with a conductive semiconductor layer, and current confinement is achieved using a pn junction and a difference in built-in potential, whereas this g6QLJ In semiconductor light emitting devices, current confinement is achieved using a semi-insulating semiconductor layer that is lattice-matched to the substrate, especially a semi-insulating semiconductor layer that has a lower refractive index than the active layer, thereby improving its characteristics and simplifying its structure. f: To be achieved.

(e)  発明の実施例 以下本発明を実施例によシ図面を参照して具体的に説明
する。
(e) Embodiments of the Invention The present invention will be specifically described below by way of embodiments with reference to the drawings.

第2図は半導体レーザについて本発明を実施した例を示
す斜視図であシ、11はn型InP基板、12は半絶縁
性InP)fi5.13はn型InP第1クラッド層、
14はノンドープのInGaAsP活性層、15はp型
1np第2クラッド層、16はp型In−GaAsPキ
’ryプ層、17はp側′?I、極、18id:n伊0
電極を示す。
FIG. 2 is a perspective view showing an example of implementing the present invention for a semiconductor laser, in which 11 is an n-type InP substrate, 12 is a semi-insulating InP layer, fi5.13 is an n-type InP first cladding layer,
14 is a non-doped InGaAsP active layer, 15 is a p-type 1np second cladding layer, 16 is a p-type In-GaAsP cap layer, and 17 is a p-side '? I, pole, 18id:nI0
Shows electrodes.

前記実施例の半導体レーザの製造方法の概要不二第3図
(a)及び(b)を参照して説、明する。
An outline of the method for manufacturing the semiconductor laser of the above embodiment will be explained with reference to FIGS. 3(a) and 3(b).

第3図(a)に示す如く、n型InP基板11上に気相
成畏法によってクロム(’Cr)’eドープしIC半絶
縁性InP7m 12を厚さ例えば4〔μm〕程度に成
長させる。5in2からなるマスク19′f:用いて1
194約3〔μm〕のストライプ状の溝20を半絶縁性
InP/m12を貫通してn型InPIjtl 11に
充分達する深さに例えば塩酸(H(u)と硝酸(HNO
s)との混合液を用いるエツチングによって形成する〇
a′、3しl (b)に示す如く、前M’Lマスク19
を除去することなく、n型InP第1クラッド/I+1
3全7!さ2〔8m70程度に、ノンドープのInGa
AsP活性層14を厚さ0.2 C,ttrn、)程度
に、p型InP第2クラッド層15Q厚さ2〔即り程度
に、I) uInGaAsPInGaAsPキャラ上表
面が前記半絶縁性InP層12の上表面とほぼ同一平面
となる厚さに順次LPE法によって成長させる。このL
PE成長においては先の従来例とは異なシ溝20外の表
面は5i02によるマスク19によって被覆されている
ために、この領域には半導体層は堆積しない。
As shown in FIG. 3(a), IC semi-insulating InP 7m 12 is grown on an n-type InP substrate 11 to a thickness of about 4 μm, for example, doped with chromium ('Cr)'e by vapor deposition method. . Mask 19'f consisting of 5in2: using 1
For example, hydrochloric acid (H(u) and nitric acid (HNO
As shown in (b), the front M'L mask 19 is formed by etching using a mixed solution with s).
n-type InP first cladding/I+1 without removing
3 total 7! Size 2 [About 8m70, non-doped InGa
The AsP active layer 14 has a thickness of about 0.2 C, ttrn,), and the p-type InP second cladding layer 15Q has a thickness of about 2 (about 2), so that the upper surface of the uInGaAsPInGaAsP layer is on the order of 0.2C, ttrn, ). The layers are sequentially grown by LPE to a thickness that is substantially flush with the upper surface. This L
In PE growth, the surface outside the trench 20 is covered with a mask 19 of 5i02, which is different from the conventional example, so no semiconductor layer is deposited in this region.

次いで前記S i Oxによるマスク19の除去、n型
InP基板11の厚さの調整、p側電極17及びri側
↑↓3、極18の形成、並びに端面の臂I5i′1等’
tr: 111J次行なうことによって第21ン1に示
した半導体レーザ量子が完成する。
Next, the mask 19 is removed using SiOx, the thickness of the n-type InP substrate 11 is adjusted, the p-side electrode 17, the ri side ↑↓3, and the pole 18 are formed, and the edges of the end face I5i'1, etc.'
tr: By carrying out 111J steps, the semiconductor laser quantum shown in No. 21-1 is completed.

なお、前記5i02によるマスク19を除去することな
くp側電極を形成するならば、この5i02j友は11
流狭窄の効果を助長する。
Note that if the p-side electrode is formed without removing the mask 19 of 5i02, this 5i02j friend is 11
Promotes the effect of flow stenosis.

以上説明した本実飾物の半導体レーザにおいては、スト
ライプ領域は半絶縁性半導体層のみに狭せれて電流狭窄
が行なわれ、オだ半絶縁性半導体層は屈折率ガイドの効
果も有して、前記従来例の如くストライプ領域の半導体
層と電流(!旧[1−領域の半導体層との相対的位埴関
係のばらつきの11A1題も生じない。
In the semiconductor laser of the present embodiment described above, the stripe region is narrowed only by the semi-insulating semiconductor layer to effect current confinement, and the semi-insulating semiconductor layer also has the effect of refractive index guide. Unlike the conventional example, the problem of variation in the relative phase relationship between the semiconductor layer in the stripe region and the semiconductor layer in the current (!old [1- region)] does not occur.

前記本実飾物について特性を測定した結果、Kl値電流
は約10 [rnA)で無効電流は検出されず、量゛子
効率は一面あたり約30〔チ〕が得られ、かつ特性の分
散についても大幅な改善が達成さすしている。
As a result of measuring the characteristics of this actual ornament, the Kl value current was approximately 10 [rnA], no reactive current was detected, the quantum efficiency was approximately 30 [chi] per surface, and the dispersion of the characteristics was also Significant improvements are being achieved.

以上説明した実施例は単一の半導体レーザであるが、本
発明の特徴とする半絶縁性半導体層は素子間分離の効果
も有し、発光素子を含む隼私回路装Re高密度に形成す
ることが容易となる。
Although the embodiment described above is a single semiconductor laser, the semi-insulating semiconductor layer, which is a feature of the present invention, also has the effect of isolating elements, and is highly densely formed in Hayabusa's circuitry including light emitting elements. This makes it easier.

また前記実施例の製造方法として、半導体基板上にまず
半絶縁性半導体NI全形成し、これに設けた溝内に活性
層等を形成したが、半導体基板上にクラッド層、活性層
等とする所要の半導体層を順次形成した後にストライプ
状にこれらの坐導体/+’S全残置する選択的エツチン
グを施し、しかる後に半絶縁性半導体層全選択成長する
製造方法も可能であシ、この方法による場合には活性層
の形状及び厚さ等の制御が容易となる。
In addition, in the manufacturing method of the above embodiment, a semi-insulating semiconductor NI was first completely formed on a semiconductor substrate, and an active layer, etc. was formed in a groove provided in this, but a cladding layer, an active layer, etc. were formed on the semiconductor substrate. It is also possible to perform a manufacturing method in which, after sequentially forming the required semiconductor layers, selective etching is performed to leave all of these sitting conductors/+'S in a stripe shape, and then a semi-insulating semiconductor layer is selectively grown on all of them. In this case, it becomes easy to control the shape, thickness, etc. of the active layer.

更に前記実施例はInP −InGaAsP系半堺体相
料によって構成されているが、半導体材料はこれに限ら
れるものではなく、例えばガリウム・砒素(Ga、As
 )基板上にアルミニウム・ガリウム・砒素(A6Ga
As )半絶縁性半導体層に埋設されたストライプ領域
を形成するなど任意の半導体相料による発光装置に本発
明を適用することが可能である0 (f)  発明の詳細 な説明した如く本発明によれば、電流狭窄が安定して行
なわれて閾値電流の減少、無効電流の阻止、並びに量子
効率の向上が大幅にかつ再現性良く達成され、更に来秋
化に際しても集積密度を向上することが可能となる6
Further, although the above embodiment is made of an InP-InGaAsP semi-crystalline phase material, the semiconductor material is not limited to this, and for example, gallium/arsenic (Ga, As
) Aluminum, gallium, arsenic (A6Ga) on the substrate
As) The present invention can be applied to a light emitting device using any semiconductor phase material, such as forming a striped region embedded in a semi-insulating semiconductor layer. (f) As described in detail, the present invention According to the research, current confinement is performed stably, reducing threshold current, blocking reactive current, and improving quantum efficiency significantly and with good reproducibility.Furthermore, it is possible to improve integration density even next fall. 6 possible

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)及び(b)は半導体レーザの従来例を示す
断面図、第2図は半導体レーザにかかる本発明の実施例
を示す斜視図、第3図(a)及び(b)ld前記実施例
の製造工程全説明する1θ1面図である。 図において、1ltj:n型ITIP基板、12け半絶
縁性InP層、13 u n lJ’i InPm 1
クラッド層、14はノンドーグのInGaAsP活性層
、15はp型InP第2クラッド層、16はp型InG
aAsPキャップ層、17はp側電極、18はn側電極
を示す。 第 1 図 4
FIGS. 1(a) and (b) are cross-sectional views showing a conventional example of a semiconductor laser, FIG. 2 is a perspective view showing an embodiment of the present invention related to a semiconductor laser, and FIGS. 3(a) and (b) ld FIG. 2 is a 1θ one-view diagram illustrating the entire manufacturing process of the embodiment. In the figure, 1ltj: n-type ITIP substrate, 12 semi-insulating InP layers, 13 u n lJ'i InPm 1
cladding layer, 14 is a non-doped InGaAsP active layer, 15 is a p-type InP second cladding layer, 16 is a p-type InG
In the aAsP cap layer, 17 is a p-side electrode, and 18 is an n-side electrode. Figure 1 Figure 4

Claims (2)

【特許請求の範囲】[Claims] (1)発光領域への電流路を画定する半導体層として半
絶縁性半導体層を用いたことを特徴とする半導体発光装
置。
(1) A semiconductor light emitting device characterized in that a semi-insulating semiconductor layer is used as a semiconductor layer that defines a current path to a light emitting region.
(2)光電変換部を構成する半m体層及び該半導体層ど
−の電極との間に設けられた半導体層の側端部が、半絶
縁性半導体層に当接して終端してなることを特徴とする
特許請求の範囲81!1項記賊の半導体発光装置。
(2) The side end portion of the semiconductor layer provided between the semi-molar layer constituting the photoelectric conversion section and the electrode of the semiconductor layer is terminated by contacting the semi-insulating semiconductor layer. A semiconductor light emitting device according to claim 81!1, characterized in that:
JP57157206A 1982-09-07 1982-09-07 Semiconductor light emitting device Pending JPS5944887A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57157206A JPS5944887A (en) 1982-09-07 1982-09-07 Semiconductor light emitting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57157206A JPS5944887A (en) 1982-09-07 1982-09-07 Semiconductor light emitting device

Publications (1)

Publication Number Publication Date
JPS5944887A true JPS5944887A (en) 1984-03-13

Family

ID=15644520

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57157206A Pending JPS5944887A (en) 1982-09-07 1982-09-07 Semiconductor light emitting device

Country Status (1)

Country Link
JP (1) JPS5944887A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61191087A (en) * 1985-02-20 1986-08-25 Fujitsu Ltd Semiconductor light emitting device
EP0260475A2 (en) * 1986-09-18 1988-03-23 EASTMAN KODAK COMPANY (a New Jersey corporation) A process for forming a positive index waveguide
EP0261408A2 (en) * 1986-09-18 1988-03-30 EASTMAN KODAK COMPANY (a New Jersey corporation) Laser including monolithically integrated planar devices and processes for their preparation
JPH01215081A (en) * 1988-02-24 1989-08-29 Fujitsu Ltd Semiconductor light emitting device
FR2683392A1 (en) * 1991-11-06 1993-05-07 France Telecom PROCESS FOR PRODUCING OPTOELECTRONIC COMPONENTS BY SELECTIVE EPITAXY IN A SILLON.

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61191087A (en) * 1985-02-20 1986-08-25 Fujitsu Ltd Semiconductor light emitting device
EP0260475A2 (en) * 1986-09-18 1988-03-23 EASTMAN KODAK COMPANY (a New Jersey corporation) A process for forming a positive index waveguide
EP0261408A2 (en) * 1986-09-18 1988-03-30 EASTMAN KODAK COMPANY (a New Jersey corporation) Laser including monolithically integrated planar devices and processes for their preparation
JPH01215081A (en) * 1988-02-24 1989-08-29 Fujitsu Ltd Semiconductor light emitting device
FR2683392A1 (en) * 1991-11-06 1993-05-07 France Telecom PROCESS FOR PRODUCING OPTOELECTRONIC COMPONENTS BY SELECTIVE EPITAXY IN A SILLON.

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