JPS61191087A - Semiconductor light emitting device - Google Patents

Semiconductor light emitting device

Info

Publication number
JPS61191087A
JPS61191087A JP60031943A JP3194385A JPS61191087A JP S61191087 A JPS61191087 A JP S61191087A JP 60031943 A JP60031943 A JP 60031943A JP 3194385 A JP3194385 A JP 3194385A JP S61191087 A JPS61191087 A JP S61191087A
Authority
JP
Japan
Prior art keywords
layer
inp
ingaasp
added
diffraction grating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60031943A
Other languages
Japanese (ja)
Inventor
Masato Kondo
真人 近藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP60031943A priority Critical patent/JPS61191087A/en
Publication of JPS61191087A publication Critical patent/JPS61191087A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/10Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/12Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region the resonator having a periodic structure, e.g. in distributed feedback [DFB] lasers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/20Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/227Buried mesa structure ; Striped active layer
    • H01S5/2275Buried mesa structure ; Striped active layer mesa created by etching

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Semiconductor Lasers (AREA)
  • Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)

Abstract

PURPOSE:To obtain a distributed feedback type semiconductor laser, wherein leak currents are few even when a large current is injected and high speed modulation is possible, by using Fe added high-resistance InP as an embedded layer for narrowing a current. CONSTITUTION:On an n<+>-InP substrate 21, a diffraction grating 23 is formed. Then non-added InGaAsP 22 is grown on the diffraction grating 23. An Fe- added, high-resistance InP layer 30 is grown on the layer 22. An SiO2 film 27, in which a stripe shaped window (groove) 31 is patterned, is provided. The Fe-added, high-resistance InP 30 is selectively etched. Then the n-InGaAsP layer 22 is selectively etched. In this process, the diffraction grating 23 appears at the bottom of the groove. Then, an n-InGaAsP guide layer 24, a non-added InGaAsP active layer 25, a p-InP layer 26 and p-InGaAsP layer 33 are sequentially grown. Finally, an SiO2 film 32 having a stripe shaped window is deposited. Ti/Pt/Au is formed as a p-type electrode 28 on the film 32, and AuSn is formed as an n-type electrode 29 on the back surface of the substrate.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体発光装置C二係り、特C低閾値電流、
高出力、高効軍及び高速変調が可能な分布帰還型の半導
体レーザ装置C二関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor light emitting device C2, a special C low threshold current,
The present invention relates to a distributed feedback semiconductor laser device C2 capable of high output, high efficiency, and high speed modulation.

〔従来の技術〕[Conventional technology]

現在、数百メガビット/秒〜数ギガビット/秒という高
速変調時においても単一な縦モードで発振するレーデと
しては、分布帰還型(j)istribut*dp@a
dbaek ; DFB )レーザが主流である。従来
のDFBレーデC;は、第4図〜第6図の工うな主C二
6・りのタイプのDFBレーデがある。
Currently, as a radar that oscillates in a single longitudinal mode even during high-speed modulation of several hundred megabits/second to several gigabits/second, the distributed feedback type (j) istribut*dp@a
dbaek; DFB) lasers are the mainstream. Conventional DFB radars include the main types of DFB radars shown in FIGS. 4 to 6.

第4図は従来のDFBレーザの$1の例(埋込み型、 
BH,’ Buried H@t*rostructu
r* )であり、n −InP基板1の上C二項ζ二n
−InGaAsPガイド)m 2 、 InGaAsp
活性層5.p−InP上部クラッド層4及びキャップ層
のp−InGaAsP層8がi成されている。そして、
逆メナ構造C二より活性層34!:含む各成長層の幅が
規定されており、該逆メサ構造の両側Cp−InPj−
6及びn−InP層7が埋込まれる。さらC二酸化膜(
Sins)10の開孔七通してp−型電極9が設けられ
る。
Figure 4 shows a $1 example of a conventional DFB laser (embedded type,
BH,' Buried H@t*rostructu
r*), and the upper C binomial ζ2n of the n-InP substrate 1
-InGaAsP guide) m2, InGaAsp
Active layer 5. A p-InP upper cladding layer 4 and a p-InGaAsP layer 8 as a cap layer are formed in an i-formed structure. and,
Active layer 34 from reverse mena structure C2! : The width of each growth layer included is defined, and both sides of the inverted mesa structure Cp-InPj-
6 and n-InP layer 7 are buried. Sara C dioxide film (
A p-type electrode 9 is provided through seven of the openings 10.

動作時にはp−InP層4 、 n−InP層7 、 
p−InP基板1及びn+−InP基板1から形成され
るp−n−p−n 構造により、実線矢印の工うC二電
流がもれることが防止され、′磁流狭窄が行なわれる。
During operation, p-InP layer 4, n-InP layer 7,
The p-n-p-n structure formed from the p-InP substrate 1 and the n+-InP substrate 1 prevents the C2 current indicated by the solid arrow from leaking, and magnetic current confinement is performed.

ところが、成る程度大きな電流を流すと、 p−re層
4からp−InP層6に破線矢印のようなもれ電流が生
じ、これが引金とな・りて、p−n−p−nのナイリス
タ構造が導通する結果、電流狭窄が不十分C二なるとい
う欠点がある。また、第4図のように、半導体表面が平
坦にならないという欠点も生ずる。
However, when a large current is passed through the p-re layer 4 to the p-InP layer 6, a leakage current as shown by the broken line arrow occurs, which triggers the p-n-p-n. As a result of the conduction of the Nyristor structure, there is a drawback that current confinement becomes insufficient. Furthermore, as shown in FIG. 4, there is also the drawback that the semiconductor surface is not flat.

第5図は従来の第2例(平坦な埋込み型、 PBH;P
ムnsr Burled Heteroatructu
re )であって、第4図の各部と対応するようC二番
号を付しており、同一番号部C二ついては本質的C二は
第4図と同様である。
Figure 5 shows a second conventional example (flat embedded type, PBH;
Munsr Burled Heteroatructu
re), and is numbered C2 so as to correspond to each part in FIG. 4, and if there are two parts C2 with the same number, C2 is essentially the same as in FIG. 4.

この例の特徴はp−InP層11を設け、半導体素子表
面の平坦化を図った点にある。しかし、電流狭窄が不十
分な問題は改善されない。
The feature of this example is that a p-InP layer 11 is provided to planarize the surface of the semiconductor element. However, the problem of insufficient current confinement cannot be improved.

1g6図はD C−P BH(Doubts Chax
uxstPムnor Buried)fsterost
ructure )と呼ばわる構造であり、やはり、第
4図、第5図と番号を統一して示す。この第3の従来例
は、活性層34I:含むメナの両側に溝12゜13ヲ掘
−’)でp−InP層6及びn−InP @ 7 t’
埋込む点。
1g6 diagram is D C-P BH (Doubts Chax
uxstPmu nor Buried) fsterost
4 and 5, and the numbers are the same as in FIGS. 4 and 5. In this third conventional example, active layer 34I: grooves 12° to 13° are dug on both sides of the active layer 34I, including p-InP layer 6 and n-InP@7t'.
Point to embed.

及びその側方の埋込層(6,7)の下方(24元層(I
nGaAsP層6)が存在している点が特徴であ、る。
and below the embedded layers (6, 7) on its side (24-element layer (I
It is characterized by the presence of an nGaAsP layer 6).

この4元層によって、第6図C二示す(り七エミッタ。This quaternary layer creates an emitter as shown in Figure 6C.

■をペース、■をコレクタとするトランジスタ構造の利
得ゼ低下し、それにより上述のもれ電流(この場合は上
部クラッド層のp−InP4から埋込層のp−InP 
6 にもれる゛電流)によりp−n−p−nの狭窄機構
の働きが不十分になる問題を解決しようとするものであ
る。
The gain of the transistor structure with ■ as the pace and ■ as the collector decreases, and as a result, the leakage current (in this case, from p-InP4 in the upper cladding layer to p-InP4 in the buried layer) decreases.
This is an attempt to solve the problem in which the p-n-p-n constriction mechanism becomes insufficient due to the leakage of current.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記の従来の半導体レーデζ二共通する欠点は、(D電
流阻止層(=p−n−p−n接合を使っているので、高
電流注入時シニおいて、完全な電流阻止ができない、(
わ電流阻止層のp−n接合等C二起因する静電容量によ
り、十分な高速変調ができない、■活性層成長後(;、
2回目、3回目成長が必要なため、活性層に熱損傷が入
り易い、とい−クた点である。
The common drawbacks of the above conventional semiconductor radars are that (D current blocking layer (= p-n-p-n junction) is used, so when high current is injected, complete current blocking cannot be achieved.
(1) Sufficient high-speed modulation cannot be achieved due to the capacitance caused by C2 such as the p-n junction of the current blocking layer. (2) After the active layer grows (;
This is because the active layer is likely to be thermally damaged because the second and third growth steps are required.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は電流阻止層CFe(鉄)f:添加した高抵抗の
InPを用いることにより、上記問題点を解決するもの
である。
The present invention solves the above problems by using a current blocking layer CFe (iron) f: added high resistance InP.

第1図の本発明の実施例上様・りて本発明構成を説明す
ると、まず回折格子25 t−形成したInP基板21
上に、Fe添加1nP層301=よる高抵抗層を形成し
、選択エツtングCニエリストライプ状の#31を形成
した後、2回目成長時C二活性j@ 25等を成長せし
めている。
The structure of the present invention will be explained by referring to the embodiment of the present invention shown in FIG.
After forming a high-resistance layer of Fe-doped 1nP layer 301 on top, and forming #31 in the form of selectively etched C-niel stripes, C2-activated J@25 etc. are grown during the second growth.

〔作用] 上記本発明の精成IニエればF@f添加した高抵抗のI
nP/jig用いて′電流累子層を形成したので、リー
ク電流を減少させることができ、また電流阻止層に起因
する静電容量を減少することができ、その結果高速変調
を可能にする。
[Function] If the refined I of the present invention is used, the high-resistance I added with F@f
Since the current collector layer is formed using nP/jig, leakage current can be reduced, and capacitance due to the current blocking layer can be reduced, resulting in high-speed modulation.

本発明において、特にFe添加のInP Jt高抵抗層
に用いたのは、再現性良く妬抵抗;抵抗率t5 X10
”Ω・副程度またはこれ以上が得られることが明らか6
二な・つた為である。FeはInPl二添加すると、デ
ィープ・レベルの不純物として働き、安定した高抵抗層
が得られている。これζ二対し、他のディープ・レベル
をつくるであろうと考えられる不純物、例えばCo(コ
バルト)は安定して高抵抗が得られていない。またNl
 にッケル)は、InPの結晶性を損う欠点がある。ま
た、Cd、 Zn、 Mn 等の比較的浅いレベルの不
純物を添加することも考えられるが、その制御が困難で
あり、p型層が形成され易く、再現性良く高抵抗層が得
られない。
In the present invention, the InP Jt high-resistance layer doped with Fe has a high resistance with good reproducibility; resistivity t5
”It is clear that Ω・minor level or higher can be obtained6
Second, it is for ivy. When Fe is added to InPl2, it acts as a deep level impurity and a stable high resistance layer is obtained. On the other hand, other impurities that are thought to create a deep level, such as Co (cobalt), do not provide a stable high resistance. Also Nl
Nickel) has the disadvantage of impairing the crystallinity of InP. It is also possible to add a relatively shallow level of impurities such as Cd, Zn, Mn, etc., but it is difficult to control, a p-type layer is likely to be formed, and a high-resistance layer cannot be obtained with good reproducibility.

次に、本発明(:J:れば、2回目成長時(:活性層上
成長する為、従来より活性層形成後の熱処理回数が少な
くて済み、活性層への熱損傷が少なくな   ”る利点
が生ずる。
Next, if the present invention (:J:) is used, the second growth (::Grows on the active layer, so the number of heat treatments after forming the active layer is reduced compared to the conventional method, and thermal damage to the active layer is reduced. Benefits arise.

〔実施例〕〔Example〕

以下、第1図、第2図(=示す本発明の実施例上解説す
る。
The following will explain the embodiments of the present invention shown in FIGS. 1 and 2.

第21囚参照 ■まず、(100) n+−InP基vjL21上シニ
、干渉露光と化学エツチングCニエリ、ピツy−397
0X、深さ1000又の回折格子231に形成する。
Refer to Prisoner 21■ First, (100) n+-InP group vjL21, interference exposure and chemical etching C Nyeri, Pit Y-397
A diffraction grating 231 of 0x and depth of 1000 is formed.

第2図(Bl 0次に、回折格子23上C二、無添加(undopsd
 ) InGaAaP(λ、、=t、1s l1m’)
 224r:約0.2μ、その上C二Fe添加高抵抗I
nP #50 t’約2μm成長する。この成長はLP
E (液相成長法)或いはMOC’VD(有機金属原料
ガスを用いた化学堆積法)等が使用される。
Figure 2 (Bl 0th order, C2 on the diffraction grating 23, undoped (undopsd)
) InGaAaP (λ, , = t, 1s l1m')
224r: Approximately 0.2μ, high resistance I with addition of C2Fe
nP #50 t' grows to about 2 μm. This growth is LP
E (liquid phase growth method) or MOC'VD (chemical deposition method using organometallic raw material gas) is used.

成長温度はInへのFaの溶解度を上げるため、約70
0℃とする。高温成長のため、回折格子23の熱変形が
懸念されるため、成長開始までGa Asワエハによ・
りてInP基板の表面上カバーすると良い(QaAsワ
エハの使用で経験上良い結果が得られている)。LPE
(:よる場合、Fe添加InPのメルトの組成は、In
: P: Fe =1 g:20mg:15mgである
The growth temperature is approximately 70°C to increase the solubility of Fa in In.
The temperature shall be 0°C. Due to the high temperature growth, there is a concern about thermal deformation of the diffraction grating 23, so the GaAs wafer is not used until the start of growth.
It is best to cover the surface of the InP substrate by using a QaAs wafer (good results have been obtained from experience using a QaAs wafer). LPE
(:), the composition of the Fe-added InP melt is In
: P: Fe = 1 g: 20 mg: 15 mg.

第2図(C)、の)参照 0幅3μmのストライプ状の窓(溝)51がパターニン
グされた810宜膜27f:設け、HCL : Ha 
PO番;3:1でFe添加高抵抗InP層30を選択エ
ツチングし、次にHa 304 : Hoot : H
鵞0= 90 : 5 : 5でn−InGaAsP層
22ヲ選択エツチングする。この過程で溝の底部に回折
格子23が現われること(=なる。
Refer to FIG. 2(C), 810 film 27f patterned with a striped window (groove) 51 having a width of 3 μm: Provided, HCL: Ha
The Fe-added high resistance InP layer 30 is selectively etched with PO number: 3:1, and then Ha 304 : Hoot : H
The n-InGaAsP layer 22 is selectively etched at a ratio of 0=90:5:5. During this process, a diffraction grating 23 appears at the bottom of the groove.

第2図(鱒参照 ■n−InGaAsP (22% =t1sμm)ガイ
ド層24.無添加InGaAaP活性層(λ−=1.5
μm) 2S 、 p−InPクラッド層26.及びp
−InGaAsPキャップ層33ヲ順次成長する。成長
開始温度は600℃(LPE)である。各層のキャリア
濃度と膜厚は次のようにする1キャリア濃度(n又はp
)  膜4(d)n−InGaAaP層p    n 
= 5 X 10”tM−’、   d = 0.1μ
m(ガイドIII) (Sn添加) InGaAiP活性層*     n−1X 10”c
rR−”、   d=o、15/Jm(無添加) p−InPクラッド層s    P=5X101?3−
”、   d=2μm(Ca添加) p(nGaAsPキャップ層:  II=4×10”m
−’、   d==o、2/Jmなお、多層成長時の冷
却速度は毎分約17℃である。
Figure 2 (see trout ■ n-InGaAsP (22% = t1s μm) guide layer 24. Additive-free InGaAaP active layer (λ- = 1.5
μm) 2S, p-InP cladding layer 26. and p
- The InGaAsP cap layer 33 is sequentially grown. The growth starting temperature is 600°C (LPE). The carrier concentration and film thickness of each layer are calculated as follows: 1 carrier concentration (n or p
) Film 4 (d) n-InGaAaP layer p n
= 5 x 10"tM-', d = 0.1μ
m (Guide III) (Sn addition) InGaAiP active layer* n-1X 10”c
rR-”, d=o, 15/Jm (no additives) p-InP cladding layer s P=5X101?3-
”, d=2μm (Ca addition) p(nGaAsP cap layer: II=4×10”m
-', d==o, 2/Jm Note that the cooling rate during multilayer growth is about 17° C. per minute.

(り最後(=幅2綿のストライプ状の窓のあいた5il
l膜32を堆積し、その上C二p型電f4i28として
Ti/Pt/Auを、そして基板裏面にn型電J429
としてAu8nt’形成する。
(The end (= 2 widths of 5ils with a striped window)
1 film 32 is deposited, Ti/Pt/Au is deposited on top of it as a C2p-type conductor f4i28, and an n-type conductor J429 is deposited on the back side of the substrate.
As a result, Au8nt' is formed.

■共振器長4t!150μmとしてへき関し、ファブリ
・ペロモードの発振を抑制する為、へき開端1i1i4
1:Si、N、膜(反射防止膜)でコーティングするこ
とにより、第1図の分布帰還型半導体レーザが完成する
■Resonator length 4t! In order to suppress Fabry-Perot mode oscillation, the cleavage ends 1i1i4 are cleaved to 150 μm.
1: By coating with Si, N, film (antireflection film), the distributed feedback semiconductor laser shown in FIG. 1 is completed.

第3図は本発明の他の実施例を示すものである。FIG. 3 shows another embodiment of the invention.

先の′S2図ではpq電極2Bが活性層25の上甚二位
置するストライプ状の窓があいた5ICh膜62の上g
二全面にわたって形成されているが、その構造では、ス
トライプ外部C二金属/絶縁物/半導体構造が全dii
il=わたって存在することC二なる。したがって寄生
容量により高速変調特性C二悪影響を及ぼすことが考え
られる。そこで、これを改善しょうというのが第6図の
実施例であって、21g1目の埋込み成長が終了した後
、活性層25の上部6二対応した位置艦二幅50μmの
ストライプ状のSiO2膜(図示せず)4r:堆積し、
これをマスクC二用いて、臭素/メタノール=α2チに
エリs P W InGaA膳PキャップII 55 
、 p型1nPクラッドII 26 、 InGaAs
P活性層25 、 n−InGaAmPガイド層24 
、 Fe添加InP電流阻止層(高抵抗InP層)30
を全体で1.5μm程度の深さC二除去する。
In the previous figure 'S2, the pq electrode 2B is located on the upper part of the 5ICh film 62 with a striped window located on the active layer 25.
However, in that structure, the stripe external C two metal/insulator/semiconductor structure is formed over the entire dii
il = exists across C2. Therefore, it is conceivable that the parasitic capacitance adversely affects the high-speed modulation characteristic C2. Therefore, the embodiment shown in FIG. 6 is an attempt to improve this. After the filling growth of the first part of the active layer 25 is completed, a striped SiO2 film with a width of 50 μm is formed at a position corresponding to the upper part 62 of the active layer 25 ( (not shown) 4r: deposited;
Using this mask C2, remove bromine/methanol = α2.
, p-type 1nP clad II 26 , InGaAs
P active layer 25, n-InGaAmP guide layer 24
, Fe-doped InP current blocking layer (high resistance InP layer) 30
is removed to a total depth of about 1.5 μm.

その後、StO,膜(図示せず)を除去し、p−InG
aAiPキャップ層33上C二、p型’XE極28とし
て、Ti/Pt/Au t’ストライプ状ζ二形成する
After that, the StO film (not shown) was removed, and the p-InG
On the aAiP cap layer 33, Ti/Pt/Au t' stripes are formed as the p-type XE electrode 28.

本実施例(:J:れば、寄生容量の減少C二より、更C
;良好な高速変調特性が得られる。
In this example (:J:, from the reduction of parasitic capacitance C2, the
; Good high-speed modulation characteristics can be obtained.

〔発明の効果〕〔Effect of the invention〕

本発明では、以上のととくFe添加高抵抗InP4電流
狭窄のための纏込J−とすることC二より、高電流注入
時≦二おいても電流のリークが少なく、高速変調が可能
な分布帰還型半導体レーデが提供される。また、その製
造上、成長時(=活性層への熱損傷が少ないという利点
がある。
In the present invention, from the above-mentioned Fe-doped high resistance InP4 lumped J- for current confinement C2, current leakage is small even when high current is injected ≦2, and high-speed modulation is possible. A feedback semiconductor radar is provided. In addition, there is an advantage in manufacturing that there is less thermal damage to the active layer during growth.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の斜視図、 第2図(4)〜(鱒は本発明の一実施例の製造工程図、
第5図は本発明の他の実施例の断面図、第4図〜第6図
はそれぞれ従来の分布帰還型半導体レーザであり、第4
図は埋込み型、第5図は平坦な埋込み型、第6図は2重
チャン卆ルのついた平坦埋込み型の要部断面図。 主な符号 21・・・♂−1nP基板 22 =・(無添加) InGaAsP24− n−I
nGaAsP (ガイドa>25 ・(無添加) In
GaAsP (活性層)26−= p−InP (クラ
ッド#)28・・・p型電極 29・・・n型電極
Figure 1 is a perspective view of an embodiment of the present invention; Figures 2 (4) to (trout are manufacturing process diagrams of an embodiment of the present invention;
FIG. 5 is a sectional view of another embodiment of the present invention, and FIGS. 4 to 6 are respectively conventional distributed feedback semiconductor lasers.
The figure is a recessed type, FIG. 5 is a flat recessed type, and FIG. 6 is a sectional view of the main part of a flat recessed type with a double channel. Main code 21...♂-1nP substrate 22 = (no additive) InGaAsP24- n-I
nGaAsP (Guide a>25 (no additives) In
GaAsP (active layer) 26-=p-InP (cladding #) 28...p-type electrode 29...n-type electrode

Claims (1)

【特許請求の範囲】[Claims]  回折格子を有するInP基板上のFe添加の高抵抗I
nPの電流阻止層と、該電流阻止層に形成された溝と、
該溝に順に埋込まれたガイド層、活性層及びクラッド層
の各成長層とを有することを特徴とする半導体発光装置
Fe-doped high resistance I on InP substrate with diffraction grating
an nP current blocking layer; a groove formed in the current blocking layer;
A semiconductor light emitting device comprising a guide layer, an active layer, and a cladding layer, which are sequentially embedded in the groove.
JP60031943A 1985-02-20 1985-02-20 Semiconductor light emitting device Pending JPS61191087A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60031943A JPS61191087A (en) 1985-02-20 1985-02-20 Semiconductor light emitting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60031943A JPS61191087A (en) 1985-02-20 1985-02-20 Semiconductor light emitting device

Publications (1)

Publication Number Publication Date
JPS61191087A true JPS61191087A (en) 1986-08-25

Family

ID=12345044

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60031943A Pending JPS61191087A (en) 1985-02-20 1985-02-20 Semiconductor light emitting device

Country Status (1)

Country Link
JP (1) JPS61191087A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0390077A2 (en) * 1989-03-30 1990-10-03 Oki Electric Industry Co., Ltd. Laser diode and method for fabricating of the same
JPH02275796A (en) * 1989-01-13 1990-11-09 Nec Corp Gas phase growth and preparation of semiconductor laser having embedded structure

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58114478A (en) * 1981-12-26 1983-07-07 Fujitsu Ltd Semiconductor laser
JPS5944887A (en) * 1982-09-07 1984-03-13 Fujitsu Ltd Semiconductor light emitting device
JPS59197182A (en) * 1983-04-25 1984-11-08 Nec Corp Distribution feedback type semiconductor laser

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58114478A (en) * 1981-12-26 1983-07-07 Fujitsu Ltd Semiconductor laser
JPS5944887A (en) * 1982-09-07 1984-03-13 Fujitsu Ltd Semiconductor light emitting device
JPS59197182A (en) * 1983-04-25 1984-11-08 Nec Corp Distribution feedback type semiconductor laser

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02275796A (en) * 1989-01-13 1990-11-09 Nec Corp Gas phase growth and preparation of semiconductor laser having embedded structure
EP0390077A2 (en) * 1989-03-30 1990-10-03 Oki Electric Industry Co., Ltd. Laser diode and method for fabricating of the same

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