JP2550714B2 - High-resistance semiconductor layer embedded semiconductor laser - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a high-resistance semiconductor layer-embedded semiconductor laser capable of high-speed modulation.

(Prior Art) With the construction of an advanced information society, the capacity of optical communication systems and the sophistication of communication networks are being advanced. One of the effective means for increasing the capacity of an optical communication system is to increase the modulation speed. 2. Description of the Related Art In an optical communication system in which a light source is modulated at ultra-high speed to achieve high speed, a semiconductor laser excellent in high speed response is required.

In recent years, as a buried layer for effectively confining a current only in the active region of a semiconductor laser and also effectively confining light in the active region due to a difference in refractive index, a technique using a high resistance semiconductor layer utilizing a deep level in a semiconductor has been proposed. It is attracting attention and is being actively researched and developed.

In the semiconductor laser using the high-resistance semiconductor layer as the buried layer, the pn junction current block layer is not used for the current confinement to the active region, so that the parasitic capacitance is small and high-speed modulation is possible.

As shown in FIG. 7, a conventional structure example of a semiconductor laser using a high resistance semiconductor layer as a buried layer is sandwiched between a first clad layer 41 and a second clad layer 43 formed on a semiconductor substrate 40. Both sides of the striped active layer 42 are filled with a high-resistance semiconductor layer 44 having a deep level for trapping electrons or holes, and current is effectively injected into the active layer. In the figure, 45 is a contact layer, 46 is an insulating film, and 47.
And 48 indicate electrodes.

(Problems to be Solved by the Invention) In the above-described conventional technique, p / SI / is used because the semi-insulating semiconductor layer (SI) that captures only one of the electron and the hole is used in the current blocking layer. In the n-structure part, the hole current from the p-layer due to double injection flows and becomes a leakage current that flows outside the active region, which increases the threshold current, lowers the external differential quantum efficiency, and lowers the maximum output. It was causing deterioration. Therefore, it has been difficult to obtain a high-performance semiconductor laser using the high resistance semiconductor layer as the current blocking layer by the conventional technique.

It is an object of the present invention to provide a high-resistance semiconductor layer-embedded semiconductor laser capable of high-speed modulation by overcoming the above-mentioned drawbacks of the prior art.

(Means for Solving the Problems) In order to solve the above problems, a high-resistance semiconductor layer-embedded semiconductor laser according to the present invention comprises a first conductivity type first clad layer, an active layer, and A double heterostructure semiconductor laser including at least a second clad layer having a conductivity type opposite to that of the first clad layer, the stripe-shaped mesa including the active layer, and current blocking layers provided on both sides of the mesa. The current blocking layer includes at least a semi-insulating semiconductor layer having a deep level for trapping electrons and a semi-insulating semiconductor layer having a deep level for trapping holes. The semi-insulating semiconductor layer having a level is formed so as to be in contact only with the n-type semiconductor layer, and the semi-insulating semiconductor layer having a deep level for trapping holes is formed so as to be in contact only with the p-type semiconductor layer.

(Operation) FIG. 5 (a) is an energy band diagram when a p-type semiconductor layer, a semi-insulating semiconductor layer having a deep electron trap level, and an n-type semiconductor layer are contacted and a forward bias voltage is applied. is there. Further, FIG. 5B is an energy band diagram when a p-type semiconductor layer, a semi-insulating semiconductor layer having a deep hole trapping level, and an n-type semiconductor layer are brought into contact with each other and a forward bias voltage is applied. is there.

In the conventional high resistance semiconductor layer embedded type semiconductor laser,
Since the p-type clad layer, the high resistance semiconductor layer and the n-type clad layer are directly connected to each other and a bias voltage is applied in the forward direction when the semiconductor laser is driven, an energy band diagram shown in FIG. 5 (a) or (b) is obtained. Is equivalent to

Therefore, in the case of a semi-insulating semiconductor layer having a deep electron trap level, electrons and holes recombine near the interface between the p-type cladding layer and the semi-insulating semiconductor layer, and a recombination current flows. In the case of a semi-insulating semiconductor layer having a deep hole trap level, electrons and holes recombine near the interface between the n-type cladding layer and the semi-insulating semiconductor layer, and a recombination current flows.

On the other hand, FIG. 6 (a) shows an energy band diagram of the current blocking layer in the structure of the present invention described above.

Electrons injected from the n-type cladding layer are trapped by the semi-insulating semiconductor layer having a deep electron trap level, and holes injected from the p-type cladding layer are a semi-insulating semiconductor layer having a deep hole trap level. Since they are captured by the layer, recombination of electrons and holes is suppressed.

Further, FIG. 6 (b) shows an energy band diagram of the current blocking layer.

Since the semi-insulating semiconductor layer having a deep electron trap level is surrounded by the n-type semiconductor layer, holes are not recombined with the electrons trapped in the deep level of the semi-insulating semiconductor layer. Further, since the semi-insulating semiconductor layer having a deep hole trapping level is surrounded by the p-type semiconductor, electrons are not recombined with the holes trapped in the deep level of the semi-insulating semiconductor layer. . Furthermore, the n-type semiconductor layer and the p-type semiconductor layer inserted between the semi-insulating semiconductor layer having a deep electron trap level and the semi-insulating semiconductor layer having a deep hole trap level are in contact with each other over a wide area. However, since the n-type semiconductor layer sandwiches the n-type cladding layer or the n-type substrate and the semi-insulating semiconductor layer, electrons are not supplied to the n-type semiconductor layer, while the p-type semiconductor layer is p-type.
Since the type clad layer or the p-type cap layer and the semi-insulating semiconductor layer are sandwiched, holes are not supplied to the p-type semiconductor layer, and no current flows in this pn coupling.

As described above, in the high-resistance-layer-embedded semiconductor laser according to the present invention, there is almost no leakage current, and the injection current is effectively converted into light in the active layer. Therefore, low threshold current and high external differential quantum efficiency are obtained. , High light output can be expected.

(Example) Next, this invention is demonstrated with reference to drawings.

FIG. 1 is a sectional view showing a semiconductor structure related to one embodiment of the present invention. In this example, an example of an indium phosphide (InP) -based material that is a long-wavelength-based material will be described.

The semiconductor laser having this structure is obtained through the following steps. First, sulfur (S) -doped n-type InP substrate with (100) plane
Silicon (Si) -doped n-type InP layer 18 [n = 1 × 10 ¹⁸ cm ^-3 ], using metal organic chemical vapor deposition (MOVPE) on 11
An indium-gallium-arsenic-phosphorus (InGaAsP) active layer 19 having a band gap of 1 μm and an emission wavelength of 1.55 μm and a thickness of 0.15 μm and a zinc (Zn) -doped p-type InP layer 2
0 [p = 1 × 10 ¹⁸ cm ^-3 ] with a thickness of 1.5 μm and Zn doping p
Type InGaAsP contact layer 17 [p = 1 × 10 ¹⁹ cm ^-3 ]
Epitaxial growth of 0.5 μm continuous.

Next, by a CVD technique and a photolithography technique, a SiO ₂ stripe mask having a thickness of about 2000 Å and a width of 2 μm is formed at intervals of 300 μm in the <011> direction. afterwards,
P type InGaAsP contact layer 17, p by chemical etching
The type InP layer 20, the InGaAsP active layer 19, and the n-type InP layer 18 are etched so that the height of the mesa stripe is 3.5 μm.

Further, with the SiO ₂ stripe-shaped mask left, the high resistance InP layer 1 with iron (Fe) doping in the concave portion of the mesa stripe 1
2 is 1.5 μm thick, titanium (Ti) -doped high resistance InP layer 1
Selectively epitaxially grow 5 with a thickness of 2.0 μm by MOVPE so that the whole is flat. After removing the SiO ₂ striped mask with ammonium fluoride, the total thickness is 12
Polished to about 0 μm, p-type semiconductor side, and n
The electrode 10 on the mold semiconductor substrate side is formed by a vacuum vapor deposition method, annealed, and then cleaved into individual semiconductor lasers, and the whole processing is completed, and the semiconductor laser shown in FIG. 1 is completed.

2 to 4, the semi-insulating semiconductor layer for trapping electrons of the above current block is in contact only with the n-type semiconductor layer, and the semi-insulating semiconductor layer for trapping holes is the p-type semiconductor layer. A cross-sectional view of an embodiment configured for contact only with is shown.

The semiconductor laser shown in FIG. 2 is obtained as follows. That is, the S-doped n-type InP substrate 11 having the (100) plane
Using MOVPE on top, Si-doped n-type InP layer 18 [n = 1
X 10 ¹⁸ cm ^-3 ], and the InGaAsP active layer 19 having a bandgap with an emission wavelength of 1.55 μm is 0.15 μm and Zn.
Doping p-type InP layer 20 [p = 1 × 10 ¹⁸ cm ^-3 ] with a thickness of 0.1
μm, and epitaxial growth is performed continuously.

Next, by a CVD technique and a photolithography technique, a SiO ₂ stripe mask having a thickness of about 2000 Å and a width of 2 μm is formed at intervals of 300 μm in the <011> direction. afterwards,
0.1 μm thick p-type InP layer 20 by chemical etching, InGa
The AsP active layer 19 and the n-type InP layer 18 have a mesa stripe height of 1.
Etch to 5 μm.

Further, while leaving the SiO ₂ stripe-shaped mask, the Fe-doped high-resistance InP layer 12 is 1.5 μm thick in the concave portion of the mesa stripe, and the Si-doped n-type InP layer 13 [n = 4 × 10 ¹⁸ cm
^-3 ], 0.4 μm thick, Zn-doped p-type InP layer 14 [p = 7
× 10 ¹⁷ cm ^-3 ], 0.4 μm thick, Ti-doped high resistance InP layer
15 is selectively epitaxially grown with a thickness of 1.2 μm MOVPE. After removing the SiO ₂ stripe-shaped mask with ammonium fluoride, a 2.5 μm thick Zn-doped p-type InP layer 16 [p] is formed on the 0.1 μm-thick p-type InP layer 20 and the Ti-doped high resistance InP layer 15. = 7 × 10 ¹⁷ cm ^-3 ], MOVPE epitaxially grows so that the surface becomes flat, and then Zn
Doping p-type InGaAsP contact layer 17 [p = 1 × 10 ¹⁹ c
m ⁻³ ] is epitaxially grown by MOVPE with a thickness of 0.5 μm.

Finally, polish until the total thickness is about 120 μm,
The electrodes 10 on the p-type semiconductor side and the n-type semiconductor substrate side are formed by a vacuum vapor deposition method, annealed, and then cleaved into individual semiconductor lasers to complete the whole process, and the semiconductor laser shown in FIG. 2 is produced. Go up.

Next, the semiconductor laser shown in FIG. 3 is obtained as follows. First, Zn-doped p-type InP substrate 21 with (100) plane
Using MOVPE on top, Zn-doped p-type InP layer 23 [p = 1
X 10 ¹⁸ cm ^-3 ], and the InGaAsP active layer 19 having a bandgap with an emission wavelength of 1.55 μm is 0.15 μm and Si.
Doping n-type InP layer 24 [n = 1 × 10 ¹⁸ cm ^-3 ] with a thickness of 0.1
μm, and epitaxial growth is performed continuously.

Next, by a CVD technique and a photolithography technique, a SiO ₂ stripe mask having a thickness of about 2000 Å and a width of 2 μm is formed at intervals of 300 μm in the <011> direction. afterwards,
0.1 μm thick n-type InP layer 24 by chemical etching, InGa
The AsP active layer 19 and the p-type InP layer 23 have a mesa stripe height of 1.
Etch to 5 μm.

Furthermore, with the SiO ₂ stripe-shaped mask left, a Ti-doped high-resistance InP layer 15 having a thickness of 1.5 μm and a Zn-doped p-type InP layer 14 [p = 7 × 10 ¹⁷ cm] is formed in the concave portion of the mesa stripe.
^-3 ] is 0.4 μm thick and Si-doped n-type InP layer 13 [n = 4
× 10 ¹⁸ cm ^-3 ], 0.4 μm thick, Fe-doped high resistance InP layer
12 is 1.2 μm thick and is selectively epitaxially grown by MOVPE. After removing the SiO ₂ striped mask with ammonium fluoride, a 2.5 μm-thick Si-doped n-type InP layer 18 [n] is formed on the 0.1-μm-thick n-type InP layer 24 and the Fe-doped high-resistance InP layer 12. = 1 × 10 ¹⁸ cm ^-3 ], epitaxially grown by MOVPE so that the surface becomes flat.
Doped n-type InGaAsP contact layer 22 [n = 1 × 10 ¹⁹ c
m ^-3 ], with a thickness of 0.5 μm, is epitaxially grown by MOVPE.

Finally, polish until the total thickness is about 120 μm,
The electrodes 10 on the p-type semiconductor side and the n-type semiconductor substrate side are formed by a vacuum vapor deposition method, annealed, and then cleaved into individual semiconductor lasers, and the whole processing is completed, and the semiconductor laser shown in FIG. 3 is completed. .

In the embodiment shown in FIGS. 2 and 3, the Fe-doped high resistance InP layer 12 and the p-type InP 16, 20, and 23 mesa portions are in contact with each other, and the Ti-doped high resistance InP layer 15 and n are formed.
This also includes the case where the mesa portions of the type InP layers 18 and 24 are in contact with each other.

Next, steps for obtaining the semiconductor laser shown in FIG. 4 will be described. First, on the S-doped n-type InP substrate 11 having the (100) plane, MOVPE is used to form the Si-doped n-type InP layer 18 [n
= 1 × 10 ¹⁸ cm ^-3 ], and the InGaAsP active layer 19 having a bandgap with an emission wavelength of 1.55 μm is 0.15 μm.
m, Zn-doped p-type InP layer 20 [p = 1 × 10 ¹⁸ cm ⁻³ ] with a thickness of 1.5 μm, Zn-doped p-type InGaAsP contact layer 17
[P = 1 × 10 ¹⁹ cm ⁻³ ] is continuously epitaxially grown to a thickness of 0.5 μm.

Next, a SiO ₂ stripe mask having a thickness of 2000 Å and a width of 2 μm is formed at 300 μm intervals in the <011> direction by the CVD technique and the photolithography technique. After that, p-type InGaAsP contact layer 17 and p-type InP are chemically etched.
The layer 20, the InGaAsP active layer 19, and the n-type InP layer 18 are etched so that the height of the mesa stripe is 3.5 μm.

Further, with the SiO ₂ stripe-shaped mask left, the high resistance InP layer 1 with iron (Fe) doping in the concave portion of the mesa stripe 1
2 is 1.5 μm thick, Si-doped n-type InP layer 13 [n = 4 × 1
0 ¹⁸ cm ^-3 ], 0.4 μm thick, Zn-doped p-type InP layer 14
Selective epitaxial growth of [p = 7 × 10 ¹⁷ cm ⁻³ ] with a thickness of 0.4 μm and titanium (Ti) -doped high resistance InP layer 15 with a thickness of 1.2 μm by MOVPE is performed so that the entire surface becomes flat. Si
After removing the O ₂ stripe mask with ammonium fluoride, polish it until the total thickness is about 120 μm, and p
The electrodes 10 on the side of the type semiconductor and the side of the n-type semiconductor substrate are formed by vacuum vapor deposition, annealed, and then cleaved into individual semiconductor lasers, and the whole process is completed, and the semiconductor laser shown in FIG. 4 is completed.

If the high-resistance semiconductor layer-embedded semiconductor laser described above is applied to an InP-based long-wavelength semiconductor laser, there is almost no reactive current flowing except in the active layer, and a VSB type (V-grooved Substrate) using a pn junction in the block layer is used. Buried Heterost
ructure Lasers) and DC-PBH type (Double Channel Planar
Buried Heterostructure Lasers) with a threshold current around 10mA and a single-sided external quantum efficiency around 30%.

Further, since the high resistance semiconductor layer having a thickness of 2 to 3 μm is used for the current blocking layer, the parasitic capacitance is 4 to 5 pF and is practically used as a light source for an optical communication system of several gigabits per second (Gb / sec) class. It can be used enough.

It should be noted that in the above-described embodiment, it can be realized even if the substrate is a semi-insulating semiconductor, and can be realized even if the material system is GaAs system, and even if it is DFB (Distributed Feed Back). Therefore, it can be realized even if the active region has a quantum well structure.

(Effects of the Invention) As described in detail above, according to the present invention, electrons and holes are separately trapped in the deep level of the semi-insulating semiconductor layer, so that low threshold current and high external differential quantum efficiency are obtained. There is an effect that it is possible to realize a high-resistance semiconductor layer-embedded semiconductor laser having ultrahigh-speed modulation characteristics.

Further, according to the present invention, the semi-insulating semiconductor layer having a deep electron trap level is surrounded by the n-type semiconductor layer, and the semi-insulating semiconductor layer having a deep hole trap level is surrounded by the p-type semiconductor layer. It has the effect of preventing current and realizing low threshold current, high external differential quantum efficiency, and ultra-high speed modulation characteristics.

[Brief description of drawings]

FIG. 1 is a sectional view showing a structure relating to one embodiment of a high resistance semiconductor embedded semiconductor laser according to the present invention, and FIGS.
FIG. 4 is a sectional view showing the structure of another embodiment of the high-resistance semiconductor layer-embedded semiconductor laser according to the present invention, and FIG. 5 (a).
Is a diagram showing a hand structure in which an n-type semiconductor layer, a semi-insulating semiconductor layer having a deep electron trap level, and a p-type semiconductor layer are in contact with each other, and a forward bias is applied to the n-type semiconductor layer, and FIG. Type semiconductor layer, a semi-insulating semiconductor layer having a deep hole trap level, and a p-type semiconductor layer are in contact with each other, and a band structure when a forward bias is applied thereto, FIG.
-Type semiconductor layer, a semi-insulating semiconductor layer having a deep electron trap level, a semi-insulating semiconductor layer having a deep hole trap level, a diagram showing a band structure when the p-type semiconductor layer is in contact,
FIG. 6B shows an n-type semiconductor layer, a semi-insulating semiconductor layer having a deep electron trap level, an n-type semiconductor layer, a p-type semiconductor layer, a semi-insulating semiconductor layer having a deep hole trap level,
The figure which shows the band structure when a p-type semiconductor layer contact | connects, 7th
FIG. 1 is a sectional view showing the structure of a conventional semiconductor laser having a high resistance current blocking layer. 10 ... Electrode, 11 ... n-type InP substrate, 12 ... Fe-doped high resistance InP layer, 13 ... n-type InP layer, 14 ... p-type InP layer, 15
…… Ti doping high resistance InP, 16 …… p type InP layer, 17 ……
p-type InGaAsP contact layer, 18 ... n-type InP layer, 19 ... In
GaAsP active layer, 20 ... P-type InP layer, 21 ... P-type InP substrate, 2
2 ... n-type InGaAsP contact layer, 23 ... p-type InP layer, 24
... n-type InP layer, 40 ... semiconductor substrate, 41 ... first cladding layer, 42 ... active layer, 43 ... second cladding layer, 44 ...
… High resistance semiconductor layer, 45 …… contact layer, 46 …… insulating film, 47 …… electrode, 48 …… electrode.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-61-230387 (JP, A) JP-A-61-290790 (JP, A) JP-A-3-49282 (JP, A)

Claims (1)

(57) [Claims] 1. A double heterostructure semiconductor laser including at least a first conductivity type first cladding layer, an active layer, and a second conductivity type second cladding layer opposite to the first cladding layer on a semiconductor substrate. And a semi-insulating semiconductor layer having a stripe-shaped mesa including the active layer and current blocking layers provided on both sides of the mesa, wherein the current blocking layer has a deep level for capturing at least electrons, and The semiconductor layer includes a semi-insulating semiconductor layer having a deep level for trapping holes, and the semiconductor layer having a deep level for trapping electrons is in contact with only the n-type semiconductor layer and has a deep level for trapping holes. A high-resistance semiconductor layer-embedded semiconductor laser, wherein the insulating semiconductor layer is formed so as to contact only the p-type semiconductor layer.