JPH077232A - Optical semiconductor device - Google Patents

Abstract

PURPOSE:To perform at a time the growth of a buried part having a current narrowing structure of a thyristor structure, without increasing a process of photolithography, and to prevent a fogging growth in an optical semiconductor device prepared by a selective growth wherein a (111) B side appears. CONSTITUTION:An active area on an n-substrate 1 of a III-V compound semiconductor is held between an n-clad layer on the lower side and a p-clad layer on the upper side, and since the area is formed by a selective growth, the laterail side is made two (111) B faces. On the opposite sides thereof, p, n-block layers 12 and 13a are present in this sequence from below and further a P<+> thin buried layer is present thereon. Due to diffusion of p-type impurities from this layer during a crystal growth, the upper part of the n-block layer on the upper side of the active area is p-inverted (13b). At the time of the growth of the block layers, the opposite sides of the active area become faces of a high order. Therefore the speed of a vapor growth becomes high and the thickness becomes large. On the other hand, the (n) layer above the active area becomes so thin that it can be p-inverted with case.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical semiconductor device, and more particularly, to a compound semiconductor light emission having a double heterojunction structure formed by selective growth utilizing the plane orientation dependence of the crystal growth rate and a current block structure. The present invention relates to a semiconductor device including at least one of a device, a modulator, an optical amplifier and an optical waveguide.

[0002]

2. Description of the Related Art In recent years, active research has been made on a double heterojunction structure of a III-V compound semiconductor laser which is formed by utilizing selective growth and has both sides thereof as (111) planes. These are (111) in the metal organic chemical vapor deposition method (hereinafter referred to as MO-VPE method).
The property that the crystal growth rate on the B-plane is extremely slower than that on the other crystal plane is positively utilized. Examples thereof include JP-A-2-288283 "Method for manufacturing semiconductor laser device" and JP-A-2-268482 "Method for manufacturing embedded semiconductor laser device".

A conventional, typical optical semiconductor device of this type will be described with reference to FIGS. First, as shown in FIG. 12, two strap-like shapes extending in a [0-1-1] direction having a width of 4 μm and a gap of 3 μm on an n-InP substrate 1 having a (100) surface as a surface. A silicon dioxide film 2 is formed and n-I is formed by a low pressure MO-VPE method.
The nP cladding layer 3 having a thickness of 0.8 μm and the double heterojunction structure 4 are sequentially crystal-grown. Double hetero structure 4
Is n-In having a composition (abbreviated as 1.2 μm composition. The same applies hereinafter) having a forbidden band width corresponding to a wavelength of 1.2 μm.
GaAsP guide layer 5, InGaAs / InGaAsP
Of the MQW layer 6 consisting of 5 layers and a p-type of 1.2 μm composition.
It has a structure in which InGaAsP guide layers 7 are sequentially stacked. Subsequently, the p-InP cladding layer 8 is crystal-grown. Here, the growth of the p-InP clad layer 8 is stopped when the (111) B planes 9 on the growth side surfaces on both sides are combined and the sectional shape of the selective growth is just a triangle. This is (111) compared to other crystal planes in vapor phase growth.
The fact that the crystal growth rate on the B surface is extremely slow is used. The reason for forming the triangle is that if the growth is insufficient, the n-InP block layer 13 described later remains at the apex of the triangle, and if the growth is too much, the (111) B plane is broken and becomes a higher surface. Therefore, the purpose of utilizing the (111) B plane having a slow growth rate cannot be achieved.

Next, as shown in FIG. 13, the central portions of the two striped SiO ₂ films 2 are removed by 2 μm each, and two striped silicon dioxide films 1 having a width of 2 μm are removed.
Using 1 as a growth inhibition mask, the p-InP block buried layer 12 and the n-InP block layer 13 are crystal-grown. At this time, the side surface of the first selective growth portion is (111) B.
Since it is face 9, it hardly grows here. However, from the position where the (111) B surface 9 and the (100) surface exposed after the removal of the silicon dioxide film 2 intersect, (211)
A plane corresponding to the (311) plane is formed from the plane, and this is
Crystals grow at a higher growth rate than the (100) plane. Therefore, the p-InP block buried layer 12 and the n-InP block layer 13 are (111) on the side surface of the double heterojunction structure 4.
The B surface 9 is deposited so as to rise up. At this time, n-In
At the stage where the P block layer 13 does not cover the triangular p-InP clad layer 8 above the double heterojunction structure 4, as shown in FIG. 14, the next p-InP buried layer 15 is formed.
Then, the p ⁺ -InGaAs contact layer 16 is grown.

According to this method, the n-InP block layer 13 is formed.
However, the growth layer thickness is adjusted so as not to cover the apex portion of the p-InP cladding layer 8 of the ridge portion 10 having a triangular sectional shape. JP-A-2-288283 "Manufacturing Method of Semiconductor Laser Device" Similarly, the method disclosed in Japanese Unexamined Patent Publication No. 2-268482, "Method for manufacturing embedded semiconductor laser device" is exactly the same.

After the above crystal growth is completed, as shown in FIG. 14, a silicon dioxide film 17 is formed, and then a surface electrode 18 is formed by a vapor deposition method, a sputtering method or the like so that the wafer has a thickness of 100 μm. Back surface polishing is performed to form back surface electrode 19
Is formed over the entire surface. The surface electrode 18 is CrAu-TiPt.
The Au film and the back electrode are AuGe-AuNi films.

[0007]

In the conventional semiconductor light emitting device described above, in the buried growth of the n-InP block layer, the n-InP block layers on both sides grow along the (111) B plane, and the cross section is changed. Be careful not to cover the upper part of the triangular p-InP clad layer with n-InP.
It is very delicate and difficult to control the layer thickness of the block layer, and there is a drawback that a high manufacturing yield cannot be obtained. Also,
In terms of crystal structure design as well, in order to prevent fogging on the apex of the p-InP clad layer having a triangular cross-section, n-
There was a problem that the thickness of the InP block layer could not be made sufficiently thick and the current confinement was insufficient.

Further, as a problem of the above-mentioned conventional example,
The growth has to be stopped just at the time when the triangular shape in cross section formed by the two (111) B planes is formed in the first selective growth, but this is very difficult to control, reproducibility, in-plane wafer Uniformity cannot be obtained. In particular, the closer to the top of the triangle, the higher the crystal growth rate becomes, and it is extremely difficult to control this.

[0009]

An optical semiconductor device of the present invention comprises a first semiconductor layer of a first conductivity type, a second semiconductor layer having a narrower band gap and a larger refractive index than the first semiconductor layer, and At least a double heterojunction structure in which a third semiconductor layer of a second conductivity type having a wider forbidden band width and a smaller refractive index than the second semiconductor layer is sequentially laminated, A ridge portion selectively formed on the main surface,
A second conductive type semiconductor block layer covering the second semiconductor layer on the side surface of the double heterojunction structure, the second semiconductor layer, and the one main surface adjacent to the double heterojunction structure; The third semiconductor layer and the second side surface of the heterojunction structure excluding the top and the vicinity thereof.
An optical semiconductor including a first conductivity type block layer in contact with the conductivity type semiconductor block layer, and a second conductivity type fourth semiconductor layer in contact with the top of the double heterojunction structure and the first conductivity type block layer. It has a dielectric film provided on each of the one main surface on both sides of the device and the optical semiconductor device.

Further, according to the present invention, one of the two block layers having different conductivity types is formed by the entire surface crystal growth and the diffusion by the selective growth mask before the selective growth for forming the SCH-MQW layer. A means for solving the problem of the conventional example is provided in which only one buried block layer is formed after the selective growth. That is, the present invention relates to a compound optical semiconductor device having an optical waveguide, in which optical waveguide or optical amplification,
Alternatively, the light-absorbing active layer is adjacent to the first-conductivity-type clad layer having a larger forbidden band width than the active layer on the compound semiconductor substrate side, and is above the second-conductivity-type clad layer having a larger forbidden band width than the active layer. The first conductivity type clad layer, the active layer, and the second conductivity type clad layer are adjacent to the layer, and the first conductivity type clad layer, the active layer, and the second conductivity type clad layer are directly above the second conductivity type semiconductor layer laminated on the first conductivity type compound semiconductor substrate. A selectively formed ridge portion, and the second conductive type semiconductor layer between the compound semiconductor substrate and the ridge portion is converted to the first conductive type by diffusion before forming the ridge portion. Further, the ridge portion is characterized by being surrounded by a first conductive type block layer and a second conductive type semiconductor layer, respectively.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will now be described with reference to the drawings along with its manufacturing process.

First, as shown in FIG. 2, n-In
P substrate 1 has a plane orientation (100) plane with a width of 4 μm and an interval of 3 μm.
Two striped silicon dioxide films 2 extending in the [0-1-1] direction are formed by m, and the n-InP cladding layer 3 and the double heterojunction structure 4 are continuously grown by the low pressure MO-VPE method. . The double heterojunction structure 4 is composed of 1.2 μm composition and 60 nm thick n-InGa in order from the bottom.
AsP guide layer 5, having a total thickness of 75 nm, can be regarded as a semiconductor film having a photoluminescence peak wavelength of 1.55 μm M
QW multilayer film 6 (having an InGaAs-InGaAsP multilayer structure), 1.2 μm composition, p-thickness of 60 nm
It is composed of an InGaAsP guide layer 7. Next, the p-InP clad layer 8 is crystal-grown continuously. p-In
The P-clad layer 8 does not need to have a triangular cross-sectional shape as described in the section of the related art, and has a trapezoidal cross-sectional shape (upper side length 0.4 μm to 0.7 μm) of the ridge portion 10A (3 to
8) is formed. This ridge portion has a structure in which a double heterojunction structure is sandwiched between clad layers.

Next, as shown in FIG. 3, the ridge portion sides of the two striped silicon dioxide films 2 are 2 μm each.
The two striped silicon dioxide films 11 having a width of 2 μm are left as a growth prevention mask, and the reduced pressure MO-V is applied.
The p-InP block layer 12 and the n-InP block layer 13 are crystal-grown by the PE method. In the figure, a p-InP block layer 12a and an n-In layer are formed on top of the p-InP clad layer.
Although shown as forming the P block layer 13a, these may or may not be covered on the top of the p-InP cladding layer 8. However, n-I
The nP block layer 13a is controlled to have a thickness of 0 to 0.02 μm. When forming the n-InP block layer 13, (11
1) A large amount of the crystal growth gas raw material is consumed in a region having a high growth rate that rises above the B-plane 9.
The growth rate at the top of the p-InP cladding layer 8 sandwiched between them is significantly slowed down, and the layer thickness of the n-InP block layer 13a can be easily controlled to 0.2 μm or less. In contrast,
The side surface has a high growth rate and can have a layer thickness of 0.6 μm.

Next, while the growth rate of InP is reduced to 1/10 or less, the supply flow rate of the p-type impurity gas such as diethylzinc is increased ten times as much as when the p-InP block layer 12 is formed.
As shown in FIG. 1, a p ⁺ -InP buried layer 14 having a thickness of 0.15 μm is formed (growth rate is, for example, 0.1 μm /
h). Alternatively, after depositing an undoped InP layer, P
It may be exposed to mold impurity gas. As a result of this, p ⁺ −
During the growth of the InP burying layer 14, zinc having a large diffusion coefficient diffuses in the solid phase, and the surface portion of the n-InP block layer 13a is p-type.
Due to the difference in the layer thickness of the -InP layer, all 13a at the top of the p-InP cladding layer 8 is p-inverted, and the side surface portion is 0.4 μm.
The n-InP block layer 13a of m remains. After that, the p-InP clad buried layer 15, p +
-InGaAs contact layer 16 is crystal-grown.

On this epitaxial wafer, p ⁺ -I
A silicon dioxide film 17 opened on the nGaAs contact layer 16 is formed. On this wafer, a surface electrode 18
Then, the back surface is polished so that the thickness of the wafer is 100 μm, and the back surface electrode 19 is formed on the entire surface. The surface electrode is C
rAu-TiPtAu, the back electrode is AuGe-AuNi
And is formed by vapor deposition and sputtering.

After forming the ridge portion, the p-InP block layer 12 or the p ⁺ -InGaAsP contact layer 16 is formed.
Can be formed in the same MO-VPE growth apparatus without the need for a photolithography step, so that the steps can be simplified. In addition, even if the n-InP block layer 13 is formed thickly, p ⁺ -InP is formed from above.
Since the buried layer 14 is formed and the n-type layer at the top of the ridge portion can be inverted to p-type, a thyristor structure capable of sufficient current confinement can be realized.

Next, a second embodiment of the present invention will be described. First, as in the first embodiment, as shown in FIG. 4, two striped silicon dioxide films 2 are formed on an n-InP substrate 1 and n-I is formed by a low pressure MO-VPE method.
The nP clad layer 3 and the double heterojunction structure 4 are continuously grown. Next, the p-InP clad layer 8 is continuously formed.
a is 0.4 μm and the p ⁺ -InP clad layer 8b is 0.2 μm.
μm crystal grows. In the p ⁺ -InP clad layer 8b,
Zinc is doped at a higher concentration than the p-InP clad layer 8a. The p ⁺ -InP cladding layer 8b does not need to have a triangular sectional shape. Thus, the ridge portion 10B having a trapezoidal cross-section (consisting of 3 to 8b) is formed.

Next, as shown in FIG. 5, the ridge portions of the two striped silicon dioxide films 2 are 2 μm each.
Then, the p-InP block layers 12 and 12a, the undoped i-InP block layer 20, and the n-InP block layer 13 are crystal-grown by the low pressure MO-VPE method. i-
The InP block layer 20 has a top of 0.1 μm or less, n
-InP block layer 13 has a top of 0.1 to 0.2 μm.
Control to a thickness of m. Since the growth rate is slow at the top of the ridge, these can be easily controlled. On the other hand, since the growth rate of the side surface is high, the i-InP block layer 20 has
Is 0.2 μm, and the n-InP block layer 13 is 0.4 μm.
The layer thickness can be set. At this stage of growth, i-In
A portion of the P block layer in contact with the p ⁺ -InP clad layer 8b is p-InP due to zinc diffusion generated during crystal growth.
It becomes the layer 20a.

Next, while maintaining the growth of InP, the supply flow rate of the p-type impurity gas is increased ten times as much as when the p-InP block layer 12 is formed, the growth rate is reduced to 1/10 or less, and p ⁺ -InP burying layer 15 is grown. Diethyl zinc is used as the p-type impurity gas. At this time, zinc diffuses in the solid phase, and a part of the n-InP block layer 13 becomes the p-InP layer 13b as shown in FIG. At this time, the n-InP block layer is entirely p-inverted at the top of the ridge portion due to the difference in layer thickness, and the region of the InP clad layer 20a which is p-inverted by zinc diffusion from the p ⁺ -InP clad layer 8b is widened. As a result, a sufficiently wide p region can be obtained at the top of the ridge. On the other hand, the side surface is 0.3
The μm n-InP block 13a remains. After that, the p-InP clad buried layer 15 and P ⁺ − are continuously formed as they are.
The InGaAs contact layer 16 is crystal-grown. The formation of the final silicon dioxide film 17 and the formation of electrodes are the same as in the first embodiment.

In this embodiment, the p ⁺ -InP cladding layer 8 is used.
Due to the presence of b, the n-InP block layer 13 and the i-
There is an advantage that the p-inversion of the covered portion of the InP block layer can be performed more reliably.

1 and 5 of the first and second embodiments described above
The 5 μm semiconductor laser has a small leakage current and a very high laser oscillation yield of about 80%, and the main characteristics such as threshold current and external differential quantum efficiency are improved by 20 to 30% compared with the conventional one. It was

The structures of the first and second embodiments described above can be used for a semiconductor laser (the MQW multilayer film 6 serves as a light emitting layer), but in addition, the semiconductor optical modulators (5, 6, 7 are It serves as an absorption layer), a semiconductor optical amplifier, an optical waveguide and an integrated device thereof, and has a wide range of applications. The ridge portion of this embodiment has a structure in which a double heterostructure is sandwiched between cladding layers, but a single semiconductor layer is sandwiched between semiconductor layers having a wider forbidden band width and a smaller refractive index. You may comprise a ridge part with a heterojunction structure.

In the above embodiments, the InGaAsP / InGaAs optical device on the InP substrate was described, but other III-V group compound semiconductors such as AlGa are used.
It goes without saying that it can be applied to As / GaAs type and AlGaInP / GaAs type optical elements.

Next, a third embodiment of the present invention will be described with reference to the drawings. So far, the optical semiconductor element on the n-type substrate has been described, but the above description does not essentially change even if the conductivity type is reversed. Hereinafter, a p-type substrate will be described as an example.

First, as shown in FIG. 7, a reduced pressure M is formed on a p-InP substrate 21 having a surface orientation of (100).
The n-InP block layer 22 is made 0.4 by the O-VPE method.
Grows on the entire surface with a width of 4 μm and a gap of 0.8 μ
Two striped silicon dioxide films 2 extending in the opened [0-1-1] direction are formed. MO this wafer
Installed in a VPE furnace, the furnace pressure is set to 75 Torr, and the wafer temperature is raised to 500 ° C. while flowing phosphine (PH ₃ ). At this stage, dimethyl zinc is supplied to diffuse zinc to a depth of 0.45 μm, and in the zinc diffusion region 23, the n-InP block layer 22 in the mask opening is inverted. Then, the wafer temperature is continuously set to 625 ° C. and the p-InP clad layer 8 and the double heterojunction structure 4 are continuously grown. The double heterojunction structure 4 comprises, in order from the bottom, a p-InGaAsP guide layer 7 having a composition of 1.2 μm and a thickness of 60 nm, and InGaA.
s / 1.2 μm composition InGaAsP is composed of 5 layers of MQW multilayer film 6 having a total thickness of 75 nm and a photoluminescence peak wavelength of 1.55 μm, and an n-InGaAsP guide layer 5 having a composition of 1.2 μm and a thickness of 60 nm. ing. Next, the n-InP clad layer 3 is crystal-grown continuously.

Next, the double heterojunction structure 4 side of the two striped silicon dioxide films 2 is removed by 2 μm each, and the two striped silicon dioxide films 11 with a width of 2 μm are left as growth inhibition masks. As shown in FIG. 8, the p-InP block layer 12 is crystal-grown by the low pressure MO-VPE method. At this time, the p-InP block layer 12 is
At the stage of covering the side surface of the double heterojunction structure 4 and not covering the triangular n-InP cladding layer 3 on the upper portion of the double heterojunction structure 4, switching to the growth of the next n-InP cladding buried layer 24, Finally n ⁺ -InGaA
The s contact layer 25 is formed.

On this epitaxial wafer, n ⁺ -I
A silicon dioxide film 17 having an opening above the nGaAs contact layer 25 is formed. Further, the front surface electrode 18 is formed on this wafer, the back surface is polished so that the thickness of the wafer is 100 μm, and the back surface electrode 19 is formed on the entire surface. The front surface electrode 18 is CrAu-TiPtAu, and the back surface electrode 19 is Au.
Ge-AuNi, which is formed by vapor deposition and sputtering.

In the first and second embodiments described above,
Since the distance between the double heterojunction structure 4 and the n-InP substrate 1 was long, it was not possible to manufacture the DFB-LD substantially. Since the distance to the heterojunction structure 4 can be reduced, the DFB-LD can be manufactured. In fact, D
When manufacturing the FB-LD, a diffraction grating is formed on the n-InP block layer 22 before the stripe-shaped silicon dioxide film 2 is formed at the stage where the n-InP block layer 22 is first grown over the entire surface. It should be formed.

Although the optical semiconductor device on the p-type substrate is described here, it is essentially the same on the n-type substrate in the case where the conductivity types are opposite to each other. You can think about it by reversing the mold.

Next, a fourth embodiment of the present invention will be described with reference to the drawings. First, as in the third embodiment, as shown in FIG. 9, a reduced pressure MO is applied to the p-type InP substrate 21.
The n-InP block layer 22 is 0.4 μm thick by the -VPE method.
m Full-scale growth. On top of that, a width of 4 μm and a gap of 1.2 μ
Two striped silicon dioxide films 2a opened are formed. At this time, a 2000 angstrom-thickness whole surface silicon dioxide film is formed, and a resist pattern is formed by photolithography, and then O2 plasma treatment is performed to weaken the adhesion between the resist and the silicon dioxide film. Then, when the silicon dioxide is etched with buffered hydrofluoric acid, the edges are tapered off. Using this stripe-shaped silicon dioxide film 2a as a mask, zinc diffusion is performed with a diffusion depth of 0.45 μm. Since the zinc diffusion region 23 has an opening of 1.2 μm in the stripe-shaped silicon dioxide film 2a, it can be controlled to have a width of 2.1 μm on the surface of the n-InP block layer 22 even in consideration of lateral diffusion. . When zinc is diffused and then the entire surface is etched by buffered hydrofluoric acid for 1000 angstroms, the edge portion of the silicon dioxide recedes by 0.3 μm, and the mask opening portion widens in a self-aligned manner as shown in FIG. At this time, the stripe-shaped silicon dioxide film 2b has a thickness of 1000 Å and an opening width of 1.8 μm.

In the following, exactly the same as the third embodiment, p-I
nP clad layer 8, double heterojunction structure 4, nI
The nP cladding layer 3 is crystal-grown. Next, the two heterojunction structure side portions of the two striped silicon dioxide films 2b are removed by 2 μm each, and as shown in FIG.
The p-InP block layer 12, n was formed by the low pressure MO-VPE method.
The -InP clad buried layer 24 and the n + InGaAs contact layer 25 are crystal-grown, and finally, the silicon dioxide film 17 and the surface electrode 18 are formed in the same manner as in the third embodiment.

In this embodiment, compared with the third embodiment, the distance between the double heterojunction structure 4 and the n-InP block layer 22 which is not p-inverted can be shortened, so that the leakage current of the device can be reduced. There are advantages.

The four embodiments have been described above.
And a method of eliminating the block layer covered on the double heterojunction structure 4 which is the feature of the second embodiment by diffusion during crystal growth, and the two block layers described in the third and fourth embodiments. The method of forming one of them in a self-aligned manner prior to selective growth can also be used in combination, which is an important application example for DFB-LD and the like.

[0034]

As described above, according to the present invention, in the first and second embodiments, by forming the high-concentration second conductivity type semiconductor layer on the first conductivity type block layer, the number of times of crystal growth
First selective growth while forming a thyristor structure with a sufficiently thick block layer excellent in current confinement on both sides of the ridge part including the double heterojunction structure without increasing the photolithography process. It is possible to reliably prevent the second conductivity type block layer from covering the top portion (first conductivity type) of the ridge portion formed in (1). Therefore, the leakage current of the optical semiconductor device can be reduced, and the optical semiconductor device can be manufactured with a high yield.

On the other hand, in the third and fourth embodiments, n-
If the InP block layer is formed before the selective growth,
Since the number of block-embedded layers for selective growth can be reduced to one, control of block embedding can be facilitated. Therefore,
It is possible to control the ridge portion in a triangular shape in the first selective growth even if it is slightly deviated, and as in the first and second embodiments, the current confinement property is provided on both sides of the double heterojunction structure. It is possible to form a thyristor-structured block layer having a sufficient thickness, and p is formed on the first selective growth portion.
It is possible to prevent the -InP block layer from being covered with a sufficiently high yield. Therefore, it has the effect of reducing the leak current of the semiconductor laser, further reducing the threshold current, and improving the differential quantum efficiency.

If the first and second embodiments are combined with the third and fourth embodiments, the yield can be improved and the performance can be improved more remarkably.

The structure described above is applied to, for example, 1.55 μm.
When applied to a band semiconductor laser, the laser oscillation yield was improved, and the main characteristics, that is, the threshold current and the slope efficiency, were improved by 20 to 30% as compared with the conventional one.

Further, in the third and fourth embodiments, since the active layer position can be set at a position lower than the selective growth start surface, it is difficult to control the composition of the active layer during selective growth, which has been difficult in the past. However, there is an advantage that it becomes easy. Furthermore, DFB
When the LD is manufactured, the grating position is usually placed on the selective growth start surface, so that the conventional method substantially reduces the DFB.
Although it was difficult to manufacture a -LD, the method of the present invention can also manufacture a DFB-LD, and an integrated device of a modulator and a DFB-LD, which takes advantage of the characteristics of selective growth, and other The manufacture of optical integrated devices has also become easier.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a semiconductor chip showing a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of a semiconductor chip for explaining the manufacturing method according to the first embodiment.

FIG. 3 is a cross-sectional view of a semiconductor chip for explaining a next process of the process corresponding to FIG.

FIG. 4 is a sectional view of a semiconductor chip for explanation of a second embodiment of the present invention along with its manufacturing process.

FIG. 5 is a cross-sectional view of a semiconductor chip for explaining a next process of the process corresponding to FIG.

FIG. 6 is a cross-sectional view of a semiconductor chip showing a second embodiment of the present invention.

FIG. 7 is a cross-sectional view of a semiconductor chip for explanation of a third embodiment of the present invention along with its manufacturing process.

FIG. 8 is a cross-sectional view of a semiconductor chip showing a third embodiment of the present invention.

FIG. 9 is a sectional view of a semiconductor chip for explanation of a fourth embodiment of the present invention along with its manufacturing process.

FIG. 10 is a cross-sectional view of a semiconductor chip for explaining a next process of the process corresponding to FIG.

FIG. 11 is a sectional view of a semiconductor chip showing a fourth embodiment of the present invention.

FIG. 12 is a cross-sectional view of a semiconductor chip for explanation of a conventional example along the manufacturing process thereof.

FIG. 13 is a cross-sectional view of the semiconductor chip for explaining the next step of the step corresponding to FIG.

FIG. 14 is a cross-sectional view of a semiconductor chip showing a conventional example.

[Explanation of symbols]

1 n-InP substrate 2, 2a, 2b Striped silicon dioxide film 3 n-InP cladding layer 4 Double heterojunction structure 5 n-InGaAsP guide layer 6 MQW multilayer film 7 p-InGaAsP guide layer 8, 8a p-InP cladding layer Layer 8b p ⁺ -InP clad layer 9 (111) B surface 10, 10A, 10B Ridge portion 11,17 Silicon dioxide film 12 p-InP block layer 13, 13a, 22 n-InP block layer 13b p-InP layer 14 p ⁺ -InP burying layer 15 p-InP burying layer 16 p ⁺ -InGaAsP contact layer 18 surface electrode 19 back electrode 20 i-InP block layer 20a p-InP layer 21 p-InP substrate 23 zinc diffusion region 24 n-InP clad burying layer Layer 25 n ⁺ -InGaAs contact layer

Claims (9)

[Claims] 1. A first semiconductor layer of a first conductivity type, the first semiconductor layer.
Second semiconductor layer having a narrower forbidden band width and a larger refractive index than the second semiconductor layer and a third semiconductor layer of a second conductivity type having a wider forbidden band width and a smaller refractive index than the second semiconductor layer are sequentially stacked. A ridge portion having at least a double heterojunction structure and selectively formed on one main surface of the first conductivity type compound semiconductor substrate; the second semiconductor layer on the side surface of the double heterojunction structure; Second semiconductor layer and a second conductivity type semiconductor block layer covering the one main surface adjacent to the double heterojunction structure, and the third semiconductor on the side surface excluding the top and the vicinity of the double heterojunction structure Layer and a first conductivity type block layer in contact with the second conductivity type semiconductor block layer, and a second conductivity type fourth semiconductor layer in contact with the top of the double heterojunction structure and the first conductivity type block layer When The optical semiconductor device characterized by having an optical semiconductor element and each provided with a dielectric film on the one main surface of both sides of the optical semiconductor device comprising. 2. The optical semiconductor device according to claim 1, wherein the second semiconductor layer is a multilayer film having a multiple quantum well structure. 3. A zinc-blende-type crystal compound semiconductor substrate (1
The double heterojunction structure having both sides (111) B planes is provided in a region sandwiched by two striped dielectric films extending in the [0-1-1] direction on the (00) plane. Alternatively, the optical semiconductor device according to the item 2. 4. The optical semiconductor device according to claim 1, wherein the third semiconductor layer is doped at a higher concentration on the top side of the double heterojunction structure than on the remaining portion thereof. 5. In a compound optical semiconductor device having an optical waveguide, an active layer for optical waveguide, light amplification, or light absorption has a forbidden band width larger than that of the active layer on the compound semiconductor substrate side. Is adjacent to the second conductive type clad layer having a band gap larger than that of the active layer. The first conductive type clad layer, the active layer, and the second conductive type clad layer are adjacent to the layer. A ridge portion selectively formed immediately above a semiconductor layer of the second conductivity type laminated on a compound semiconductor substrate of the first conductivity type, wherein the second conductivity between the compound semiconductor substrate and the ridge portion. Type semiconductor layer is converted to the first conductivity type by diffusion before forming the ridge portion, and the side and upper sides of the ridge portion are blocks of the first conductivity type, respectively. Layer, surrounded by a second conductivity type semiconductor layer An optical semiconductor device characterized in that 6. The optical semiconductor device according to claim 5, wherein the active layer is a multilayer film having a multiple quantum well structure. 7. The compound semiconductor is a zinc blende type crystal, and the ridge portion including the active layer has a striped region extending in the [0-1-1] direction on the (100) plane as a bottom face. The optical semiconductor device according to claim 5, wherein both side surfaces are (111) B planes. 8. A portion of the first conductivity type block layer on the side of the ridge portion covers the upper portion of the ridge portion, and the entire upper portion of the first conductivity type block layer is evenly provided with a first portion. 8. The impurity of the second conductivity type is diffused to leave the first conductivity type portion in the lateral portion of the first conductivity type block layer and to convert the upper portion to the second conductivity type. Optical semiconductor device. 9. The optical semiconductor device according to claim 5, wherein the top side of the second-conductivity-type cladding layer is more highly doped than the remaining portion.