JPH01215081A - Semiconductor light emitting device - Google Patents

Semiconductor light emitting device

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Publication number
JPH01215081A
JPH01215081A JP4104188A JP4104188A JPH01215081A JP H01215081 A JPH01215081 A JP H01215081A JP 4104188 A JP4104188 A JP 4104188A JP 4104188 A JP4104188 A JP 4104188A JP H01215081 A JPH01215081 A JP H01215081A
Authority
JP
Japan
Prior art keywords
layer
current
inp
emitting device
light emitting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4104188A
Other languages
Japanese (ja)
Inventor
Shoji Isozumi
五十棲 祥二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4104188A priority Critical patent/JPH01215081A/en
Publication of JPH01215081A publication Critical patent/JPH01215081A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To increase a maximum light output by forming, between one clad layer and a current contraction layer, a semiconductor layer which is of an opposite conductivity type to that of a clad layer. CONSTITUTION:In a double-hetero structure in which the top and bottom surfaces of an active layer 2 are connected to clad layers 1 and 3 respectively, a p-InP layer 7 is formed between the n-InP clad layer 1 and an SI-InP current constricting layer 6. Leak current and an input capacitance of the SI-InP current constricting layer 6 are made small as usual. In the p-InP layer 7, electrons from the n-clad layer 1 are recombined inside to keep the electrons from being injected to the current constricting layer 6. Therefore, carries injected to SI-InP which forms the current constricting layer 6 are only holes from the p-clad layer 3. And, the input current required to take insulation from the current constricting layer 6 gets remarkably larger than usual. By this method, this semiconductor light emitting device increases its maximum light output, keeping the leak current and the input capacitance small.

Description

【発明の詳細な説明】 〔概 要〕 活性層の上下面がそれぞれクラッド層に接合し、  て
なるダブルヘテロ構造と、ダブルヘテロ構造の両側を埋
めた半絶縁性半導体の電流狭窄層とを有する半導体発光
装置に関し、 最大光出力の向上を目的とし、 一方のクラッド層と電流狭窄層との間に該クラフト層と
は反対導電型の半導体層が介在しているように構成する
[Detailed Description of the Invention] [Summary] The upper and lower surfaces of the active layer are respectively bonded to the cladding layer, and the active layer has a double heterostructure, and a semi-insulating semiconductor current confinement layer that fills both sides of the double heterostructure. A semiconductor light emitting device is configured such that a semiconductor layer of a conductivity type opposite to that of the craft layer is interposed between one cladding layer and a current confinement layer for the purpose of improving maximum light output.

〔産業上の利用分野〕[Industrial application field]

本発明は、活性層の上下面がそれぞれクラッド層に接合
してなるダブルヘテロ構造と、ダブルヘテロ構造の両側
を埋めた半絶縁性半導体の電流狭窄層とを有する半導体
発光装置に関する。
The present invention relates to a semiconductor light emitting device having a double heterostructure in which the upper and lower surfaces of an active layer are respectively bonded to cladding layers, and a semi-insulating semiconductor current confinement layer filling both sides of the double heterostructure.

上記半導体発光装置は、レーザ光を発して例えば光通信
の光信号源などに用いられるものであり、:後述のよう
に、改良された特性を有するものの、最大光出力が低く
、最大光出力の向上が望まれている。
The semiconductor light emitting device described above emits laser light and is used, for example, as an optical signal source for optical communications.As described below, although it has improved characteristics, the maximum optical output is low and the maximum optical output is low. Improvement is desired.

〔従来の技術〕[Conventional technology]

第2図は従来の半導体発光装置の要部側断面図である。 FIG. 2 is a side sectional view of the main part of a conventional semiconductor light emitting device.

第2図において、1はn−1nPのクラッド層、2はI
nGaAs Pの活性層、3はp、−1nPのクランド
層、4はp”−1nGaAs Pのコンタクト層、5は
p−InP層5a及びn −1nPIii5bからなる
電流狭窄層、である。
In FIG. 2, 1 is an n-1nP cladding layer, 2 is an I
An active layer of nGaAs P, 3 a p, -1nP ground layer, 4 a p"-1nGaAs P contact layer, and 5 a current confinement layer consisting of a p-InP layer 5a and an n-1nPIii 5b.

活性層2は、幅が1〜2μ−程度で、クラッド層1及び
クラッド層3と接合してダブルヘテロ構造を形成し、電
流狭窄層5は、InPM5a、5bが形成するpn接合
5cを有して、ダブルヘテロ構造の両側の広い領域を埋
めている。
The active layer 2 has a width of about 1 to 2 μ- and is bonded to the cladding layer 1 and the cladding layer 3 to form a double heterostructure, and the current confinement layer 5 has a pn junction 5c formed by InPM 5a and 5b. , filling a large area on both sides of the double heterostructure.

この半導体発光装置は、コンタクト層4側からクラッド
層1側に向けて通電すると、逆方向のpn接合5cの存
在により大半の電流が活性層2に集中して光を発し、電
流を成る値(I th :発振しきい値電流)より大き
くするとレーザ発振を起こしてレーザ光を発する。
In this semiconductor light emitting device, when current is passed from the contact layer 4 side to the cladding layer 1 side, most of the current is concentrated in the active layer 2 due to the existence of the pn junction 5c in the opposite direction and emits light, and the current becomes a value ( I th : oscillation threshold current) When the current is increased, laser oscillation occurs and laser light is emitted.

しかしながら、p−クラッド層3とp −1nP層5a
の一部が相互に繋がっているため、p−クラッド層3か
らp−1nP層5aを通りn−クラッド層lに抜けるリ
ーク電流が存在する。その様子は、活性層3の部分が形
成する順方向のダイオードをDI、p−1nP層5aに
よる抵抗をR,p−1nP層5aとn−クラフト層1が
形成する順方向のダイオードをD2、で示した第3図の
回路図のようであり、ダイオードD2の立ち上がり電圧
がダイオードD1のそれより大きいとはいえ、上記リー
ク電流は可なり大きなものである。そしてこのリーク電
流は1thを太き(しη(発振効率)を低下させる問題
となる。
However, the p-cladding layer 3 and the p-1nP layer 5a
Since some of the layers are connected to each other, there is a leakage current flowing from the p-cladding layer 3 to the n-cladding layer l through the p-1nP layer 5a. In this case, the forward direction diode formed by the active layer 3 is DI, the resistance by the p-1nP layer 5a is R, the forward direction diode formed by the p-1nP layer 5a and the n-Craft layer 1 is D2, Although the rising voltage of the diode D2 is larger than that of the diode D1, the leakage current is quite large. This leakage current becomes a problem in that it increases 1th and reduces η (oscillation efficiency).

また、チップ全面の中の広い領域を占める電流狭窄層5
には、pn接合が形成する容量が存在するため、入力容
量が300μ−角程度のチップで10〜100pFにも
なり、高速で動作させようとした際に問題となる。
In addition, the current confinement layer 5 occupies a wide area within the entire surface of the chip.
Since there is a capacitance formed by the pn junction, the input capacitance is as high as 10 to 100 pF for a chip of approximately 300 μ-square, which poses a problem when attempting to operate at high speed.

第4図は、上述のリーク電流及び入力容量が小さくなる
ように改良された半導体発光装置の従来例の要部側断面
図である。
FIG. 4 is a sectional side view of a main part of a conventional example of a semiconductor light emitting device that has been improved to reduce the leakage current and input capacitance described above.

第4図に示す従来例は、第3図で述べた半導体発光装置
の電流狭窄層5をSt −In P (半絶縁性InP
)単層構成の電流狭窄層6に変えたものである。このS
l −In Pは、一般にFeなどの不純物を導入して
半絶縁性にしである。従って、電流狭窄層6にはpn接
合がなく、p−クラッド層3から電流狭窄層6を通りn
−クラッドFilに至る間は、pin構造となっている
In the conventional example shown in FIG. 4, the current confinement layer 5 of the semiconductor light emitting device described in FIG.
) The current confinement layer 6 has a single layer structure. This S
1-InP is generally made semi-insulating by introducing impurities such as Fe. Therefore, there is no pn junction in the current confinement layer 6, and the n
- It has a pin structure up to the cladding film.

このことから、先に述べたリーク電流及び入力容量が共
に微小になって、I”thが小さくηが大きく且つ高速
動作が可能になっている。
As a result, both the leakage current and the input capacitance mentioned above become small, I''th is small, η is large, and high-speed operation is possible.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながらこの従来例の電流狭窄N6を形成するSl
 −In Pのような半絶縁性半導体は、完全な絶縁体
ではなく、通常は結晶中の深い電子(または正孔) ト
ラップが残留電子(または正孔)を捕獲することによっ
て絶縁性を維持しているため、ここにかかる電場が大き
くなりキャリアの注入が増大するにつれて急速に絶縁性
を失う特性を有している。特に、pin構造のように電
子と正札の両キャリアが同時に注入される場合には、t
l中でのキャリアの再結合が生ずるため、単一のキャリ
アだけの場合に比べて遥かに小さな電場でその絶縁性が
失われる。
However, in this conventional example, the current confinement N6 is formed by
-In Semi-insulating semiconductors such as P are not perfect insulators and usually maintain their insulating properties by capturing residual electrons (or holes) through deep electron (or hole) traps in the crystal. Therefore, as the electric field applied here increases and the injection of carriers increases, it rapidly loses its insulating properties. In particular, when both electrons and carriers of the genuine tag are injected at the same time as in the pin structure, t
Because recombination of carriers in l occurs, the insulating property is lost in a much smaller electric field than in the case of only a single carrier.

このこめ上記従来例は、入力電流が小さな際には良好な
特性を示すものの、入力電流が大きくなると急速にηが
低下して、大きな最大光出力が得られない問題がある。
Therefore, although the above-mentioned conventional example exhibits good characteristics when the input current is small, when the input current becomes large, η rapidly decreases, and there is a problem that a large maximum optical output cannot be obtained.

そこで本発明は、従来例の小リーク電流及び小入力容量
なる特性を確保しながら、最大光出力を向上させること
を目的とする。
Therefore, an object of the present invention is to improve the maximum optical output while ensuring the characteristics of the conventional example of small leakage current and small input capacitance.

〔課題を解決するための手段〕[Means to solve the problem]

上記目的は、活性層の上下面がそれぞれクラッド層に接
合してな゛るダブルヘテロ構造と、ダブルヘテロ構造の
両側を埋めた半絶縁性半導体の電流狭窄層とを有し、一
方のクラッド層と電流狭窄層との間に該クラッド層とは
反対導電型の半導体層が介在している本発明の半導体発
光装置によって達成される。
The above purpose is to have a double heterostructure in which the upper and lower surfaces of the active layer are respectively bonded to cladding layers, and a semi-insulating semiconductor current confinement layer that fills both sides of the double heterostructure, with one cladding layer This is achieved by the semiconductor light emitting device of the present invention in which a semiconductor layer of a conductivity type opposite to that of the cladding layer is interposed between the current confinement layer and the current confinement layer.

〔作 用〕[For production]

従来例は、電流狭窄層を半絶縁性半導体にしてリーク電
流及び入力容量を小さくしであるものの、この半絶縁性
半導体に電子と正孔の両キャリアが同時に注入されて最
大光出力が低く抑えられた。
In the conventional example, the current confinement layer is made of a semi-insulating semiconductor to reduce leakage current and input capacitance, but both electron and hole carriers are simultaneously injected into this semi-insulating semiconductor, keeping the maximum optical output low. It was done.

これに対して本発明の半導体発光装置は、電流狭窄層を
従来例と同様に半絶縁性半導体にしてリーク電流及び入
力容量を小さくし、加えて、上記介在させた半導体層を
設けである。
On the other hand, in the semiconductor light emitting device of the present invention, the current confinement layer is made of a semi-insulating semiconductor to reduce leakage current and input capacitance as in the conventional example, and in addition, the above-mentioned intervening semiconductor layer is provided.

この半導体層は、それが接するクラッド層からのキャリ
アを内部で再結合させて、そのキャリアが電流狭窄層で
ある半絶縁性半導体に注入されるのを阻止する。従って
、この半絶縁性半導体は、注入されるキャリアが単一に
なって、両キャリアが同時に注入される従来例の場合よ
り絶縁性を失う電場の大きさが大きくなる。
This semiconductor layer internally recombines carriers from the cladding layer with which it is in contact, and prevents the carriers from being injected into the semi-insulating semiconductor, which is the current confinement layer. Therefore, in this semi-insulating semiconductor, only a single carrier is injected, and the magnitude of the electric field at which insulation is lost is greater than in the conventional case where both carriers are injected simultaneously.

このことからこの半導体発光装置は、従来例の特徴であ
る小リーク電流及び小入力容量を維持して最大光出力が
向上する。
Therefore, this semiconductor light emitting device maintains the small leakage current and small input capacitance, which are the characteristics of the conventional example, and improves the maximum light output.

〔実施例〕〔Example〕

以下本発明による半導体発光装置の実施例について第1
図の要部側断面図を用いて説明する。全図を通じ同一符
号は同一対象物を示す。
The following is a first example of the semiconductor light emitting device according to the present invention.
This will be explained using a side sectional view of the main part in the figure. The same reference numerals indicate the same objects throughout the figures.

第1図に示す実施例は、第4図で述べた従来例に対して
、n−fPのクラフト層1とSl −In Pの電流狭
窄層6との間にp−lnP層7を介在させたものである
The embodiment shown in FIG. 1 differs from the conventional example shown in FIG. It is something that

即ち、クラッド層1はSnをl X IQ ” / c
d程度ドープしたn−1nPs活性層2はバンドギャッ
プ波長が例えば1.3μ−で厚さ約0.15μ■のアン
ドープInGaAs P %クラッド層3はZnを5 
XIO”/aJ程度ドープした厚さ約2μ−のp−1n
Psコンタク)N4はlnPに格子整合しZnをlXl
0’う/−程度ドープした厚さ約0.5μ曽のp” −
1nGaAs Pであり、これらの各層は、不図示のn
 −1nP基板上に順次成長された後、5iOzストラ
イプ膜などをマスクにしてメサエンチングされて、活性
層2の幅が1〜2μ髄程度のメサストライプ構造を形成
しており、活性層2とそれに接合するクラッド層l及び
クラッド層3がダブルヘテロ構造をなしている。
That is, the cladding layer 1 contains Sn at l×IQ”/c
The n-1nPs active layer 2 doped to about d is undoped InGaAs with a bandgap wavelength of, for example, 1.3μ and a thickness of about 0.15μ.
P-1n with a thickness of approximately 2 μ- doped to the extent of XIO”/aJ
Ps contact) N4 is lattice matched to lnP and Zn is lxl
0'U/- doped p"- with a thickness of about 0.5μ
1nGaAsP, and each of these layers has nGaAsP (not shown).
- After being sequentially grown on a 1nP substrate, mesa-etching is performed using a 5iOz stripe film as a mask to form a mesa-stripe structure with a width of about 1 to 2 μm, and the active layer 2 and the bonded to it are mesa-etched. The cladding layer l and the cladding layer 3 have a double heterostructure.

これに51− In Pを埋込み成長してメサストライ
プ構造の両側に電流狭窄層6を形成したものが従来例で
あるが、実施例は、その成長に先立ちZnなどのp型不
純物を表面から拡散して、クラッド層lの表面領域に不
純物濃度10’e〜10Is/ali程度で厚さ0.2
μ一程度のp−lnP層7を形成し、その後に電流狭窄
層6を従来例と同様にして形成しである。
In the conventional example, 51-InP is embedded and grown to form current confinement layers 6 on both sides of the mesa stripe structure, but in the embodiment, p-type impurities such as Zn are diffused from the surface prior to the growth. Then, the surface region of the cladding layer l is coated with an impurity concentration of about 10'e to 10Is/ali and a thickness of 0.2
A p-lnP layer 7 having a thickness of about 1 μ is formed, and then a current confinement layer 6 is formed in the same manner as in the conventional example.

Sr −In Pの電流狭窄層6は、従来例と同様にリ
ーク電流を小さくし、入力容量を小さくする。
The Sr-In P current confinement layer 6 reduces leakage current and input capacitance as in the conventional example.

p−lnP層7は、n−クラッド層lからの電子を内部
で再結合させて、その電子が電流狭窄層6に注入される
のを阻止する。従って、電流狭窄層6を形成するSI 
−夏nPに注入されるキャリアはp−クラッド層3から
の正孔のみとなり、電流狭窄層6が絶縁性を失うに至る
までの入力電流は、従来例の場合より温かに大きくなる
The p-lnP layer 7 internally recombines electrons from the n-cladding layer l and prevents the electrons from being injected into the current confinement layer 6. Therefore, the SI forming the current confinement layer 6
- Summer The carriers injected into the nP are only holes from the p- cladding layer 3, and the input current until the current confinement layer 6 loses its insulation properties becomes warmer and larger than in the conventional example.

かくしてこの半導体発光装置は、従来例の特徴である小
リーク電流及び小入力容量を維持して最大光出力が向上
する。
Thus, this semiconductor light emitting device maintains the small leakage current and small input capacitance, which are the characteristics of the conventional example, and improves the maximum light output.

本発明者の確認によれば、従来例では光出力が最大8m
Wで飽和していたのに対し、実施例では301m−以上
の光出力を得ることができ、然も、1th及びlは、両
者とも同じ<15−及び0.28a+W/gtAであっ
た。また、入力容量にも差が認められなかった。
According to the inventor's confirmation, in the conventional example, the maximum light output is 8m.
Whereas it was saturated with W, in the example it was possible to obtain a light output of 301 m- or more, and 1th and l were both <15- and 0.28a+W/gtA, which were the same. Furthermore, no difference was observed in input capacity.

上記実施例におけるp−lnP層7形成のp型不純物拡
散の代わりに、Sなどのn型不純物を拡散してp−クラ
フト層3の表面領域にn −lnP層を形成しても良い
、その場合には、p−クラッド層3からの正孔が電流狭
窄層6に注入されるのを阻止されて、実施例と同様な結
果が得られる。
Instead of p-type impurity diffusion to form the p-lnP layer 7 in the above embodiment, an n-lnP layer may be formed in the surface region of the p-craft layer 3 by diffusing an n-type impurity such as S. In this case, holes from the p-cladding layer 3 are prevented from being injected into the current confinement layer 6, and results similar to those of the embodiment are obtained.

また、実施例における各層の導電型は実施例と逆になっ
ても良い。
Further, the conductivity type of each layer in the embodiment may be reversed from that in the embodiment.

更に、実施例の半導体発光装置はlnP系の場合である
が、本発明の半導体発光装置は、その原理からしてln
P系に限定されるものではない。
Furthermore, although the semiconductor light emitting device of the embodiment is an lnP type, the semiconductor light emitting device of the present invention is based on the lnP type based on its principle.
It is not limited to P-type.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明の構成によれば、活性層の上
下面がそれぞれクラッド層に接合してなるダブルヘテロ
構造と、ダブルヘテロ構造の両側を埋めた半絶縁性半導
体の電流狭窄層とを有する半導体発光装置において、小
リーク電流及び小人力容量の特性を確保しながら最大光
出力を向上させることができて、1thが小さくηが大
きく且つ高速動作が可能で然も光出力の大きな半導体発
光装置の提供を可能にさせる効果がある。
As explained above, according to the configuration of the present invention, there is a double heterostructure in which the upper and lower surfaces of the active layer are respectively bonded to the cladding layer, and a current confinement layer made of a semi-insulating semiconductor that fills both sides of the double heterostructure. It is possible to improve the maximum optical output while ensuring the characteristics of small leakage current and small power capacity in a semiconductor light emitting device with a small 1th, large η, high speed operation, and high optical output. This has the effect of making it possible to provide equipment.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は実施例の要部側断面図、 第2図は従来の半導体発光装置の要部側断面図、第3図
は第2図発光装置のリーク電流を示す回路図、 第4図は従来例の要部側断面図、 である。 図において、 1はn−1nPクラッド層、 2はInGaAs P活性層、 3はp−rnPクラッド層、 4はp −1nGaAs Pコンタクト層、5はp−1
nP層5aとn −1nP層5bによる電流狭窄層、 6はSl −In P電流狭窄層、 7は本発明により介在させたp−1nP層、Dlは3の
部分が形成するダイオード、D2は5aと1が形成する
ダイオード、Rは5aによる抵抗、 である。 オ芝釆0手44不充光茨!のぞ祁4則灯面図第zn 第2DイしたiにイVのリーク電シ几E汀じすB回路図
第3m 従来例の字部側1面図 第4m
Fig. 1 is a side sectional view of the main part of the embodiment, Fig. 2 is a side sectional view of the main part of a conventional semiconductor light emitting device, Fig. 3 is a circuit diagram showing the leakage current of the light emitting device of Fig. 2, and Fig. 4 is This is a side sectional view of the main part of the conventional example. In the figure, 1 is an n-1nP cladding layer, 2 is an InGaAs P active layer, 3 is a p-rnP cladding layer, 4 is a p-1nGaAsP contact layer, and 5 is a p-1
A current confinement layer composed of an nP layer 5a and an n-1nP layer 5b, 6 is an Sl-InP current confinement layer, 7 is a p-1nP layer interposed according to the present invention, Dl is a diode formed by the part 3, and D2 is 5a and 1 form a diode, and R is the resistance due to 5a. Oshiba Kama 0 moves 44 unfilled thorns! 4-rule lamp diagram No. zn 2nd D I and I V leakage electric current B circuit diagram No. 3m Conventional example side 1 view No. 4m

Claims (1)

【特許請求の範囲】[Claims] 活性層の上下面がそれぞれクラッド層に接合してなるダ
ブルヘテロ構造と、ダブルヘテロ構造の両側を埋めた半
絶縁性半導体の電流狭窄層とを有し、一方のクラッド層
と電流狭窄層との間に該クラッド層とは反対導電型の半
導体層が介在していることを特徴とする半導体発光装置
It has a double heterostructure in which the upper and lower surfaces of the active layer are respectively bonded to cladding layers, and current confinement layers made of semi-insulating semiconductor that fill both sides of the double heterostructure, and one of the cladding layers and the current confinement layer. A semiconductor light emitting device characterized in that a semiconductor layer of a conductivity type opposite to that of the cladding layer is interposed therebetween.
JP4104188A 1988-02-24 1988-02-24 Semiconductor light emitting device Pending JPH01215081A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4104188A JPH01215081A (en) 1988-02-24 1988-02-24 Semiconductor light emitting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4104188A JPH01215081A (en) 1988-02-24 1988-02-24 Semiconductor light emitting device

Publications (1)

Publication Number Publication Date
JPH01215081A true JPH01215081A (en) 1989-08-29

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP4104188A Pending JPH01215081A (en) 1988-02-24 1988-02-24 Semiconductor light emitting device

Country Status (1)

Country Link
JP (1) JPH01215081A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016031970A (en) * 2014-07-28 2016-03-07 三菱電機株式会社 Optical semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5944887A (en) * 1982-09-07 1984-03-13 Fujitsu Ltd Semiconductor light emitting device
JPS62217690A (en) * 1986-03-19 1987-09-25 Fujitsu Ltd Semiconductor light-emitting device and manufacture thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5944887A (en) * 1982-09-07 1984-03-13 Fujitsu Ltd Semiconductor light emitting device
JPS62217690A (en) * 1986-03-19 1987-09-25 Fujitsu Ltd Semiconductor light-emitting device and manufacture thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016031970A (en) * 2014-07-28 2016-03-07 三菱電機株式会社 Optical semiconductor device

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