JPH0438880A - Semiconductor light emitting element - Google Patents
Semiconductor light emitting elementInfo
- Publication number
- JPH0438880A JPH0438880A JP2144304A JP14430490A JPH0438880A JP H0438880 A JPH0438880 A JP H0438880A JP 2144304 A JP2144304 A JP 2144304A JP 14430490 A JP14430490 A JP 14430490A JP H0438880 A JPH0438880 A JP H0438880A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- light emitting
- inp
- electrode
- emitting region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000005253 cladding Methods 0.000 claims description 6
- 238000002955 isolation Methods 0.000 abstract description 16
- 230000003287 optical effect Effects 0.000 abstract description 12
- 238000009792 diffusion process Methods 0.000 abstract description 4
- 238000002347 injection Methods 0.000 abstract description 4
- 239000007924 injection Substances 0.000 abstract description 4
- 239000002184 metal Substances 0.000 abstract description 2
- 229910052751 metal Inorganic materials 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 230000005855 radiation Effects 0.000 abstract 1
- 238000005019 vapor deposition process Methods 0.000 abstract 1
- 238000001947 vapour-phase growth Methods 0.000 abstract 1
- 230000017525 heat dissipation Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000007704 transition Effects 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- 101150110330 CRAT gene Proteins 0.000 description 2
- 229920006395 saturated elastomer Polymers 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Led Devices (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ドーム形高出力半導体発光素子に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a dome-shaped high-power semiconductor light emitting device.
従来例のドーム形発光素子として、アイ・イー・イー・
イー、トランザクションズ オン エレクトロン デバ
イシズ、イー デイ−２８、３７４（１９８１） （
ＩＥＥＥ、 Ｔｒａｎｓａｃｔｉｏｎｓ ｏｎ Ｅｌｅ
ｃｔｒｏｎＤｅｖｉｃｅｓ、 Ｖｏｌ ＥＤ−２８，３
７４（１９８１）に記載のような構造を挙げることがで
きる。As a conventional dome-shaped light emitting element, I.E.
E. Transactions on Electron Devices, E.D.-28, 374 (1981) (
IEEE,Transactions on ELE
ctronDevices, Vol ED-28,3
74 (1981).
上記従来例の素子は、ｎ電極側とＰ電極側がアイソレー
ション溝により電気的に分離された構造となっていた。The conventional element described above has a structure in which the n-electrode side and the p-electrode side are electrically separated by an isolation groove.
このアイソレーション溝の形成により発光領域への電流
注入をより効果的に行なうことができる。しかしながら
、この従来技術においては電流注入により生しる発光領
域の熱は、発光領域の電極部を通してのみサブマウント
側へ放熱される。したがって、光出力を増すために高電
流注入を行なうと、光出力−電流特性において光出力の
飽和が起こるという問題があった。By forming this isolation groove, current can be more effectively injected into the light emitting region. However, in this prior art, heat in the light emitting region generated by current injection is radiated toward the submount only through the electrode portion of the light emitting region. Therefore, when a high current is injected to increase the optical output, there is a problem in that the optical output saturates in the optical output-current characteristic.
本発明の目的は、発光領域の熱放散を良くし、高電流注
入領域における光出力の飽和を低減することにあり、更
に高出力の発光素子を提供することにある。An object of the present invention is to improve heat dissipation in a light emitting region, reduce saturation of light output in a high current injection region, and further provide a high output light emitting device.
上記目的を達成するために本発明においては、従来のア
イソレーション溝領域を高抵抗半導体層により形成した
。In order to achieve the above object, in the present invention, a conventional isolation trench region is formed of a high-resistance semiconductor layer.
従来の発光素子では、ｎ側領域とｎ側領域がアイソレー
ション溝により分離されているため発光領域の熱の放散
が悪く高電流側で光出力の飽和があった。本発明では、
上記アイソレーション溝部が高抵抗半導体層で形成され
ているため、電流注入はアイソレーション溝の場合と同
様発光領域のみに制限される。更に発光領域で発生した
熱は上記高抵抗半導体層を通して横方向へも放熱される
ため熱放散が良くなり、高電流注入時の光出力の飽和が
生じにくく、高出力動作が可能である。In a conventional light emitting element, since the n-side region and the n-side region are separated by an isolation groove, heat dissipation in the light emitting region is poor and optical output is saturated on the high current side. In the present invention,
Since the isolation groove portion is formed of a high-resistance semiconductor layer, current injection is limited to only the light emitting region as in the case of the isolation groove. Furthermore, the heat generated in the light emitting region is also dissipated in the lateral direction through the high-resistance semiconductor layer, so heat dissipation is improved, optical output is less likely to be saturated when high current is injected, and high output operation is possible.
〔実施例〕
以下、本発明の実施例を第１図〜第５図により説明する
。[Example] Hereinafter, an example of the present invention will be described with reference to FIGS. 1 to 5.
〔実施例１〕
第１図は、本発明を長波長発光ダイオードに適用した場
合の素子構造を示す。[Example 1] FIG. 1 shows an element structure when the present invention is applied to a long wavelength light emitting diode.
ｎ−ＩｎＰ基板１ （キャリア濃度１−５ Ｘ１０”ａ
ｍ−３）上に有機金属気相成長（ＭＯＣＶＤ）法により
ｎ−ＩｎＰバッファ層２ （３±１μｍ、キャリア濃度
Ｉ Ｘ １０１８Ｃ１−勺、 ｐ−１ｎＧａＡｓＰ活
性層３（１ｇ 〜１．３ ｐ ｍ Ｔ Ｏ−５±０．３
μｍ、キャリア濃度５Ｘ１０１７ｃｎ−３） 、ｐ−Ｉ
ｎＰクラッド層４（１±０．５μｍ、キャリア濃度１
ｘ１０”ａ＋＋−３） −ｎ−ＩｎＧａＡｓＰキャップ
層５ （１±０．５μｍ、キャリア濃度１〜４×１０’
７３）を順次積層する。次に、ｎ−ＩｎＰバッファ層２
に達する深さのアイソレーション溝１４の形成により２
ｏ〜５０μｍφの発光領域を形成する。n-InP substrate 1 (carrier concentration 1-5 x 10"a
n-InP buffer layer 2 (3±1 μm, carrier concentration I×1018C1−1), p-1nGaAsP active layer 3 (1 g to 1.3 p m T) by metal organic chemical vapor deposition (MOCVD) O-5±0.3
μm, carrier concentration 5×1017cn-3), p-I
nP cladding layer 4 (1±0.5 μm, carrier concentration 1
x10"a++-3) -n-InGaAsP cap layer 5 (1±0.5 μm, carrier concentration 1 to 4×10'
73) are sequentially stacked. Next, the n-InP buffer layer 2
By forming the isolation groove 14 with a depth of 2.
A light emitting region with a diameter of 0 to 50 μm is formed.
次に上記アイソレーション溝１４をＭＯＣＶＤ法により
ＴｉドープＩｎＰ高抵抗層６ （０，５μｍ）、および
ＦｅドープＩｎＰ高抵抗層７（１〜３μｍ）で平坦に埋
込む。ＴｉおよびＦｅを同時ドーピングしたＩｎＰ層１
層のみでもよい。その後、発光領域の中央部へｐ−Ｉｎ
Ｐクラッド層４に達するＺｎ拡散８を施こし、ｎ電極９
．ｎ電極１０を蒸着により形成する。更に、チップ化し
た後光出射面の一部あるいは全面を図のようにドーム状
に加工する。Next, the isolation trench 14 is filled flat with a Ti-doped InP high resistance layer 6 (0.5 μm) and an Fe-doped InP high resistance layer 7 (1 to 3 μm) by MOCVD. InP layer 1 co-doped with Ti and Fe
It may be just a layer. After that, p-In is applied to the center of the light emitting region.
Zn diffusion 8 is performed to reach the P cladding layer 4, and an n electrode 9 is formed.
．． The n-electrode 10 is formed by vapor deposition. Furthermore, after the chip is formed, a part or the entire surface of the light emitting surface is processed into a dome shape as shown in the figure.
第２図に以上の様にして作製した発光素子の光出力−電
流特性を示す。FIG. 2 shows the optical output-current characteristics of the light emitting device manufactured as described above.
従来の発光素子のようにｎおよびｐ電極間がアイソレー
ション溝によって電気的に分離されている場合は、熱放
散が悪いため高電流領域において光出力の飽和が生し易
く、高出力動作時に不利である。ところが、本発明のよ
うにアイソレーション溝内部が高抵抗半導体層によって
埋込まれている場合、発光領域において発生した熱の横
方向への放散が良いため高電流領域における光出力の飽
和が起こりにくく高出力動作が可能である。When the n and p electrodes are electrically separated by an isolation groove as in conventional light emitting devices, the optical output tends to saturate in the high current region due to poor heat dissipation, which is disadvantageous during high output operation. It is. However, when the inside of the isolation groove is filled with a high-resistance semiconductor layer as in the present invention, the heat generated in the light emitting region is well dissipated in the lateral direction, so saturation of the optical output in the high current region is less likely to occur. High output operation is possible.
更に本実施例のようにまず正孔をトラップする深い不純
物準位を形成する遷移元素（Ｔｉ）をドブした層で埋込
み１次に電子をトラップする深い不純物準位を形成する
遷移元素（Ｆｅ）をトープした層で埋込み、Ｆｅトープ
層がｐ導電形層と接触しない構造とするとリーク電流が
少なく発光効率の良い素子が得られる。また、Ｆｅの替
わりに同様に電子をトラップする不純物準位をつくるＭ
ｎやＣｏなど他の遷移元素を用いても良く、更にＴ１ド
ープ層の替わりにｎ導電形層（０，１〜０．５μｍ）を
用いても同様の効果が得られる。また、１種類の遷移元
素のみをドープした高抵抗層１層で平坦に埋込んでも良
い。Furthermore, as in this example, first, a layer doped with a transition element (Ti) that forms a deep impurity level that traps holes is buried, and the first layer is doped with a transition element (Fe) that forms a deep impurity level that traps electrons. If the structure is such that the Fe-topped layer does not come into contact with the p conductivity type layer, an element with low leakage current and high luminous efficiency can be obtained. Also, instead of Fe, M which creates an impurity level that similarly traps electrons is used.
Other transition elements such as n and Co may be used, and the same effect can be obtained even if an n conductivity type layer (0.1 to 0.5 μm) is used instead of the T1 doped layer. Alternatively, a single high-resistance layer doped with only one type of transition element may be buried flatly.
〔実施例２〕
第３図に５本発明の他の実施例の素子構造を示した。実
施例１と同様にＭＯＣＶＤ法により作製した。まず、ｎ
−ＩｎＰ基板上にＰ−ＩｎＰバッファ層２’ （１０
〜３０μｍ、キャリア濃度１〜２ Ｘ １０”ａｎ−’
）を成長し、その後ｐ −ＩｎＧａＡｓＰ活性層３（λ
ｇ＝１．３μｍ、０．５±０．３μｍ。[Embodiment 2] FIG. 3 shows an element structure of another embodiment of the present invention. It was produced by the MOCVD method in the same manner as in Example 1. First, n
- P-InP buffer layer 2' (10
~30μm, carrier concentration 1~2 x 10"an-'
), and then p-InGaAsP active layer 3 (λ
g=1.3 μm, 0.5±0.3 μm.
キャリア濃度５Ｘ１０１７ａ＋＋−３）、ｎ−Ｉ ｎＰ
クラッド層４′ （１±０．５μｍ 、キャリア濃度１
×１０”ａ＋＋−３） 、 ｎ −ＩｎＧａＡｓＰ
キャップ層５ （λ１＝１．５μｍ、１±０．５μｍ、
キャリア濃度１〜４ Ｘ Ｉ Ｑ”ａｓ−”）を順次積
層する。次に発光領域を２０〜５０μｍφにｐ−ＩｎＰ
バッファ層に達する深さにメサエッチして形成し、発光
領域の側部をＦｅおよびＴ１ドープ高抵抗層７′で平坦
に。Carrier concentration 5X1017a++-3), n-I nP
Cladding layer 4' (1±0.5 μm, carrier concentration 1
×10”a++-3), n-InGaAsP
Cap layer 5 (λ1=1.5 μm, 1±0.5 μm,
Carrier concentrations of 1 to 4XIQ"as-") are sequentially stacked. Next, the light emitting region is made of p-InP with a diameter of 20 to 50 μm.
It is formed by mesa etching to a depth that reaches the buffer layer, and the sides of the light emitting region are flattened with Fe and T1 doped high resistance layers 7'.
かつ選択的に埋込む。この埋込み層は実施例］−と同様
に多層埋込み構造としても良い。次に高抵抗埋込み層の
一部にｐ−ＩｎＰバッファ層に達する深さのＺｎ拡散８
を施こし、ｎ電極９＋Ｐ電極１０を形成する。更に実施
例１と同様にチップ化し光出射面をドーム状に加工する
。and selectively embed. This buried layer may have a multilayer buried structure similar to the embodiment]-. Next, Zn is diffused into a part of the high-resistance buried layer to a depth that reaches the p-InP buffer layer 8.
The n-electrode 9 and the p-electrode 10 are formed. Furthermore, in the same manner as in Example 1, it is made into a chip and the light emitting surface is processed into a dome shape.
本実施例においても、実施例１と同様高電流領域におい
て光出力飽和の少ない高出力発光ダイオードが得られた
。In this example, as in Example 1, a high-output light emitting diode with little optical output saturation in the high current region was obtained.
〔実施例３〕
第４図は、実施例２の発光ダイオードに半導体多層反射
膜を適用し、更に高出力化を図った素子の断面構造であ
る。素子製作については、実施例２とほぼ同様でありｎ
−ＩｎＰクラット層４′とｎ−ＩｎＧａＡｓＰキャップ
層５の間に半導体多層反射膜１１をエピタキシャル成長
するのみであるので、詳細は省略する。[Example 3] FIG. 4 is a cross-sectional structure of a device in which a semiconductor multilayer reflective film is applied to the light emitting diode of Example 2 to further increase the output. The device fabrication is almost the same as in Example 2.
Since only the semiconductor multilayer reflective film 11 is epitaxially grown between the -InP crat layer 4' and the n-InGaAsP cap layer 5, the details will be omitted.
半導体多層反射膜１１の構造は、高屈折率層としてｎ
−ＩｎＧｓＡｓＰ （λｇ”１．１５μｍ、９７１．３
Ａキャリア濃度Ｉ Ｘ １０１５ｃｍ’−３） 、低屈
折率層としてｎ−ＩｎＰ （１０１２，６人 、キャリ
ア濃度ＩＸ １０１８ａａ−３）を用い１６ペアとした
。反射膜のトータル膜厚は３．１７μｍである。The structure of the semiconductor multilayer reflective film 11 includes n as a high refractive index layer.
-InGsAsP (λg”1.15 μm, 971.3
A carrier concentration IX 1015 cm'-3) and n-InP (1012,6, carrier concentration IX 1018 aa-3) were used as the low refractive index layer to form 16 pairs. The total thickness of the reflective film is 3.17 μm.
本実施例では、多層反射膜１１を採用したため、実施例
１，２の発光ダイオードに比へ、更に高出力の素子が得
られ、第２図に示した高抵抗埋込の場合に比へて３０％
程度光出力が向上した。また。In this example, since the multilayer reflective film 11 is adopted, a device with even higher output is obtained compared to the light emitting diodes of Examples 1 and 2, and compared to the case of high-resistance embedding shown in FIG. 30%
The light output has been improved to a certain degree. Also.
この素子においても、ＦｅおよびＴｉドープＩｎＰ層埋
込みの効果により高電流領域における光出力の飽和は第
２図の高抵抗埋込の場合とほぼ同程度に低減された。In this device as well, saturation of optical output in the high current region was reduced to approximately the same level as in the case of high resistance embedding shown in FIG. 2 due to the effect of embedding the Fe- and Ti-doped InP layers.
〔実施例４〕
第５図は、本発明を面発光型レーザに適用した場合の実
施例である。ｎ −丁ｎ Ｐ基板１上にＭＯＣＶＤ法に
よりｐ−ＩｎＰバッファ層２’ （１０〜３０μｍ）
を成長し、次にｐ −ＩｎＧａＡｓＰ （λ８＝１．
１５μｍ、９７１．３人、キャリア濃度０．５−ＩＸＬ
Ｏ”ａｏ−一とｐ−ＩｎＰ（１０１２，６人、匁ヤｌア
濃度０．５〜ｌ Ｘ １０１９ａｎ−’）を交互に１６
ヘア積層した多層反射膜１２を成長する。更に、ｐ −
Ｉ ｎ Ｐクララト層１３（−５μｍ、キャリア濃度ｌ
Ｘ１０１９ｃｎ−’） 、 ｐ−４ｎＧａＡｓＰ活性層
３（λｇ”１．３μｍ、２〜５μｍ、キャリア濃度０．
５＝ＩＸｌ○１″Ｑｌｌ−’）、ｎ−ＩｎＰクラット層
４′ （〜５μｍ、キャリア濃度Ｉ Ｘ １０”■−３
）を順次積層し、つづいて上記反射膜と同構造の多層反
射膜１１およびｎ−ＩｎＰキャップ層５（λｇ” ］、
、 １５ ｐ ｍ、１±０．５ μｍ、キャリア濃度
１〜４Ｘ１０”８】〜１）を積層する。その後、発光領
域が１０〜２０μｍφになるよう反射膜１２またＬ：！
ｐ−ＩｎＰバッファ層に達する深さのアイツレジョン溝
１４を形成する。次にそのアイソレーション溝をＦｅト
ープＩｎＰ７ （または、Ｆｅおよび１゛］トープＩｎ
Ｐ７’）で平坦に埋込み、図に示すようなＺｎ拡散８を
施こす。更に、ｎ電極９ 、 ｎ電極１０を形成し、光
出射面をドーム状に加工して素子は完了する。[Embodiment 4] FIG. 5 shows an embodiment in which the present invention is applied to a surface emitting laser. A p-InP buffer layer 2' (10 to 30 μm) is formed on a p-substrate 1 by MOCVD.
and then p-InGaAsP (λ8=1.
15 μm, 971.3 people, carrier concentration 0.5-IXL
O"ao-1 and p-InP (1012, 6 people, Momoyara concentration 0.5~l x 1019an-') were alternately 16
A multilayer reflective film 12 formed by laminating hair is grown. Furthermore, p −
I n P clarato layer 13 (-5 μm, carrier concentration l
X1019cn-'), p-4nGaAsP active layer 3 (λg" 1.3 μm, 2 to 5 μm, carrier concentration 0.
5=IXl○1"Qll-'), n-InP crat layer 4' (~5 μm, carrier concentration IX10"■-3
) are sequentially laminated, followed by a multilayer reflective film 11 having the same structure as the above reflective film and an n-InP cap layer 5 (λg''),
, 15 pm, 1±0.5 μm, carrier concentration 1 to 4×10”8] to 1) are laminated. Then, the reflective film 12 and L:! are layered so that the light emitting area becomes 10 to 20 μmφ.
An eye region trench 14 is formed with a depth that reaches the p-InP buffer layer. Next, insert the isolation groove into Fe-topped InP7 (or Fe and 1゛]-topped InP7
P7') is buried flatly, and Zn diffusion 8 is performed as shown in the figure. Further, an n-electrode 9 and an n-electrode 10 are formed, and the light emitting surface is processed into a dome shape to complete the device.
この面発光レーザにおいては、発振波長１．３μｍしき
い値電流２０〜３０ｍＡの素子が得られ、熱放散が改善
されたため光出力−電流特性の直線性良い素子が得られ
た。In this surface emitting laser, a device with an oscillation wavelength of 1.3 μm and a threshold current of 20 to 30 mA was obtained, and due to improved heat dissipation, a device with good linearity of optical output-current characteristics was obtained.
以上の実施例ではＩｎＰ基扱としてｎ導電形のウェハを
用いたが、ｐ形１ｎＰ基板を用いても良く、その場合実
施例２，３．４においてはｐ −ＩｎＰバッファ層２′
が薄くても良い（〜５μｍ）という利点がある。In the above embodiments, an n-conductivity type wafer was used as the InP base, but a p-type 1nP substrate may also be used. In that case, in Examples 2 and 3.4, the p-InP buffer layer 2'
It has the advantage that it can be thin (~5 μm).
また１本発明はＧ ａ Ａ ｓ系の発光素子についても
適用可能であり、その場合高抵抗層のドーパントとして
はＣｒ、Ｖ、Ｏなどが良く用いられる。The present invention is also applicable to GaAs-based light emitting elements, in which case Cr, V, O, etc. are often used as dopants for the high resistance layer.
本発明によれば、ｎ電極とｎ電極を高抵抗層により電気
的にアイソレーションしているため、発光領域において
発生した熱の横方向への放散が良くなるため、高電流領
域における光出力の飽和が低減され、高出力動作が可能
になる。According to the present invention, since the n-electrode and the n-electrode are electrically isolated by the high-resistance layer, the heat generated in the light emitting region is better dissipated in the lateral direction, so that the light output in the high current region is reduced. Saturation is reduced and high power operation is possible.
第１図は本発明の一実施例のアイソレーション溝のみを
高抵抗層で埋込んだ発光素子の断面図、第２図は第１図
の発光素子の光出力−電流特性図、第３図は発光領域以
外を全て高抵抗層で埋込んだ実施例になる発光素子の断
面図、第４図は多層反射膜を具備した実施例になる発光
素子の断面図、第５図は本発明を面発光レーザに適用し
た実施例の素子断面図である。
１・・ＩｎＰ基板、２，２′・・バッファ層、３・・活
性層、４・・・ｐクラッド層、Ｓ・・・キャップ層、６
・・高抵抗層、７，７′・・・高抵抗層、８・・・Ｚｎ
拡散、９・ｎ電極、１０・・Ｐ電極、１１・・・多層反
射膜。
１２・・多層反射膜、１３・・・ｎクラッド層、１４・
・アイソレーション溝。FIG. 1 is a cross-sectional view of a light emitting device according to an embodiment of the present invention in which only the isolation groove is filled with a high resistance layer, FIG. 2 is a light output-current characteristic diagram of the light emitting device shown in FIG. 1, and FIG. 4 is a sectional view of a light emitting device according to an embodiment in which the entire area other than the light emitting region is filled with a high resistance layer, FIG. 4 is a sectional view of a light emitting device according to an embodiment equipped with a multilayer reflective film, and FIG. FIG. 2 is a cross-sectional view of an element of an example applied to a surface emitting laser. 1...InP substrate, 2,2'...buffer layer, 3...active layer, 4...p cladding layer, S...cap layer, 6
...High resistance layer, 7,7'...High resistance layer, 8...Zn
Diffusion, 9.N electrode, 10..P electrode, 11..multilayer reflective film. 12...Multilayer reflective film, 13...n cladding layer, 14...
・Isolation groove.
Claims (1)
含む多層構造を有し、かつｎ電極とｐ電極が光出射面に
対して反対側に有り、光出射面の少なくとも一部がドー
ム状になっている発光素子において、該電極間が高抵抗
半導体層により電気的にアイソレーションされているこ
とを特徴とする半導体発光素子。 ２、高抵抗半導体層が、Ｆｅ、Ｃｏ、Ｔｉ、Ｍｎ、Ｃｒ
、Ｖ、Ｏのうち少なくとも１つを添加した少なくとも１
つの半導体層で形成されていることを特徴とする請求項
１記載の半導体発光素子。[Claims] 1. A semiconductor substrate has a multilayer structure including at least an active layer and a cladding layer, and an n-electrode and a p-electrode are located on the opposite side of the light-emitting surface, and at least one of the light-emitting surfaces 1. A semiconductor light emitting device, wherein a portion of the light emitting device has a dome shape, and the electrodes are electrically isolated by a high resistance semiconductor layer. 2. High resistance semiconductor layer is made of Fe, Co, Ti, Mn, Cr
, V, and O.
2. The semiconductor light emitting device according to claim 1, wherein the semiconductor light emitting device is formed of two semiconductor layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2144304A JPH0438880A (en) | 1990-06-04 | 1990-06-04 | Semiconductor light emitting element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2144304A JPH0438880A (en) | 1990-06-04 | 1990-06-04 | Semiconductor light emitting element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0438880A true JPH0438880A (en) | 1992-02-10 |
Family
ID=15358962
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2144304A Pending JPH0438880A (en) | 1990-06-04 | 1990-06-04 | Semiconductor light emitting element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0438880A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1995002910A1 (en) * | 1993-07-12 | 1995-01-26 | British Telecommunications Public Limited Company | Electrical barrier structure for semiconductor device |
| CN103730431A (en) * | 2014-01-07 | 2014-04-16 | 宝钢金属有限公司 | High-power array light-emitting diode (LED) chip surface radiating structure and manufacturing method |
-
1990
- 1990-06-04 JP JP2144304A patent/JPH0438880A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1995002910A1 (en) * | 1993-07-12 | 1995-01-26 | British Telecommunications Public Limited Company | Electrical barrier structure for semiconductor device |
| EP0639875A1 (en) * | 1993-07-12 | 1995-02-22 | BRITISH TELECOMMUNICATIONS public limited company | Electrical barrier structure for semiconductor device |
| US5838025A (en) * | 1993-07-12 | 1998-11-17 | British Telecommunications Public Limited Company | Electrical barrier structure for semiconductor device doped with chromium and/or titanium |
| CN103730431A (en) * | 2014-01-07 | 2014-04-16 | 宝钢金属有限公司 | High-power array light-emitting diode (LED) chip surface radiating structure and manufacturing method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6175582B1 (en) | Semiconductor laser device | |
| US6584130B2 (en) | Multiple semiconductor laser structure with narrow wavelength distribution | |
| JPH0243351B2 (en) | ||
| JPS6239839B2 (en) | ||
| JPH0438880A (en) | Semiconductor light emitting element | |
| JPS60101989A (en) | Semiconductor laser and manufacture thereof | |
| JP2927661B2 (en) | Super luminescent diode element and method of manufacturing the same | |
| JPH01155678A (en) | Semiconductor light emitting device | |
| KR100363240B1 (en) | Semiconductor laser diode and its manufacturing method | |
| JPS59125684A (en) | Buried type semiconductor laser | |
| JPH0436598B2 (en) | ||
| JP3144821B2 (en) | Semiconductor laser device | |
| JPS6257271A (en) | Semiconductor laser device | |
| JPS6244440B2 (en) | ||
| KR100565049B1 (en) | Vertical cavity surface emitting laser | |
| JP2804533B2 (en) | Manufacturing method of semiconductor laser | |
| JPH0513872A (en) | Hetero junction type semiconductor laser | |
| JPH03203282A (en) | Semiconductor laser diode | |
| JPH06334260A (en) | Semiconductor laser element and its manufacture | |
| JP2855887B2 (en) | Semiconductor laser and method of manufacturing the same | |
| JPS62102583A (en) | Buried structure semiconductor laser | |
| JPS622718B2 (en) | ||
| JPH01215081A (en) | Semiconductor light emitting device | |
| JPS5884485A (en) | Buried hetero-structure semiconductor laser | |
| JPS62259490A (en) | Buried hetero structure semiconductor laser |