JPH09298334A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

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Publication number
JPH09298334A
JPH09298334A JP8113387A JP11338796A JPH09298334A JP H09298334 A JPH09298334 A JP H09298334A JP 8113387 A JP8113387 A JP 8113387A JP 11338796 A JP11338796 A JP 11338796A JP H09298334 A JPH09298334 A JP H09298334A
Authority
JP
Japan
Prior art keywords
layer
type
grown
semiconductor
inp
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP8113387A
Other languages
Japanese (ja)
Inventor
Toru Haga
芳賀  徹
Toshihiro Kono
敏弘 河野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8113387A priority Critical patent/JPH09298334A/en
Publication of JPH09298334A publication Critical patent/JPH09298334A/en
Withdrawn legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To reduce the threshold of an buried hetero-junction laser by burying and growing a first conductivity type semiconductor layer and second conductivity type semiconductor layer, diffusing a dopant into the surface of this semiconductor layer to change it to a first conductivity type one and burying and growing a first and second conductivity semiconductor layers. SOLUTION: A p-type clad layer 2 is grown on a p-type substrate 1 and an undoped MQW active layer 3 an n-type clad layer 4 are grown. A SiO2 film 15 is deposited. After a photolithographic step, a mesa stripe having smooth side faces is formed by etching while using this film 15 as a mask. Its side faces are filled with a Zn-doped p-type InP layer 5 and Si-doped n-type InP layer 6 to form a p-type Zn diffused layer 7 on the surface of the InP layer 6. A Zn-doped p-type InP layer 8 and Si-doped n-type InP layer 9 are grown and the mesa stripe is buried. The SiO2 film is removed and n-type InP layer 10 and n-type InGaAs cap layer 11 are buried flat.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は埋込ヘテロ構造半導
体レーザに関する。
TECHNICAL FIELD The present invention relates to a buried heterostructure semiconductor laser.

【0002】[0002]

【従来の技術】半導体レーザの低閾値化を図るには、活
性領域以外を流れるリーク電流の低減が必須である。従
来、埋込ヘテロ(BH;Buried Heterostructure)構造
レーザでは、電流ブロック層としてp−n接合や高抵抗
半導体層(Fe及びTiドープ等)が用いられており、
p基板を用いたBHレーザの例は、エレクトロニクス・
レターズ 28巻 ナンバー19 1992年 184
4頁(Electronics Letters Vol.28 No.19 1992 p.18
44)に記載のように、有機金属気相成長(MOCVD;
Metalorganic Chemical Vapor Deposition)法によ
るp−n接合埋込型のBHレーザがある。
2. Description of the Related Art In order to reduce the threshold of a semiconductor laser, it is essential to reduce the leak current flowing in regions other than the active region. Conventionally, in a buried hetero (BH; Burried Heterostructure) laser, a pn junction or a high resistance semiconductor layer (Fe and Ti doping, etc.) is used as a current blocking layer,
An example of a BH laser using ap substrate is
Letters Volume 28 Number 19 1992 184
Page 4 (Electronics Letters Vol.28 No.19 1992 p.18
44), metal organic chemical vapor deposition (MOCVD;
There is a pn junction buried type BH laser by the Metalorganic Chemical Vapor Deposition method.

【0003】[0003]

【発明が解決しようとする課題】従来技術でp−n接合
埋込によるBHレーザを作製すると、図2に示すように
n型InP埋込層6とn型InP層9,10がつながり
易く(n−n接続ができ易く)、電流がこのn−n接続
を通じて流れるため充分な低閾値化ができない。
When a BH laser with a pn junction is buried in the prior art, the n-type InP buried layer 6 and the n-type InP layers 9 and 10 are easily connected as shown in FIG. nn connection is easily formed), and a current cannot be reduced sufficiently because the current flows through the nn connection.

【0004】ここで、図において、1はp−InP基
板、2はp−InPクラッド層、3はMQW活性層、4
はn−InPクラッド層、5はp−InP層、8はp−
InP層、11はn−InGaAsPキャップ層、12
はSiO2 膜、13はn電極、14はp電極である。
In the figure, 1 is a p-InP substrate, 2 is a p-InP clad layer, 3 is an MQW active layer, 4
Is an n-InP clad layer, 5 is a p-InP layer, and 8 is a p-
InP layer, 11 is n-InGaAsP cap layer, 12
Is an SiO 2 film, 13 is an n-electrode, and 14 is a p-electrode.

【0005】本発明の目的は、このようなn−n接続の
無い低リーク電流埋込構造を達成することにより、BH
レーザの低閾値化を図ることにある。
An object of the present invention is to achieve a low leakage current buried structure without such an nn connection, thereby achieving BH.
The object is to reduce the threshold of the laser.

【0006】[0006]

【課題を解決するための手段】上記目的を達成するため
の手段を、図1により説明する。変曲点の無い滑らかな
側面形状を持つメサストライプを形成し、その埋込成長
で最初にZnドープp型InP層5を、次にSiドープ
n型InP層6(n−InPブロック層)を連続して成
長する。次に同じ成長装置(MOCVD装置)内でZn
を拡散し、表面層をp型のInP層7とする。すると、
もしブロック層の成長フロントがメサ最上部に達してし
まった場合でも、表面層はp型のInP層7となる。よ
って、埋め込んだブロック層6は、後にこの上方に成長
するn型InP層9又は10とは完全に分離され、周囲
を移動度の小さいp型InP層5,7および8で囲まれ
た構造となる。
Means for achieving the above object will be described with reference to FIG. A mesa stripe having a smooth side surface shape without an inflection point is formed, and by the buried growth thereof, first the Zn-doped p-type InP layer 5 and then the Si-doped n-type InP layer 6 (n-InP block layer) are formed. Grow continuously. Next, in the same growth apparatus (MOCVD apparatus), Zn
Are diffused to form the p-type InP layer 7 as the surface layer. Then
Even if the growth front of the block layer reaches the top of the mesa, the surface layer becomes the p-type InP layer 7. Therefore, the buried block layer 6 is completely separated from the n-type InP layer 9 or 10 which is to be grown thereabove, and is surrounded by the p-type InP layers 5, 7 and 8 having low mobility. Become.

【0007】このような構造では、メサストライプの活
性領域以外を流れるリーク電流は効果的に抑止され、低
閾値半導体レーザが実現できる。
With such a structure, a leak current flowing in a region other than the active region of the mesa stripe is effectively suppressed, and a low threshold semiconductor laser can be realized.

【0008】[0008]

【発明の実施の形態】本発明をInGaAsP系BHレ
ーザに適用した場合について、図1,図3により説明す
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A case where the present invention is applied to an InGaAsP-based BH laser will be described with reference to FIGS.

【0009】有機金属気相成長(MOCVD)法によ
り、p−InP基板1(キャリア濃度4〜6×1018cm~
2)にp−InPクラッド層2(キャリア濃度〜1×10
18cm~2,厚さ〜2μm)を成長した後アンドープInG
aAsP/InGaAs MQW活性層3(波長1.3
μm,厚さ〜0.2μm),n−InPクラッド層4
(キャリア濃度〜2×1018cm~2,厚さ〜1μm)を成
長する。この時活性層3はアンド−プInGaAsPバ
ルク活性層でも良く、MQW構造に限定されない。
By the metal organic chemical vapor deposition (MOCVD) method, the p-InP substrate 1 (carrier concentration 4 to 6 × 10 18 cm
2 ) the p-InP clad layer 2 (carrier concentration ~ 1 x 10
18 cm ~ 2 , thickness ~ 2 μm) and then undoped InG
aAsP / InGaAs MQW active layer 3 (wavelength 1.3
μm, thickness ~ 0.2 μm), n-InP clad layer 4
(Carrier concentration of 2 × 10 18 cm 2 and thickness of 1 μm) is grown. At this time, the active layer 3 may be an AND-type InGaAsP bulk active layer and is not limited to the MQW structure.

【0010】その後、CVD法によりSiO2 膜15を
被着しホトリソ工程を経た後、SiO2 膜15をマスク
としてウェットエッチングにより図3に示されるような
変曲点の無い滑らかな側面を有するメサストライプを形
成する。メサストライプはSiO2膜15下部が側面か
らエッチングされ、SiO2膜15がオーバーハング状
になるようにする。また活性層幅は1〜2μm,メサ深
さは2.5〜4μmである。
After that, a SiO 2 film 15 is deposited by the CVD method, and a photolithography process is performed. Then, by wet etching using the SiO 2 film 15 as a mask, a mesa having a smooth side surface having no inflection point as shown in FIG. 3 is formed. Forming stripes. The mesa stripe is formed such that the lower part of the SiO 2 film 15 is etched from the side surface so that the SiO 2 film 15 has an overhang shape. The active layer width is 1 to 2 μm and the mesa depth is 2.5 to 4 μm.

【0011】次にMOCVD法により、SiO2 膜を被
着したままメサストライプの側面を、Znドープp−I
nP層5(キャリア濃度〜1×1018cm~2,厚さ0.5
〜1μm),Siドープn−InP層6(キャリア濃度
〜2×1018cm~2,厚さ0.5〜1μm)で埋め込む。
Next, by MOCVD, the side surface of the mesa stripe is Zn-doped p-I while the SiO 2 film is deposited.
nP layer 5 (carrier concentration ~1 × 10 18 cm ~ 2, a thickness of 0.5
˜1 μm), and Si-doped n-InP layer 6 (carrier concentration ˜2 × 10 18 cm- 2 , thickness 0.5-1 μm).

【0012】その後成長室にジメチルZn(DMZn)
とホスフィン(PH3 )を導入し、n−InP層6の表
面にp型のZn拡散層7を形成する。この時拡散は、MO
CVD装置内で埋め込み成長と連続して行うため、試料を
空気にさらし、汚染されることはない。ここではZnの
拡散源としてDMZnを用いたが、代わりにジエチルZ
n(DEZn)を用いても良い。
Thereafter, dimethyl Zn (DMZn) was placed in the growth chamber.
And phosphine (PH 3 ) are introduced to form a p-type Zn diffusion layer 7 on the surface of the n-InP layer 6. At this time, the diffusion is MO
The sample is exposed to air and is not contaminated because it is performed continuously with embedded growth in the CVD device. Although DMZn was used as the Zn diffusion source here, diethyl Z
n (DEZn) may be used.

【0013】次にZnドープp−InP層8(キャリア
濃度〜2×1018cm~2,厚さ1〜3μm),Siドープ
n−InP層9(キャリア濃度〜2×1018cm~2,厚さ
〜0.5μm)を成長し、メサストライプを埋め込んだ。
n−InP層9はp−n接合と再成長界面を分離するた
めに設けたもので、本発明では特に挿入を限定されるも
のでは無い。
Next, the Zn-doped p-InP layer 8 (carrier concentration: 2 × 10 18 cm- 2 , thickness: 1-3 μm), the Si-doped n-InP layer 9 (carrier concentration: 2 × 10 18 cm- 2 , The thickness was grown to 0.5 μm) and the mesa stripe was embedded.
The n-InP layer 9 is provided to separate the pn junction from the regrowth interface, and the insertion is not particularly limited in the present invention.

【0014】次に、SiO2 膜を除去した後n−InP
層10(キャリア濃度〜2×1018cm~2,厚さ〜2μ
m),n−InGaAsPキャップ層11(キャリア濃
度>5×1018cm~2,厚さ〜2μm)で平坦に埋め込ん
だ。
Next, after removing the SiO 2 film, the n-InP
Layer 10 (Carrier concentration ~ 2 × 10 18 cm ~ 2 , Thickness ~ 2μ
m), n-InGaAsP cap layer 11 (carrier concentration> 5 × 10 18 cm ~ 2 , but flat buried in thick ~2μm).

【0015】以上のようにして埋め込んだ構造では、も
しn−InP層6の成長フロントがメサ最上部に達して
しまった場合でも、その表面層はZnを拡散したp型の
InP層7となる。そのため埋め込んだn型InP層6
(n−InP電流ブロック層)は、n型InP層9及び
10とは完全に分離され、周囲を移動度の小さいp型I
nP層5,7及び8で囲まれた、理想的なブロック層構
造となる。そしてこのような構造では、メサストライプ
の活性領域以外を流れるリーク電流は効果的に抑止さ
れ、低閾値半導体レーザが実現できる。
In the structure buried as described above, even if the growth front of the n-InP layer 6 reaches the top of the mesa, its surface layer becomes the p-type InP layer 7 in which Zn is diffused. . Therefore, the embedded n-type InP layer 6
The (n-InP current blocking layer) is completely separated from the n-type InP layers 9 and 10 and has a low mobility around the p-type I layer.
An ideal block layer structure surrounded by the nP layers 5, 7 and 8 is obtained. In such a structure, a leak current flowing in areas other than the active region of the mesa stripe is effectively suppressed, and a low-threshold semiconductor laser can be realized.

【0016】その後SiO2 膜12で電流狭窄を行った
後n電極13を形成、更に基板側を研磨してトータル膜
厚100μm程度にした後p電極14を蒸着により形成
し、素子化を行った。
After that, the SiO 2 film 12 was used to confine the current, and then the n-electrode 13 was formed. Further, the substrate side was polished to a total film thickness of about 100 μm, and then the p-electrode 14 was formed by vapor deposition to form a device. .

【0017】本実施例によるBHレーザでは、発振波長
1.3μm,閾電流値10〜12mA,スロープ効率0.3
mW/mA の素子が高歩留りで得られ、低リーク電流
で且つ低閾値の半導体レーザが実現できた。
In the BH laser according to this embodiment, the oscillation wavelength is 1.3 μm, the threshold current value is 10 to 12 mA, and the slope efficiency is 0.3.
An element of mW / mA 2 was obtained with a high yield, and a semiconductor laser with a low leak current and a low threshold could be realized.

【0018】本実施例では半導体レーザへの適用につい
て説明したが、本発明は半導体レーザに限らず電流狭窄
を行う必要のある他のデバイスについても適用可能であ
る。
In this embodiment, the application to the semiconductor laser has been described. However, the present invention is not limited to the semiconductor laser and can be applied to other devices that require current confinement.

【0019】[0019]

【発明の効果】本発明のように、変曲点の無い滑らかな
側面形状を持つメサストライプをp−n接合により埋め
込む構造で、n−InP電流ブロック層の成長後にZn
を拡散すれば、ブロック層の表面はp型のInP層とな
る。そのため、ブロック層の成長フロントがメサ最上部
に達してしまった場合でもn−n接続が排除でき、リー
ク電流が小さく、活性領域へ効率的に電流注入を行う低
閾値の素子が得られる。
As in the present invention, a mesa stripe having a smooth side surface without an inflection point is embedded by a pn junction, and Zn is grown after the growth of the n-InP current blocking layer.
Is diffused, the surface of the block layer becomes a p-type InP layer. Therefore, even if the growth front of the block layer reaches the top of the mesa, the nn connection can be eliminated, the leak current is small, and a low threshold element for efficiently injecting current into the active region can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示す半導体レーザの断面
図。
FIG. 1 is a sectional view of a semiconductor laser showing one embodiment of the present invention.

【図2】従来例を示す半導体レーザの断面図。FIG. 2 is a sectional view of a semiconductor laser showing a conventional example.

【図3】本発明の一実施例の要部の説明図。FIG. 3 is an explanatory diagram of a main part of one embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1…p−InP基板、2…p−InPクラッド層、3…
MQW活性層、4…n−InPクラッド層、5…p−I
nP層、6…n−InP層、7…Zn拡散p−InP
層、8…p−InP層、9…n−InP層、10…n−
InP層、11…n−InGaAsPキャップ層、12
…SiO2 膜、13…n電極、14…p電極、15…S
iO2 膜。
1 ... p-InP substrate, 2 ... p-InP cladding layer, 3 ...
MQW active layer, 4 ... n-InP cladding layer, 5 ... pI
nP layer, 6 ... n-InP layer, 7 ... Zn diffusion p-InP
Layer, 8 ... p-InP layer, 9 ... n-InP layer, 10 ... n-
InP layer, 11... N-InGaAsP cap layer, 12
... SiO 2 film, 13 ... n electrode, 14 ... p electrode, 15 ... S
iO 2 film.

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】半導体基板上に活性層を含む多層構造を形
成し、上記多層構造を、側面が変曲点の無い滑らかな曲
面であるメサストライプ状に加工し、メサ側面を第1導
電型の半導体層及び第2導電型の半導体層を含む半導体
多層膜で埋め込む半導体装置において、最初に上記第1
導電型の半導体層、次に上記第2導電型の半導体層を埋
め込み成長した後に、表面から上記半導体層を第1導電
型とするドーパントを拡散し、その後さらに上記第1導
電型及び上記第2導電型の半導体層を埋め込み成長する
ことを特徴とする半導体装置。
1. A multi-layered structure including an active layer is formed on a semiconductor substrate, and the multi-layered structure is processed into a mesa stripe shape having a smooth curved surface with no inflection point, and the mesa side surface is formed of a first conductivity type. A semiconductor device embedded with a semiconductor multilayer film including a semiconductor layer of a second conductivity type and a semiconductor layer of a second conductivity type.
After a conductive type semiconductor layer and then the second conductive type semiconductor layer are embedded and grown, a dopant having the semiconductor layer as the first conductive type is diffused from the surface, and then the first conductive type and the second conductive type are further diffused. A semiconductor device, wherein a conductive type semiconductor layer is embedded and grown.
【請求項2】請求項1において、MOCVD装置を用い
て、最初に上記第1導電型の半導体層、次に上記第2導
電型の半導体層を埋め込み成長した後に、同じ装置内で
表面から上記半導体層を第1導電型とするドーパントを
拡散し、その後さらに上記第1導電型及び上記第2導電
型の半導体層を埋め込み成長する半導体装置の製造方
法。
2. The MOCVD apparatus according to claim 1, wherein first the semiconductor layer of the first conductivity type and then the semiconductor layer of the second conductivity type are buried and grown first, and then the same is grown from the surface in the same apparatus. A method of manufacturing a semiconductor device, wherein a dopant having a semiconductor layer as a first conductivity type is diffused, and then the semiconductor layers of the first conductivity type and the second conductivity type are further embedded and grown.
【請求項3】p型InP基板上に活性層を含む多層構造
を形成し、上記多層構造を、側面が変曲点の無い滑らか
な曲面であるメサストライプ状に加工し、メサ側面をZ
nドープp型InP層及びSiドープn型InP層で埋
め込む半導体レーザ装置において、最初にp型InP
層、次にn型InP層を埋め込み成長した後に、表面か
らZnを拡散し、その後さらにp型及びn型InP層を
埋め込み成長することを特徴とする半導体レーザ装置。
3. A multi-layer structure including an active layer is formed on a p-type InP substrate, the multi-layer structure is processed into a mesa stripe shape having a smooth curved surface with no inflection point, and the mesa side surface is Z-shaped.
In a semiconductor laser device embedded with an n-doped p-type InP layer and a Si-doped n-type InP layer, p-type InP is first
A semiconductor laser device, wherein a layer, then an n-type InP layer is buried and grown, Zn is diffused from the surface, and then p-type and n-type InP layers are further buried and grown.
【請求項4】請求項3において、MOCVD装置を用い
て、最初に上記p型InP層、次に上記n型InP層を
埋め込み成長した後に、同じ装置内で表面からZnを拡
散し、その後さらに上記p型及び上記n型InP層を埋
め込み成長する半導体レーザ装置の製造方法。
4. The MOCVD apparatus according to claim 3, wherein first, the p-type InP layer and then the n-type InP layer are grown by burying, and then Zn is diffused from the surface in the same apparatus. A method for manufacturing a semiconductor laser device in which the p-type and the n-type InP layers are embedded and grown.
JP8113387A 1996-05-08 1996-05-08 Semiconductor device and manufacture thereof Withdrawn JPH09298334A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8113387A JPH09298334A (en) 1996-05-08 1996-05-08 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8113387A JPH09298334A (en) 1996-05-08 1996-05-08 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH09298334A true JPH09298334A (en) 1997-11-18

Family

ID=14611027

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8113387A Withdrawn JPH09298334A (en) 1996-05-08 1996-05-08 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH09298334A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6470038B2 (en) * 1997-10-20 2002-10-22 Oki Electric Industry Co., Ltd. Compound semiconductor light emitting device and process for producing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6470038B2 (en) * 1997-10-20 2002-10-22 Oki Electric Industry Co., Ltd. Compound semiconductor light emitting device and process for producing the same
US6562649B2 (en) 1997-10-20 2003-05-13 Oki Electric Industry Co., Ltd. Compound semiconductor light emitting device and process for producing the same

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