JPS594119A - Annealing method of compound semiconductor - Google Patents
Annealing method of compound semiconductorInfo
- Publication number
- JPS594119A JPS594119A JP11317582A JP11317582A JPS594119A JP S594119 A JPS594119 A JP S594119A JP 11317582 A JP11317582 A JP 11317582A JP 11317582 A JP11317582 A JP 11317582A JP S594119 A JPS594119 A JP S594119A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- compound semiconductor
- arsenic
- annealing
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
Landscapes
- Physics & Mathematics (AREA)
- High Energy & Nuclear Physics (AREA)
- Engineering & Computer Science (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Abstract
Description
【発明の詳細な説明】
（１１発明の技術分野
未発明はイオン注入のなされた化合物半導体、主として
ガリウム砒素（ＧａＡｅ）、インジウムリン（Ｔｎｐ）
、及びこれらの混晶等のアニール法に関する。特に、イ
オン注入層上に保護膜を必要としない、キャップレスア
ニール法の改良に関する。Detailed Description of the Invention (11) Technical Field of the Invention The invention is related to ion-implanted compound semiconductors, mainly gallium arsenide (GaAe) and indium phosphide (Tnp).
, and annealing methods for these mixed crystals. In particular, it relates to improvements in capless annealing methods that do not require a protective film on the ion-implanted layer.
（２） 技術の背景
化合物半導体、主としてガリウム砒素（ＧａＡｅ）、イ
ンジウムリン（工ｎＰ）、及びこれらの混晶へのイオン
注入技術は半導体装置を製造する上マ極めて有用である
。ところで、この技術にあっては、イオン注入された不
純物を活性化するために、８ｏ。(2) Background of the technology Ion implantation technology into compound semiconductors, mainly gallium arsenide (GaAe), indium phosphide (nP), and mixed crystals thereof, is extremely useful for manufacturing semiconductor devices. By the way, in this technique, 8o is used to activate the ion-implanted impurity.
〜８５０〔℃〕の温度範囲においてなす基板のアニール
工程が必須である。ところが、上記の化合物半導体及び
その混晶には、高い蒸気圧を有する物質が含まれており
、それが上記のアニール工程で昇華し、その結果、結晶
に欠陥を生じる。Annealing the substrate in a temperature range of ~850 [°C] is essential. However, the above-mentioned compound semiconductor and its mixed crystal contain a substance having a high vapor pressure, which sublimes in the above-mentioned annealing process, resulting in defects in the crystal.
そこ〒、このような不利益を防止するために、（イ）基
板表面を二酸化シリコン（Ｓ ｉ Ｏ２） 、窒化シリ
コン（Ｓｉ３Ｎ４）等の保護膜１隋うことによりなされ
る保護膜アニール法と、（ロ）高い蒸気圧を有する元素
の昇華を防止するためガスを封入することによｒＪ す
ｔ 、キャップレスアニール法との二種の方法が実用化
されている。Therefore, in order to prevent such disadvantages, (a) a protective film annealing method is used in which a protective film of silicon dioxide (S i O 2 ), silicon nitride (Si 3 N 4 ), etc. is deposited on the substrate surface; (b) Two methods have been put into practical use: rJ st by enclosing gas to prevent sublimation of elements with high vapor pressure, and capless annealing.
しかし、保護膜アニール法は、保護膜と基板との界面に
界面準位が発生したり、両者の熱膨張係数の差にもとづ
きアニール工程中に基板に大きな熱歪みを与えるという
欠点を有し、一方キャンプレスアニール法↑は、このよ
うな不利益は生じないが、例えばアルシン（Ａ ｓ Ｎ
３ ） 、ホスフィン（ＰＨ３）等人体に有害な物質を
使用するという欠点を有する。However, the protective film annealing method has the disadvantage that interface states are generated at the interface between the protective film and the substrate, and large thermal distortions are given to the substrate during the annealing process due to the difference in thermal expansion coefficients between the two. On the other hand, the campless annealing method↑ does not cause such disadvantages, but for example, arsine (A s N
3) It has the disadvantage of using substances harmful to the human body, such as phosphine (PH3).
本発明は、基板の欠陥等、特性に影響を及ぼさないキャ
ップレスアニール法の改良である。The present invention is an improvement of the capless annealing method that does not affect the characteristics such as defects in the substrate.
（３） 従来技術と問題点
キャップレスアニール法の改良として、従来技術におい
ては、イオン注入のなされた基板上面と、その基板と同
一の化合物半導体よりなる板状材とを接触させた状態で
アニールをなす方法と、更にこの構成に重ねて、蒸気圧
の高い元素のガスを比較的低い蒸気圧↑封入して昇華防
止効果を高める方法とが提案されているが、これらの方
法のいづれにおいても基板表面が傷つく等の不都合が避
けられない。(3) Conventional technology and problems As an improvement to the capless annealing method, in the conventional technology, annealing is performed while the top surface of a substrate into which ions have been implanted is in contact with a plate-like material made of the same compound semiconductor as that substrate. A method has been proposed in which the sublimation prevention effect is enhanced by enclosing an elemental gas with a relatively low vapor pressure ↑ in addition to this structure, but none of these methods Inconveniences such as damage to the substrate surface cannot be avoided.
（４）発明の目的
本発明の目的は、この欠点を解消することにあ番〕、化
合物半導体を構成する物質の昇華を防ぐ目的でガスを封
入することを必快とせず、しかも、光分な活性化効果の
得られるキャップレスアニール法を提供することにある
。(4) Purpose of the Invention The purpose of the present invention is to eliminate this drawback, and to eliminate the necessity of sealing in gas for the purpose of preventing sublimation of the substances constituting the compound semiconductor, and to The object of the present invention is to provide a capless annealing method that provides an effective activation effect.
（５）発明の構成
本発明の構成は、（イ）イオン注入のなされた化合物半
導体よりなる基板に、該化合物半導体を構成する物質の
うち高い蒸気圧を有する物質よりなる板状材を、僅少な
距離上記基板と離隔して対向させながらなすことを特徴
とする、化合物半導体のアニール法にある０、
また、上記（イ）の構成において、前記高い蒸気圧を有
する物質よりなる板状材は、（ロ）化学的に安定な材料
よりなるΔンート内に形成された凹部に堆積されるか、
または、（ハ）前記化合物半導体よりなるセード内に形
成された四部に堆積されることにある０
以−ヒの構成によれば、イオン注入された基板表面と対
接させ、僅かな距離例えば１〔μｍ〕程度離隔して配設
された高い蒸気圧を有する物質よりなる板状材表面との
間の空間に上記の高い蒸気圧を有する物質が飽和蒸気圧
をもって充満することとなるため、基板表面からの昇華
を有効に防止することが可能〒ある。(5) Structure of the Invention The structure of the present invention is as follows: (a) A plate-like material made of a substance having a high vapor pressure among the substances constituting the compound semiconductor is slightly attached to a substrate made of an ion-implanted compound semiconductor. 0 in the compound semiconductor annealing method, which is characterized in that the annealing is performed while facing the substrate at a distance of , (b) deposited in a recess formed in a Δnt made of a chemically stable material;
or (c) the ions are deposited on the four parts formed in the shade made of the compound semiconductor. Since the space between the surface of the plate-shaped material made of a substance having a high vapor pressure and arranged at a distance of about [μm] is filled with the substance having a high vapor pressure at a saturated vapor pressure, the substrate It is possible to effectively prevent sublimation from the surface.
また、上記のボートの材料は、基板と同一の化合物半導
体の他に、石英等、化学的に安定な材料を用いてもよく
、これらのチートにはエツチング法等を使用して深さ５
μｍ程度の凹部を形成し、その四部に高い蒸気圧を有す
る物質を真空蒸着法等を使用して堆積させることが現実
的↑ある。In addition to the same compound semiconductor as the substrate, chemically stable materials such as quartz may be used for the material of the boat, and these cheats can be etched to a depth of 5.
It is practical to form a concave portion of approximately μm size and deposit a substance having a high vapor pressure on the four portions using a vacuum evaporation method or the like.
（６）発明の実施例
以下図面を参照しつつ、本発明の一実施例に係る化合物
半導体のアニール法について説明し、本発明の構成と特
有の効果とを明らかにする〇−例としてガリウム砒素（
ｃｉａＡｓ）よりなる基板に対してなされるキャップレ
スアニール法について述べる。(6) Embodiment of the Invention A method of annealing a compound semiconductor according to an embodiment of the present invention will be explained below with reference to the drawings, and the structure and unique effects of the present invention will be clarified. (
A capless annealing method performed on a substrate made of ciaAs) will be described.
第１図に示す如く、イオン注入層２が形成されたガリウ
ム砒素（ＧａＡｓ）よりなる基板１を、この基板１と四
−の表面寸法を有し、ガリウム砒素（ＧａＡｓ）よりな
るぜ−ト３の凹部に形成された砒素（八〇）よりなる層
４と対向、接近させた状態１反応管内に設置し、水素（
Ｎ２）または窒素（Ｎ２）雰囲気中、８５０〔℃〕程度
において約２０分間アニールを行なう。このアニールに
より、上記基板１と砒素層４との間の空間５には、砒素
（Ａｓ）の蒸気が飽和蒸気圧をもって充満し、基板１か
ら砒素（八〇）が昇華することを有効に防止する。更に
上記、Ｎ−トは繰り返し使用することが可能である。As shown in FIG. 1, a substrate 1 made of gallium arsenide (GaAs) on which an ion-implanted layer 2 is formed is connected to a substrate 1 made of gallium arsenide (GaAs) having a surface dimension of 4. The layer 4 made of arsenic (80) formed in the recess of
Annealing is performed for about 20 minutes at about 850 [° C.] in a nitrogen (N2) or nitrogen (N2) atmosphere. Through this annealing, the space 5 between the substrate 1 and the arsenic layer 4 is filled with arsenic (As) vapor at a saturated vapor pressure, effectively preventing the sublimation of arsenic (As) from the substrate 1. do. Furthermore, the above-mentioned N-to can be used repeatedly.
上記工程によれば、結果として、活性化率８８〔チ〕程
度の動作層が得られる。また、このイオン注入により形
成された動作層のキャリヤ濃度プロファイルは第２図に
示す如くなり、本実施例により得られた曲線（実線）は
ＬＳＢ理論より求めた曲線（破線）とかなり良く一致す
ることが確められた０
（力 発明の効果
以−ト説、明せるとおり、本発明によれば、化合物半導
体を構成する物質の列華を防ぐ目的でガスを刺入するこ
とを必要とせず、しかも充分な活性化効果の得られるキ
ャップレスアニール法を提供することができる。According to the above process, as a result, an active layer with an activation rate of about 88 [H] is obtained. Moreover, the carrier concentration profile of the active layer formed by this ion implantation is as shown in FIG. 2, and the curve obtained in this example (solid line) agrees quite well with the curve obtained from the LSB theory (dashed line). Effects of the Invention As can be seen, according to the present invention, it is not necessary to inject gas for the purpose of preventing the substances constituting the compound semiconductor from collapsing. Moreover, it is possible to provide a capless annealing method that provides a sufficient activation effect.
第１図は、本発明の一実施例に係り、アニールに先立ち
、ガリウム砒素（ＧａＡｓ）よりなるボートにＭＡ積さ
れた砒素（Ａｓ）層に対接して設置されたガリウム砒素
（ＧａＡｓ）よりなる基板を模式的に表わしたもの１あ
り、第２図は、本発明の一実施例により得られた動作層
の結晶プロファイルをＬＥｉＳ理論より得られたそれと
比較して示したグラフである。
１・・・基板（ＧａＡｓ）、２・・・イオン注入法によ
り形成された動作層、３・・・ＧａＡ ｅよりなる＆−
ト、４７−FIG. 1 shows an example of the present invention, in which a layer of gallium arsenide (GaAs) is placed in contact with an arsenic (As) layer MA laminated on a boat made of gallium arsenide (GaAs) prior to annealing. FIG. 2 is a graph showing a comparison of the crystal profile of the active layer obtained according to an embodiment of the present invention with that obtained from the LEiS theory. DESCRIPTION OF SYMBOLS 1... Substrate (GaAs), 2... Active layer formed by ion implantation method, 3... Consisting of GaA e &-
G, 47-
Claims (3)
に、該化合物半導体を構成する物質のうち高い蒸気圧を
有する物質よりなる板状材を、僅少な距離離隔して対向
させながらなすことを特徴とする、化合物半導体のアニ
ール法。(1) A substrate made of a compound semiconductor into which ions have been implanted, and a plate-like material made of a substance having a high vapor pressure among the substances constituting the compound semiconductor are placed facing each other at a slight distance from each other. An annealing method for compound semiconductors.
化学的に安定な材料よりなるセード内に形成された凹部
に堆積されてなる、特許請求の範囲第１項記載の化合物
半導体のアニール法。(2) The plate material made of the substance having high vapor pressure is
A method of annealing a compound semiconductor according to claim 1, wherein the compound semiconductor is deposited in a recess formed in a shade made of a chemically stable material.
前記化合物半導体よりなるキード内に形成された凹部に
堆積されてなる、特許請求の範囲第１項記載の化合物半
導体のアニール法。(3) The plate material made of the substance having high vapor pressure is
2. The method of annealing a compound semiconductor according to claim 1, wherein the compound semiconductor is deposited in a recess formed in a key made of the compound semiconductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11317582A JPS594119A (en) | 1982-06-30 | 1982-06-30 | Annealing method of compound semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11317582A JPS594119A (en) | 1982-06-30 | 1982-06-30 | Annealing method of compound semiconductor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS594119A true JPS594119A (en) | 1984-01-10 |
Family
ID=14605448
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11317582A Pending JPS594119A (en) | 1982-06-30 | 1982-06-30 | Annealing method of compound semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS594119A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007335650A (en) * | 2006-06-15 | 2007-12-27 | Mitsubishi Electric Corp | Method of heating silicon carbide semiconductor substrate |
-
1982
- 1982-06-30 JP JP11317582A patent/JPS594119A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007335650A (en) * | 2006-06-15 | 2007-12-27 | Mitsubishi Electric Corp | Method of heating silicon carbide semiconductor substrate |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4565584A (en) | Method of producing single crystal film utilizing a two-step heat treatment | |
| JP3330218B2 (en) | Semiconductor device manufacturing method and semiconductor device | |
| JPS6249729B2 (en) | ||
| JPS6236000B2 (en) | ||
| JPH01270593A (en) | Method for forming compound semiconductor layer | |
| JPS594119A (en) | Annealing method of compound semiconductor | |
| JPS637624A (en) | Method of diffusing material providing conductivity type into compound semiconductor material of group iii-v | |
| JPH0684938A (en) | Manufacture of semiconductor device | |
| JP2757364B2 (en) | Semiconductor device | |
| JP3035941B2 (en) | Method for manufacturing group III-V compound semiconductor device | |
| JPH0143454B2 (en) | ||
| JPS63252420A (en) | Compound semiconductor crystal and manufacture thereof | |
| JP2691572B2 (en) | Method for manufacturing compound semiconductor device | |
| JPH09321041A (en) | Protective film for semiconductor device and method for forming the same | |
| JP2563455B2 (en) | Method for manufacturing semiconductor device | |
| JPS6043658B2 (en) | Manufacturing method of semiconductor device | |
| JPH0746687B2 (en) | Annealing method for GaAs substrate | |
| JPS63248796A (en) | Molecular beam epitaxy and its device | |
| JPH09321060A (en) | Electric field effect transistor and its manufacture | |
| JPH01112748A (en) | Manufacture of semiconductor device | |
| JPS61145823A (en) | Molecular beam epitaxial growth method | |
| JPS6118126A (en) | P-n junction forming method | |
| JPH0758700B2 (en) | Heat treatment method | |
| JPH0243720A (en) | Molecular beam epitaxial growth method | |
| JPS59110111A (en) | Manufacture of semiconductor device |