JP2691572B2 - Method for manufacturing compound semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to an improvement in a method of manufacturing a compound semiconductor device having a channel of a two-dimensional electron gas layer generated by using, for example, a selective doping technique. In the same direction, the electrical isolation between the substrate and the active region is performed to prevent the occurrence of electrical interference between adjacent semiconductor devices and to improve the degree of integration. An arsenic-containing compound semiconductor interlayer separation layer (or aluminum) having a high resistance over the entire surface in a state where arsenic is excessively supplied as compared with a compound semiconductor layer of the same type (or an aluminum-containing compound semiconductor layer) that is subsequently grown on the surface of an insulating compound semiconductor substrate. And a step of growing an arsenic-containing compound semiconductor interlayer isolation layer, and then the arsenic-containing compound semiconductor interlayer isolation layer (or aluminum and arsenic-containing compound semiconductor). A step of growing a necessary compound semiconductor layer such as an active layer on the interlayer isolation layer), and then selectively implanting oxygen ions from the surface of the compound semiconductor layer to form the arsenic-containing compound semiconductor interlayer isolation layer (or aluminum and arsenic). And a step of forming a high-resistance element isolation layer reaching the contained compound semiconductor interlayer isolation layer).

[Industrial applications]

The present invention relates to an improvement in a method of manufacturing a compound semiconductor device having a channel of a two-dimensional electron gas layer generated by using, for example, a selective doping technique.

In order to improve the operation speed of a semiconductor device, a compound semiconductor such as a GaAs-based semiconductor is put into practical use, and a so-called
A semiconductor device such as a high electron mobility field effect transistor (HEMT) that uses generated electrons in a two-dimensional state as a carrier by applying a selective doping technique has been developed.

As such a semiconductor device is highly integrated,
It is becoming a problem that electrical interference occurs between adjacent semiconductor devices, resulting in malfunction of the mutual semiconductor devices.

[Conventional technology]

In the conventional method of manufacturing a semiconductor device of the type described above, as means for separating adjacent semiconductor devices, (1) etching between semiconductor devices to scrape off them to form a void (recess method) (2) ) Oxygen is implanted between semiconductor devices by an ion implantation method to form a high resistance region (oxygen implantation method).

When the recess method of (1) is used, there is a manufacturing difficulty because it is necessary to pass through a void to form an electrode / wiring between semiconductor devices. However, the oxygen implantation method (2) is currently widely used because it is effective for high integration.

[Problems to be solved by the invention]

In the conventional technique, as described above, the electrical isolation between the semiconductor devices is mainly considered in the lateral direction,
Sufficient measures have not been taken between the substrate and the element, that is, in the vertical direction.

However, in recent years, for example, a semi-insulating GaAs substrate, a non-doped GaAs buffer layer, an interface layer inserted at the interface between the substrate and an epitaxially grown semiconductor crystal layer, which are often used as a substrate, are also used as electrical contacts between adjacent semiconductor devices. It has become clear that it causes interference.

At present, for example, as a semi-insulating GaAs substrate, Cr-O is doped in a non-doped state to have a resistivity of 10 ⁷ [Ω].
.Cm] or more, and attempts have been made to use an AlGaAs layer as a buffer layer, but it is not sufficient as an electrical isolation means for high integration.

According to the present invention, the substrate and the active region are electrically separated not only in the horizontal direction but also in the vertical direction to prevent the occurrence of electrical interference between the adjacent semiconductor devices and to improve the integration degree. It is possible to improve.

[Means for solving the problem]

For example, molecular beam epitaxial growth
When GaAs is epitaxially grown by applying the epitaxy: MBE method, excessive irradiation with As molecular beam causes As atoms to be incorporated into the lattice of the GaAs crystal to generate lattice defects. These lattice defects generate deep level electron traps in the GaAs crystal, and the GaAs crystal has a high resistance.

In the present invention, this phenomenon is utilized to perform interlayer separation between the semi-insulating compound semiconductor substrate and the compound semiconductor layer.

FIG. 1 is a semiconductor device for explaining the principle of the present invention (HE
It shows a side view of the main part of the MT).

In the figure, 1 is a semi-insulating GaAs substrate, 2 is a high resistance non-doped GaAs interlayer isolation layer, and 3 is non-doped Ga.
As active layer, 4 is Si-doped AlGaAs electron supply layer,
5 is a GaAs contact layer doped with Si, 6 is a two-dimensional electron gas layer, 7 is an element isolation layer formed by injecting oxygen, 8 _{S1 and} 8 _S2 are source electrodes, 8 _{G1 and} 8 _G2 are gate electrodes, 8 _{D1 and} 8 _D2 are drain electrodes, and 10 is an alloyed region.

When manufacturing this semiconductor device, a semi-insulating GaAs substrate 1
The surface of the substrate is excessively irradiated with As molecular beams to grow a high-resistance GaAs interlayer isolation layer 2, and a non-doped GaAs active layer 3, an n ⁺ type AlGaAs electron supply layer 4, and an n ⁺ type GaAs contact layer are formed thereon. 5
Are sequentially grown, and then oxygen is selectively injected to form the element isolation layer 7.

By doing so, the completed HEMTs are in a state of being surrounded by layers each having a high resistance, so that electrical interference does not occur in them.

From the above, in the method of manufacturing the compound semiconductor device according to the present invention, the compound semiconductor layer of the same kind or aluminium-containing compound which is subsequently grown on the surface of the semi-insulating compound semiconductor substrate (for example, the semi-insulating GaAs substrate 1). Compound semiconductor layer (eg non-doped GaAs active layer 3 or n ⁺ type)
High resistance arsenic-containing compound semiconductor interlayer isolation layer or aluminum and arsenic-containing compound semiconductor interlayer isolation layer (for example, non-doped GaAs interlayer isolation layer 2 or A step of growing a non-doped AlGaAs interlayer isolation layer 2 ') and a step of growing a necessary compound semiconductor layer such as an active layer on the arsenic-containing compound semiconductor interlayer isolation layer or the aluminum and arsenic-containing compound semiconductor interlayer isolation layer. And then
Oxygen ions are selectively implanted from the surface of the compound semiconductor layer to reach the arsenic-containing compound semiconductor interlayer isolation layer or the aluminum and arsenic-containing compound semiconductor interlayer isolation layer (for example, oxygen is implanted to form the element isolation layer). And the step of forming the inter-element isolation layer 7).

[Action]

By adopting the above means, the influence of the semi-insulating compound semiconductor substrate is less likely to affect the semiconductor device, and the substrate and the active region are electrically separated not only in the horizontal direction but also in the vertical direction. The electrical interference between the elements is almost eliminated, and the performance is not deteriorated even with high integration.

〔Example〕

Prior to describing one embodiment of the present invention, an MBE device suitable for application thereto will be described.

FIG. 2 is an explanatory view of the main parts for explaining an example of an MBE device used when implementing the present invention. The same symbols as those used in FIG. 1 indicate the same parts or have the same meanings. I have it.

In the figure, 11 is a crystal growth chamber, 12 is a gate valve,
13 is a heater, 14 is a thermocouple, 15 is a susceptor, 16 is a liquid nitrogen shroud, 17A is a molecular beam source furnace of Ga, 17B is a molecular beam source furnace of Al, 17C is the first As molecular beam source furnace, and 17D is A second As molecular beam source furnace, 17E represents a Si molecular beam source furnace, and 18A to 18E represent shutters.

3 to 7 are sectional side views of the essential part of the HEMT in the process steps for explaining one embodiment of the present invention, which will be described below with reference to these figures. The same symbols as those used in FIGS. 1 and 2 indicate the same parts or have the same meaning.

See Fig. 3 (1) Attach the semi-insulating GaAs substrate 1 to the susceptor 15 of the crystal growth chamber 11 in the MBE device, open the shutter 18C of the first As molecular beam source furnace 17C, and irradiate As molecular beams. At the same time, the temperature of the substrate 1 is raised to, for example, 750 [° C.], and the state is maintained for, eg, 3 [minutes] to perform thermal etching.

When such thermal etching is performed, the interface level between the substrate 1 and the semiconductor layer grown thereon becomes 10 ^11.
[Cm ^-2 ] or about 10 ¹² [cm when using the conventional technology
^-2 ] compared to about 1 digit, so even if the buffer layer is formed thin, the compound semiconductor layers grown on it will be of good quality, especially in the case of HEMT. Needless to say, it is possible to eliminate the substrate bias effect during operation and to improve the through-put if the buffer layer can be thinned.

See FIG. 4 (2) While maintaining the state of the step (1), the shutter 18A of the Ga molecular beam source furnace 17A and the shutter 18D of the second As molecular beam source furnace 17D are opened, and the thickness is, for example, 200
A non-doped GaAs interlayer isolation layer 2 having a thickness of about [Å] is grown.

Since the non-doped GaAs interlayer separation layer 2 is grown by being irradiated with As molecular beams from the first As molecular beam source 17C and the second As molecular beam source 17D, the supply of As becomes excessive. ,
As a result, the resistance value becomes high and the role of interlayer separation can be sufficiently fulfilled. The thickness is 200 [Å] to 200
It can be selected in the range of 0 [Å].

See Fig. 5 (3) Close the shutter 18D of the second As molecular beam source 17D,
Non-doped GaAs having a thickness of, for example, about 0.2 μm
After the active layer 3 is grown, the shutter 18B of the Al molecular beam source 17B and the shutter 18E of the Si molecular beam source 17E are opened, and Si is doped to a thickness of, for example, about 1 × 10 ¹⁸ [cm ⁻³ ].
The AlGaAs electron supply layer 4 having a thickness of about 0.09 [μm] is grown, and thereafter, the shutter 18B of the Al molecular beam source 17B is closed and Si is doped with, for example, about 1 × 10 ¹⁸ [cm ⁻³ ] to a thickness of, for example, 0. .
The GaAs contact layer 5 of about 01 [μm] is grown.

It goes without saying that when the semiconductor layers are laminated in this manner, the two-dimensional electron gas layer 6 is generated on the active layer 3 side at the interface between the active layer 3 and the electron supply layer 4.

The active layer 3 grown here partially plays a role of a buffer layer together with the interlayer isolation layer 2, and its thickness is about 0.2 [μm] as described above, which depends on the conventional technique. Although the active layer was about 0.6 [μm], it is extremely thin as compared with the active layer, but the crystallinity of the part where the two-dimensional electron gas layer 6 is generated is still very good. As a result, there are very few levels at the interface between the substrate 1 and the interlayer separation layer 2, and
This is because the crystallinity of the interlayer isolation layer 2 is good, and the goodness is inherited by the active layer 3 as well. Thus, since the active layer 3 can be formed thin,
Put is greatly improved.

See Fig. 6 (4) By taking out the substrate 1 from the MBE device and applying a resist process in a normal photolithography technique, a photo resist mask having an opening at a portion where an element isolation layer is to be formed. After forming the substrate, the substrate 1 is placed again in the ion implantation chamber of the ion implantation apparatus, and the dose amount is set to, for example, about 1 × 10 ¹² [cm ⁻² ] and the acceleration energy is set to, for example, about 100 [KeV]. Oxygen ions are implanted to form the element isolation layer 7 reaching the interlayer isolation layer 2.

See Fig. 7 (5) Recess formation in the gate region, formation of source electrodes 8 _{S1 and} 8 _S2 , formation of drain electrodes 8 _{D1 and} 8 _D2 , etc. and two-dimensional electron Alloying treatment for obtaining ohmic contact with the gas layer 6 is performed, and then the gate electrodes 8 _{G1 and} 8 _G2 are formed to complete the process. As described above, the symbol 10 indicates the alloying region generated by the alloying process.

8 to 12 are sectional side views of the essential part of the HEMT in the process steps for explaining another embodiment of the present invention, which will be described below with reference to these drawings. . The first
The same symbols as those used in FIGS. 7 to 7 indicate the same parts or have the same meanings.

See Fig. 8 (1) Attach the semi-insulating GaAs substrate 1 to the susceptor 15 of the crystal growth chamber 11 in the MBE device, open the shutter 18C of the first As molecular beam source furnace 17C, and irradiate the As molecular beam. At the same time, the temperature of the substrate 1 is raised to, for example, 750 [° C.] exceeding about 600 [° C.], and the state is maintained for, eg, 3 [minutes] to perform thermal etching to remove the natural oxide film and the like. To do.

The advantages obtained by going through this process are the same as those in the above-mentioned embodiment.

See FIG. 9 (2) While maintaining the state of the step (1), the shutter 18A of the Ga molecular beam source furnace 17A, the shutter 18D of the second As molecular beam source furnace 17D, and the shutter 18B of the Al molecular beam source 17B.
Are simultaneously opened to grow a non-doped AlGaAs interlayer isolation layer 2'having a thickness of, for example, about 200 [Å].

Since the non-doped AlGaAs interlayer separation layer 2'is grown in a state where the supply of As is excessive, as in the above-mentioned embodiment, its resistance value becomes high and it is possible to sufficiently fulfill the role of interlayer separation. Also, in this case as well, the thickness can be selected in the range of 200 [Å] to 2000 [Å].

See Fig. 10. (3) The shutter 18B of the Al molecular beam source 17B and the shutter 18D of the second As molecular beam source 17D are closed, and the thickness is, for example, 0.2.
A non-doped GaAs active layer 3 having a thickness of about [μm] is grown, and then the shutter 18B of the Al molecular beam source 17B and the shutter 18E of the Si molecular beam source 17E are opened to remove Si by, for example, 1 × 10 ¹⁸ [cm
^-3 ] Doped thickness of about 0.09 [μm]
The AlGaAs electron supply layer 4 is grown, and then the Al molecular beam source 17
The shutter 18B of B is closed and Si is, for example, 1 × 10 ¹⁸ [cm ^-3 ]
GaAs with a thickness of approximately 0.01 μm
The contact layer 5 is grown.

When the respective semiconductor layers are stacked in this manner, the two-dimensional electron gas layer 6 is generated on the active layer 3 side at the interface between the active layer 3 and the electron supply layer 4, as in the above-described embodiment. no change.

See Fig. 11 (4) By taking out the substrate 1 from the MBE device and applying a resist process in a normal photolithography technique, a photo resist mask having an opening in a portion where an element isolation layer is to be formed. After forming the substrate, the substrate 1 is placed again in the ion implantation chamber of the ion implantation apparatus, and the dose amount is set to, for example, about 1 × 10 ¹² [cm ⁻² ] and the acceleration energy is set to, for example, about 100 [KeV]. Oxygen ions are implanted to form the element isolation layer 7 reaching the interlayer isolation layer 2'from the surface.

See Fig. 12 (5) Recess formation in the gate region, formation of source electrodes 8 _{S1 and} 8 _S2 , drain electrodes 8 _{D1 and} 8 _D2 , etc., and two-dimensional electron Alloying treatment for obtaining ohmic contact with the gas layer 6 is performed, and then the gate electrodes 8 _{G1 and} 8 _G2 are formed to complete the process. As described above, the symbol 10 indicates the alloying region generated by the alloying process.

The completed HEMT can be manufactured by any of the above embodiments.
No electrical interference occurred during the period. Further, the main difference between the first embodiment and the second embodiment,
GaAs and Al as materials for the interlayer isolation layer 2 and the interlayer isolation layer 2 '.
Although GaAs is adopted respectively, AlGaAs has many deep level electron traps compared to GaAs, so that it is easy to increase the resistance.

〔The invention's effect〕

In the method of manufacturing a compound semiconductor device according to the present invention, an arsenic-containing compound semiconductor interlayer separation layer (or aluminum and arsenic) having a high resistance obtained by excessively supplying and growing arsenic on the surface of a semi-insulating compound semiconductor substrate. A compound semiconductor interlayer separation layer containing compound) and a required compound semiconductor layer are sequentially grown, and a high resistance element reaching the high resistance arsenic containing compound semiconductor interlayer separation layer (or aluminum and arsenic containing compound semiconductor interlayer separation layer) from the surface. An inter-separation layer is formed.

In the compound semiconductor device obtained by adopting the above-mentioned structure, the substrate and the active region are electrically separated not only in the lateral direction but also in the longitudinal direction, so that the semiconductor devices between adjacent semiconductor devices are separated from each other. Since the occurrence of electrical interference is prevented, it is possible to improve the degree of integration. Also, since all semiconductor layers can be formed at a constant temperature, there is no need to increase or decrease the substrate temperature, and a compound semiconductor interlayer separation layer can be easily formed simply by opening and closing the shutter in the second As molecular beam source. can do.

[Brief description of the drawings]

FIG. 1 is a side view of a main part of a semiconductor device for explaining the principle of the present invention, and FIG. 2 is an MBE device for carrying out the present invention.
FIG. 3 to FIG. 7 are side views of the essential part of the HEMT in the process steps for explaining one embodiment of the present invention, and FIGS. 8 to 12 are other embodiments of the present invention. Each of the HEMT cutting side views in the process key points for explanation is shown. In the figure, 1 is a semi-insulating GaAs substrate, 2 is a high resistance non-doped GaAs interlayer separation layer, 2'is a high resistance non-doped AlGaAs interlayer separation layer, and 3 is a non-doped GaAs.
Active layer, 4 is Si-doped AlGaAs electron supply layer, 5
Is a GaAs contact layer doped with Si, 6 is a two-dimensional electron gas layer, 7 is an element isolation layer formed by injecting oxygen,
8 _S1 and 8 _S2 are source electrodes, 8 _G1 and 8 _G2 are gate electrodes, 8
_D1 and 8 _D2 are drain electrodes, and 10 is an alloyed region.

Front page continued (72) Inventor Teruo Yokoyama 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited (56) References JP 59-55074 (JP, A) JP 61-289621 (JP, JP, 289621) A) JP-A-63-132421 (JP, A) JP-A-1-302742 (JP, A) JP-A-55-33079 (JP, A)

Claims (2)

(57) [Claims] 1. A step of growing a high-resistance arsenic-containing compound semiconductor interlayer separation layer on the entire surface in a state in which arsenic is excessively supplied as compared with a compound semiconductor layer of the same kind which is subsequently grown on the surface of a semi-insulating compound semiconductor substrate. Next, a step of growing a necessary compound semiconductor layer such as an active layer on the arsenic-containing compound semiconductor interlayer isolation layer, and then selectively implanting oxygen ions from the compound semiconductor layer surface to form the arsenic-containing compound semiconductor interlayer. And a step of forming a high-resistance element isolation layer reaching the isolation layer. 2. A high-resistance aluminum and arsenic-containing compound semiconductor interlayer isolation over the entire surface in a state in which arsenic is excessively supplied as compared with the same kind of aluminum- and arsenic-containing compound semiconductor layer that is subsequently grown on the surface of a semi-insulating compound semiconductor substrate. A step of growing a layer, a step of growing a necessary compound semiconductor layer such as an active layer on the aluminum- and arsenic-containing compound semiconductor interlayer isolation layer, and a step of selectively implanting oxygen ions from the surface of the compound semiconductor layer. And a step of forming a high-resistance element isolation layer reaching the high-resistance aluminum and arsenic-containing compound semiconductor interlayer isolation layer.