JPH0746687B2 - Annealing method for GaAs substrate - Google Patents
Annealing method for GaAs substrateInfo
- Publication number
- JPH0746687B2 JPH0746687B2 JP13650586A JP13650586A JPH0746687B2 JP H0746687 B2 JPH0746687 B2 JP H0746687B2 JP 13650586 A JP13650586 A JP 13650586A JP 13650586 A JP13650586 A JP 13650586A JP H0746687 B2 JPH0746687 B2 JP H0746687B2
- Authority
- JP
- Japan
- Prior art keywords
- annealing
- gaas substrate
- annealing method
- ash
- arsine
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明はGaAs基板のアニール方法に関するものである。TECHNICAL FIELD The present invention relates to a method for annealing a GaAs substrate.
従来の技術 従来、イオン注入したGaAs基板のアニール方法には、Si
O2,Si3N4等の保護膜を用いるキャップアニール，アルシ
ン（AsH3）雰囲気中などのAs圧を加えてアニールするキ
ャップレスアニールなどがある。Conventional technology Conventionally, the annealing method for ion-implanted GaAs substrate is
There are cap anneals that use protective films such as O 2 and Si 3 N 4, and capless anneals that anneal by applying As pressure in an arsine (AsH 3 ) atmosphere.
発明が解決しようとする問題点 こうした従来のアニール方法では、アルシン雰囲気中の
キャップレスアニールの方が、SiO2,Si3N4等の絶縁膜を
用いるキャップアニールより絶縁膜によるストレスの影
響が少なく、活性化率も高く基板面内の活性化率のバラ
ツキの少なくすぐれている。Problems to be Solved by the Invention In such conventional annealing methods, the capless annealing in the arsine atmosphere is less affected by the stress due to the insulating film than the cap annealing using the insulating film such as SiO 2 or Si 3 N 4. Also, the activation rate is high, and there is little variation in the activation rate within the substrate surface, which is excellent.
しかし、アルシン（AsH3）という、半導体工業で用いら
れるガスの中でもっとも猛毒なガスを用いることが必要
であり、安全性の面で特に注意を要することが必要であ
る。However, as arsine (AsH 3), it is necessary to use the most poisonous gas in the gas used in the semiconductor industry, it is necessary to require special attention in terms of safety.
問題点を解決するための手段 本発明は、アルシン（AsH3）に比して致死量が10倍ほど
大きく毒性の少ないフォスフィン（PH3）中でイオン注
入したGaAs基板をアニールすることを特徴とするもので
ある。Means for Solving the Problems The present invention is characterized by annealing an ion-implanted GaAs substrate in phosphine (PH 3 ) which has a lethal dose 10 times larger than arsine (AsH 3 ) and is less toxic. To do.
作用 本発明はフォスフィン（PH3）雰囲気中でアニールする
ことにより、GaAs表面にGaAsPの極薄層が形成され、GaA
sからのAsの熱分解が抑制され、アルシン（AsH3）雰囲
気中と同様の効果があり、活性化率，基板面内のバラツ
キも、アルシン雰囲気中のアニールよりすぐれているこ
とを実験的に求めたものである。Action In the present invention, by annealing in a phosphine (PH 3 ) atmosphere, an extremely thin layer of GaAsP is formed on the GaAs surface, and GaA
It is experimentally shown that the thermal decomposition of As from s is suppressed, it has the same effect as in the arsine (AsH 3 ) atmosphere, and the activation rate and the variation in the substrate surface are superior to those in the arsine atmosphere. It is what I asked for.
実施例 第１図は、半絶縁性GaAs基板に、ドーズ量を５×1012cm
-2と固定し、加速電圧を30KeV〜150KeVまで変化させてS
i29をイオン注入した試料を、AsH3雰囲気中，およびPH3
雰囲気中でアニールしたものの活性化率を比較したもの
である。As,Pの分圧はどちらも3torr,キャリアガスはAr
を用い、アニール温度は820℃，アニール時間が15分で
ある。図より、PH3中のアニールは、AsH3中のアニール
よりすぐれていることがわかる。Example FIG. 1 shows a semi-insulating GaAs substrate with a dose of 5 × 10 12 cm 2.
Fix at -2 , change the accelerating voltage from 30 KeV to 150 KeV, and
i 29 ion-implanted sample in AsH 3 atmosphere and PH 3
This is a comparison of activation rates of those annealed in the atmosphere. The partial pressures of As and P are both 3 torr, and the carrier gas is Ar.
The annealing temperature is 820 ° C and the annealing time is 15 minutes. The figure shows that annealing in PH 3 is superior to annealing in AsH 3 .
第２図（ａ），（ｂ）は、半絶縁性GaAs基板にSi29を10
0KeV,5×1012cm-2を注入して形成したFETのしきい値電
圧の分布を、AsH3中でアニールしたものと、本発明のPH
3中のアニールしたものを比較したものである。PH3中の
アニールの方が、分布のバラツキが少なくなっているこ
とがわかる。2 (a) and 2 (b) show that a Si 29 film is formed on a semi-insulating GaAs substrate.
The distribution of the threshold voltage of the FET formed by injecting 0 KeV, 5 × 10 12 cm -2 was obtained by annealing in AsH 3 and the PH of the present invention.
This is a comparison of the ones annealed in 3 . It can be seen that the variation in distribution is smaller in annealing in PH 3 .
発明の効果 以上説明したように、本発明によればイオン注入したGa
As基板をアルシン（AsH3）より毒性の少ないフォスフィ
ン（PH3）雰囲気中でアニールすることにより、安全性
が向上し、かつ、アニールのバラツキ，活性化率もすぐ
れたアニール方法を得ることが可能である。以上の説明
では、Siをイオン注入した場合について述べたが、他の
ｎ型不純物，およびｐ型不純物を注入したGaAs基板につ
いても同様の効果があることはいうまでもない。Effects of the Invention As described above, according to the present invention, ion-implanted Ga
By annealing the As substrate in a phosphine (PH 3 ) atmosphere, which is less toxic than arsine (AsH 3 ), it is possible to obtain an annealing method that improves safety and has excellent annealing variation and activation rate. Is. In the above description, the case where Si is ion-implanted has been described, but it goes without saying that the same effect can be obtained with other n-type impurity and p-type impurity-implanted GaAs substrates.
第１図は本発明の一実施例におけるアニール方法と、従
来のアルシン中のアニール方法での活性化率の比較を示
す特性図、第２図は本実施例のアニール方法と従来のア
ルシン中のアニール方法より形成したFETのしきい値電
圧のヒストグラム図である。FIG. 1 is a characteristic diagram showing a comparison of activation rates between an annealing method according to an embodiment of the present invention and a conventional annealing method in arsine, and FIG. It is a histogram diagram of the threshold voltage of the FET formed by the annealing method.
Claims (1)
入したGaAs基板をフォスフィン（PH3）を含む雰囲気中
でアニールするようにしたGaAs基板のアニール方法。1. A method for annealing a GaAs substrate, wherein a GaAs substrate into which atoms serving as n-type or p-type impurities are ion-implanted is annealed in an atmosphere containing phosphine (PH 3 ).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13650586A JPH0746687B2 (en) | 1986-06-12 | 1986-06-12 | Annealing method for GaAs substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13650586A JPH0746687B2 (en) | 1986-06-12 | 1986-06-12 | Annealing method for GaAs substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62291916A JPS62291916A (en) | 1987-12-18 |
| JPH0746687B2 true JPH0746687B2 (en) | 1995-05-17 |
Family
ID=15176730
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13650586A Expired - Lifetime JPH0746687B2 (en) | 1986-06-12 | 1986-06-12 | Annealing method for GaAs substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0746687B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2783140B2 (en) * | 1993-12-22 | 1998-08-06 | 日本電気株式会社 | Surface treatment method for compound semiconductor device |
| JP2001168103A (en) * | 1999-12-10 | 2001-06-22 | Nagoya Kogyo Univ | Semiconductor surface treatment method and semiconductor device to which the same treatment is operated |
-
1986
- 1986-06-12 JP JP13650586A patent/JPH0746687B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62291916A (en) | 1987-12-18 |
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