JPS5941008A - Sequence control circuit - Google Patents

Sequence control circuit

Info

Publication number
JPS5941008A
JPS5941008A JP15098682A JP15098682A JPS5941008A JP S5941008 A JPS5941008 A JP S5941008A JP 15098682 A JP15098682 A JP 15098682A JP 15098682 A JP15098682 A JP 15098682A JP S5941008 A JPS5941008 A JP S5941008A
Authority
JP
Japan
Prior art keywords
address
data
output
input
rom4
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15098682A
Other languages
Japanese (ja)
Inventor
Hiroshi Shiobara
弘 塩原
Kouichirou Satou
佐藤 「こう」一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15098682A priority Critical patent/JPS5941008A/en
Publication of JPS5941008A publication Critical patent/JPS5941008A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00Programme-control systems
    • G05B19/02Programme-control systems electric
    • G05B19/04Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/045Programme control other than numerical control, i.e. in sequence controllers or logic controllers using logic state machines, consisting only of a memory or a programmable logic device containing the logic for the controlled machine and in which the state of its outputs is dependent on the state of its inputs or part of its own output states, e.g. binary decision controllers, finite state controllers

Abstract

PURPOSE:To form and change a program easily and to execute high speed processing with simple constitution by executing processing for an input from the external by the 1st ROM and executing processing for an output to the external by the 2nd ROM. CONSTITUTION:The 1st ROM1 outputs an start address signal to a switching circuit 2 in accordance with an input signal from the external and an address latch 3 latches the output of the circuit 2 to specify the address of the 2nd ROM4. The ROM4 outputs output pattern data to an external device and the ROM1 and executes control in accordance with the contents of output pattern data. The ROM4 also applies the data of the succeeding execution address to a switching circuit 2 to execute control in executing at present by the period specified by the address execution time data and to execute a program specified by the address of the succeeding execution address data read out from the ROM4.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明はプログラムの作成、変更を容易に行なえるシー
ケンスコントロール回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a sequence control circuit that allows easy creation and modification of programs.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

一般にシーケンスコントロール回路は一定の入力信号に
応じて、予めプログラムした出力信号を発生Tる。この
ようなものとしては、たとえばマイクロコンピュータを
用いて、予めプログラムラ書込んだRLIMlao:用
いて制御を行なうものが考えられる。しかしながらこの
ようなものでは、演算回路を有する之めに構造が複雑に
なり、またメモリに作業順域を必要とするためにl(A
M (ランダム、アクセス、メモリ)を必要とし、コス
トも高価になる0またプログラムを単一のl(UM(リ
ード、オンリー、メモリ)(二書き込んだものではその
一部分でも変更する場合は、全てのプログラムを変更す
る必要がある。さらC二この種の装置のプログラミング
には。
Generally, sequence control circuits generate preprogrammed output signals in response to certain input signals. An example of such a device is one that uses a microcomputer to perform control using RLIMlao: written in a program in advance. However, this type of device has a complicated structure due to the arithmetic circuit, and requires a work order area in memory, so l(A
M (Random, Access, Memory) and the cost is also high.Also, if you want to change even a part of a program that has been written in a single l (UM (Read, Only, Memory)), you must write all It is necessary to change the program.Additionally, C2 is required to program this type of device.

一般に制度の技術を必要とし、また何らかの原因でプロ
グラムが暴走した場合に出力信号?与える外部の装置の
保護対策も必要となる。
In general, it requires systematic technology, and is there an output signal if the program goes out of control for some reason? Protective measures for external equipment provided are also required.

さらCマイクロコンピュータを用いずにit−ROMに
書き込んだプログラムを順次に実行するようにしてもほ
とんど同様の問題点を内在でることになる。
Furthermore, even if the programs written in the IT-ROM are executed sequentially without using a C microcomputer, almost the same problems will occur.

〔発明の目的〕[Purpose of the invention]

本発明は上記の事情に1みてなされたものでプログラム
の作成、変更が容易で構造も簡単にでき、しかも高信頼
性を得られるシーケンスコントロール回路を提供するこ
とを目的とするものである。
The present invention has been made in view of the above-mentioned circumstances, and it is an object of the present invention to provide a sequence control circuit that is easy to create and change programs, has a simple structure, and has high reliability.

〔発明の概要〕[Summary of the invention]

Tなわち本発明は、入力信号C二応じてスタートアドレ
ス信号を出力する第1のR(JMとこのスタートアドレ
ス信号で指定されたプログラムを出力する第2のROM
とを設け、この外2のROMの出力信号に含まれる次回
のアドレス信号と上記スタートアドレス信号の一方ヲス
イッを回路で選択して第2のRLIMのアドレス指定を
行なうことを特徴とτるものである、〔発明の実施例〕 ?参照して詳細に説明する。図中1は外部から与えられ
る入力信号に応じて所定のスタート信号?出力する第1
0J R(J Mである。そしてこのスタートアドレス
信号をスイッチ回路2の一方の入力へ与え、さらC二こ
の出力をアドレスラッテ3を介して第2のR(JM4/
\与える。この第2のROM4にtまス示しない外部の
機器および上記第1のR(J Mへ与える出カバターン
データ。
In other words, the present invention includes a first ROM (JM) which outputs a start address signal in response to an input signal C2, and a second ROM (JM) which outputs a program specified by this start address signal.
The second RLIM is addressed by selecting one of the next address signal included in the output signal of the second ROM and the start address signal using a circuit. Is there an [embodiment of the invention]? This will be explained in detail with reference to the following. 1 in the figure is a predetermined start signal according to the input signal given from the outside? The first output
0J R (JM). Then, this start address signal is applied to one input of the switch circuit 2, and the output of C2 is sent to the second R (JM4/
\give. Output pattern data to be provided to external equipment and the first R (JM) which are not shown in this second ROM 4.

該制御の実行期間を指定するアドレス実行時間データ、
次の制御の実行アドレス、制御の停止を指定する停止デ
ータを書き込んでいる。そして上記出カバターンデータ
は第1のRIJMIへ入力される入力信号およびアドレ
スラッテ3とともにマトリックスを構成し、その内容に
応じてスタートアドレス信号の内容を制御する。またア
ドレス実行時間データはスイッチ回路2の他方の人力へ
与え、停止データ5二よりスイッチ回路2?制御する0
丁なわちプログラムの実行開始とともにスイッチ回路2
は他方の入力を選択し、停止データにより他方の入力を
選択する◎このような構成であれば外部から与えられる
入力信号に応じて第10J ROM lからスタートア
ドレス信号をスイッチ回路2へ与える。そしてこのスイ
ッチ回路2の出力をアドレスラッチ3でラッチし、第2
のRUMdのアドレス指定を行なうロセして第2のRL
)M Jから出力される出カバターンデータな図示しな
い外部の機器および第lのl(0M7へ与え、かつアド
レス実行時間データで指定される期聞、上記出カバター
ンデータの内容に応じた制御を行なう。また第2の80
M4から次の実行アドレスのデータをスイッチ回路2へ
与え、場に実行中の制御をアドレス実行時間データで指
定される期旧1だけ実行するとと、もに上記0次の実行
アドレスのデータを読み辺んで該アドレスで指定される
プログラムを実行する0また第2のR(J M 4から
停止データが出力されると、現C−実行中の制御の終了
時点で外部からの入力信号待ちとなるOTなわち、第1
 (IJ R(J M tは外部からの入力に対する処
理を行ない、第2のRUM 4は外部に対下る出力処理
を行なうようにしている口したがってプログラムした制
御の内容を変更し。
address execution time data specifying the execution period of the control;
Writes the next control execution address and stop data that specifies control stop. The output pattern data constitutes a matrix together with the input signal input to the first RIJMI and the address latte 3, and the contents of the start address signal are controlled according to the contents thereof. Also, the address execution time data is given to the other human power of the switch circuit 2, and from the stop data 52, the switch circuit 2? 0 to control
In other words, when the program starts executing, the switch circuit 2
selects the other input, and the stop data selects the other input. With this configuration, a start address signal is provided from the 10th ROM 1 to the switch circuit 2 in response to an externally applied input signal. Then, the output of this switch circuit 2 is latched by the address latch 3, and the second
The second RL addresses the RUMd of
)M Also perform the second 80
When the data of the next execution address is given from M4 to the switch circuit 2 and the control currently being executed is executed for the period 1 specified by the address execution time data, the data of the above-mentioned 0th execution address is read. When the stop data is output from 0 or the second R (J M 4), the program specified by the address is executed, and at the end of the control currently being executed, the program waits for an input signal from the outside. OT i.e. 1st
(IJ R (J M t processes input from the outside, and the second RUM 4 processes output to the outside. Therefore, the programmed control contents are changed.

あるいは新たなプログラムを作53E’fる場合も第1
、第2のl(0M1.4の内容を各別に変更てれはよい
の′V間単かつ容易に行なえる利点がある。また、第1
.第2のROM1.4の内容は所望の制御内答毎C二分
割し、かつ相互仁独立する複数のプログラムを収納し、
これらを適宜に選択てれはよいのでプログラムの作成に
格別。
Or, when creating a new program, the first
, the contents of the second l (0M1.4) can be changed individually.
.. The contents of the second ROM 1.4 are divided into two parts for each desired control answer, and store a plurality of mutually independent programs.
Since you can select these appropriately, it is especially useful for creating programs.

高度の技術も必要としない。さらC−スイツチ回路2C
二は常に次の実行アドレスのデータを与えるようC二し
ているので、プログラムの実行中。
It does not require advanced technology. Further C-switch circuit 2C
Since C2 always gives the data of the next execution address, the program is running.

アドレス実行時間データの内容ヲ経過Tる毎g二次の実
行アドレスのデータで指定される新たな制御?開始する
ため(二原理的にプログラムの暴走を生じない◎ なお出力データ11号は第lのRL)MJへも与え、こ
の内容とへカイー号の内容とに応じてスタートアドレス
信号を出力するマトリクスを構成するようにしている。
Every time the content of the address execution time data elapses, is a new control specified by the data of the secondary execution address? In order to start (the program will not run out of control in two principles), the output data No. 11 is the first RL) and is also given to MJ, and the matrix outputs the start address signal according to this content and the contents of Hekai No. I am trying to configure it.

したがって、上記出力データ信号に応じて外部からの入
力信号(二対Tるスタートアドレス信号の内容?制御す
ることかできる。
Therefore, it is possible to control the contents of an external input signal (two pairs of start address signals) according to the output data signal.

〔発明の効果〕〔Effect of the invention〕

以上詳述したようC二本発明によればプログラムの作成
、変更が容易で構造も簡単でありしかもプログラムの暴
走する虞もなく、コストも安価であり、演算処理回路等
の複雑な回路を用いるものf二比して畠速処理?行なう
ことができるシーケンスコントロール回路を提供するこ
とかできる。
As detailed above, according to the present invention, programs are easy to create and change, the structure is simple, there is no risk of programs running out of control, the cost is low, and complex circuits such as arithmetic processing circuits are used. Is it faster processing compared to the f2? It is possible to provide a sequence control circuit that can perform the following steps.

【図面の簡単な説明】[Brief explanation of the drawing]

図は本発明の一実施例をホ1−ブロック図であるO 1・・・第1のROM、2・・・スイッチ回路、3・・
・アドレスラッチ、4・・・@2のRuMn出1鉱代理
人弁理士 鈴 江 武 彦
The figure is a block diagram showing one embodiment of the present invention.O1...first ROM,2...switch circuit,3...
・Address latch, 4...@2 RuMn output 1 mine agent patent attorney Takehiko Suzue

Claims (1)

【特許請求の範囲】[Claims] 外部から与えられる入力信号に応じてスタートアドレス
信号を出力する第1の1((JMと、上記スタートアド
レス信号を一方の入力へ与えられるスイッチ回路と、こ
のスイッチ回路から与えられるスタートアドレスに応じ
て読み出した出カバターンデータ?外部の機器へ与えて
同時C二出力されるアドレス実行時間の内容に応じた期
は1だけ所定の制′aを行なうとともに上記出カバター
ンデータを上記第lのRtJMへ与えてスタートアドレ
ス信号の内容を制御しざらに次C二実行すべき制御内容
に応じた次の実行アドレスのデータ?上記スイッチ回路
の他方の入力へ与える第2のR(JMとを具備するシー
ケンスコントロール回路0
A first 1 (JM) that outputs a start address signal in response to an input signal given from the outside, a switch circuit to which the start address signal is given to one input, and a switch circuit that outputs a start address signal in response to an input signal given from the switch circuit. The output cover turn data that has been read out is given to an external device and a predetermined control is applied to the period corresponding to the content of the address execution time that is simultaneously outputted by 1, and the above output cover turn data is sent to the first RtJM. The data of the next execution address corresponding to the control content to be executed is controlled by controlling the content of the start address signal, and the second R (JM) is supplied to the other input of the switch circuit. Sequence control circuit 0
JP15098682A 1982-08-31 1982-08-31 Sequence control circuit Pending JPS5941008A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15098682A JPS5941008A (en) 1982-08-31 1982-08-31 Sequence control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15098682A JPS5941008A (en) 1982-08-31 1982-08-31 Sequence control circuit

Publications (1)

Publication Number Publication Date
JPS5941008A true JPS5941008A (en) 1984-03-07

Family

ID=15508782

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15098682A Pending JPS5941008A (en) 1982-08-31 1982-08-31 Sequence control circuit

Country Status (1)

Country Link
JP (1) JPS5941008A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS506239A (en) * 1973-05-17 1975-01-22
JPS5386136A (en) * 1977-01-06 1978-07-29 Nec Corp Control circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS506239A (en) * 1973-05-17 1975-01-22
JPS5386136A (en) * 1977-01-06 1978-07-29 Nec Corp Control circuit

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