JPS5939001A - Chip resistor - Google Patents

Chip resistor

Info

Publication number
JPS5939001A
JPS5939001A JP57149477A JP14947782A JPS5939001A JP S5939001 A JPS5939001 A JP S5939001A JP 57149477 A JP57149477 A JP 57149477A JP 14947782 A JP14947782 A JP 14947782A JP S5939001 A JPS5939001 A JP S5939001A
Authority
JP
Japan
Prior art keywords
chip resistor
resistor
view
recess
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57149477A
Other languages
Japanese (ja)
Inventor
日渡 正文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57149477A priority Critical patent/JPS5939001A/en
Publication of JPS5939001A publication Critical patent/JPS5939001A/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 (al  発明の技術分野 本発明はチップ抵抗器に係り、特にプリント板のプリン
ト配線に容易に半田付りにより接続し得ると共に、低コ
ストにて製作可能な該チップ抵抗器の構造に関する。
DETAILED DESCRIPTION OF THE INVENTION (al) Technical Field of the Invention The present invention relates to a chip resistor, and in particular to a chip resistor that can be easily connected to printed wiring on a printed circuit board by soldering and that can be manufactured at low cost. Concerning the structure of the vessel.

(1))技術の背景 電子機器が益々小型化してゆく趨勢に対応して高密度実
装やプリント板への自動挿入に適する電子部品の開発実
用化が進められている。その−面として従来のディスク
リート抵抗器の一部はデツプ抵抗器に置換されつつある
(1)) Background of the technology In response to the trend of electronic devices becoming smaller and smaller, electronic components suitable for high-density mounting and automatic insertion into printed circuit boards are being developed and put into practical use. On the other hand, some of the conventional discrete resistors are being replaced by dip resistors.

(C1従来技術と問題点 従来のチップ抵抗器の一般的な構造を第1図の斜視図に
示す。セラミック基板lの面上に端子2と抵抗体3が厚
膜プリント法で形成されている。
(C1 Prior Art and Problems The general structure of a conventional chip resistor is shown in the perspective view of Fig. 1. Terminals 2 and resistor 3 are formed on the surface of a ceramic substrate l by a thick film printing method. .

以下の説明の必要上、 その製作方法を第2図の平面図
を参照して簡単に述べる。 厚さ0.63〜0.30m
m程度のセラミック母基板4の表面上にチップ抵抗器の
一定間数分の端子2のパターンを例えば銀−パラジュウ
ム等の導電性利料のインクでスクリーン印刷し2次いで
同様な方法で酸化ルテニュウムを主体とする抵抗体材料
のインクで抵抗体3のパターンを印刷後、焼成炉の中で
加熱焼成する。 しかる後、セラミック母基板4の表面
上に予め形成されているスリット5を利用して切断して
個々のチップ抵抗器を分離完成する。
For the sake of the following explanation, the manufacturing method will be briefly described with reference to the plan view of FIG. Thickness 0.63~0.30m
A pattern of terminals 2 for a certain number of chip resistors is screen printed on the surface of a ceramic motherboard 4 having a diameter of about m with conductive ink such as silver-palladium, and then ruthenium oxide is applied in the same manner. After printing the pattern of the resistor 3 with the ink of the main resistor material, it is heated and fired in a firing furnace. Thereafter, the ceramic motherboard 4 is cut using the slits 5 previously formed on the surface thereof to separate the individual chip resistors.

以上に述べたチップ抵抗器の製作工程の当然の結果とし
て、該チップ抵抗器のセラミック基板lに載せてそのま
まプリン1〜配線と半田付りにより接続することは、前
記のセラミック基板1の側面1aが邪魔して非當に困難
である。
As a natural result of the manufacturing process of the chip resistor described above, it is possible to place the chip resistor on the ceramic substrate l and connect it to the wiring from the printed circuit board 1 by soldering. It's extremely difficult because it gets in the way.

匿産機種においてはプリント板配線とチップ抵抗器の端
子2とを同一平面になるようにチップ抵抗器を沈めて実
装する例もあるがコスト高を免かれない。
In some rare models, the chip resistor is mounted by sinking so that the printed circuit board wiring and the terminal 2 of the chip resistor are on the same plane, but this increases the cost.

従ってチップ抵抗器の側の対策として、第3図の斜視図
に示すように、前記のセラミック基板1の端子2に接し
た側面la上に端子2を延長した形で導電性皮膜2aを
形成することが行われている。
Therefore, as a countermeasure on the chip resistor side, as shown in the perspective view of FIG. 3, a conductive film 2a is formed on the side surface la of the ceramic substrate 1 that is in contact with the terminals 2 so as to extend the terminals 2. things are being done.

しかし該導電性皮膜2aを形成する・時は個々に切り離
されたチップ抵抗器1を取り扱うのであるからその個数
が大となり1作業能率が低くならざるをえない。加えて
、該導電性皮膜2aの形成ば手作業で筆で導電性材料の
インクをセラミック基板1の側面1aに塗るか、一定の
個数の工程中のチップ抵抗器lの側面1aを一平面に揃
えて集積し、導電性材料インクを含ませたスポンジ等に
押し当てて塗布するハツチ処理的な方法が採られておる
が、その作業能率は高いとはいえない。
However, when forming the conductive film 2a, individual chip resistors 1 are handled, so the number of chip resistors 1 is large, and the efficiency of the process is inevitably low. In addition, when forming the conductive film 2a, the ink of the conductive material is applied manually with a brush to the side surface 1a of the ceramic substrate 1, or the side surface 1a of a certain number of chip resistors l being processed is coated in one plane. A hatching method has been adopted in which the conductive material is stacked and pressed against a sponge or the like impregnated with conductive material ink, but the work efficiency cannot be said to be high.

殊に第4図の平面図に概念的にに示すような。In particular, as conceptually shown in the plan view of FIG.

複数個の抵抗体とその端子および必要な一部の配線より
構成される所謂抵抗アレイにおいては1図に示すように
多くの端子を有するので、セラミック基板1の側面1a
に複数の導電性皮膜−28を手作業で形成するには多大
の工数を要する。特に前述したハツチ処理方法を採ろう
とする時には、前述のスポンジに導電性材料のインクを
含ませるのに前記の複数個の端子に対応したパターンを
付与しなりればならなくなり、チップ抵抗器単体の場合
に比べて尚一層複雑な工程を必要とする。
A so-called resistor array consisting of a plurality of resistors, their terminals, and some necessary wiring has many terminals as shown in FIG.
Manually forming a plurality of conductive films 28 requires a large number of man-hours. In particular, when using the hatch processing method described above, it is necessary to apply patterns corresponding to the plurality of terminals in order to impregnate the sponge with the conductive material ink, and it becomes necessary to apply a pattern corresponding to the plurality of terminals, which makes the chip resistor as a single chip resistor. This requires a more complicated process than in the case of conventional methods.

fdl  発明の目的 本発明は前述の点に鑑みなされたもので1チツプ抵抗器
のセラミック基板lの構造を改良して。
fdl OBJECTS OF THE INVENTION The present invention has been made in view of the above-mentioned points, and improves the structure of a ceramic substrate l of a one-chip resistor.

該セラミック基板1の表面に端子2をスクリーン印刷し
て形成する際に同時に前記の導電性皮膜2aを側面1a
に形成しようとするものである。
When forming the terminals 2 on the surface of the ceramic substrate 1 by screen printing, the conductive film 2a is simultaneously applied to the side surface 1a.
It is intended to form a

(e)  発明の構成 上記の発明の目的は、セラミック基板の表面上にスクリ
ーン印刷により形成された抵抗体および端子より構成さ
れたチップ抵抗器であって、該端子に接する前記セラミ
ック基板の辺縁部に該端子の各々に対応して凹所を有し
、かつ該凹所は該端子と接続した導電性皮膜により被覆
されてなることを特徴とするチップ抵抗器により容易に
達成される。
(e) Structure of the Invention The object of the above invention is to provide a chip resistor comprising a resistor and a terminal formed by screen printing on the surface of a ceramic substrate, the edge of the ceramic substrate in contact with the terminal. This can be easily achieved by using a chip resistor characterized in that the chip resistor has a recess corresponding to each of the terminals, and the recess is covered with a conductive film connected to the terminal.

(fl  発明の実施例 以下本発明の実施例につき図面を参照して説明する。第
5図の斜視図は本発明に基づくチップ抵抗器の構造改良
の一実施例を示す。図において。
(fl Embodiments of the Invention) Embodiments of the invention will now be described with reference to the drawings. The perspective view of FIG. 5 shows an embodiment of the structural improvement of a chip resistor based on the invention.

6は端子2に接する側面1aに設りられた凹所であって
、この例では半円形である。該凹所6のセラミック基板
1の測面1bに前述の導電性皮膜2aを形成しである点
が新しい改良点である。その形成力法は次の通りである
Reference numeral 6 denotes a recess provided in the side surface 1a in contact with the terminal 2, and is semicircular in this example. A new improvement is that the above-mentioned conductive film 2a is formed on the measured surface 1b of the ceramic substrate 1 in the recess 6. The forming force method is as follows.

セラミック母基板7には第6図の平面図に示すように、
14子2と抵抗体3をそれぞれのインクを用いてスクリ
ーン印刷法で一定個数分のパターンを印刷しである。こ
の際前述の凹所6は隣接するチップ抵抗器のセラミック
基板Iの凹所6と列をなして孔8を構成している。この
孔群8はセラミノ゛り母基板7の形成時に予め形成され
ているものである。
As shown in the plan view of FIG. 6, the ceramic motherboard 7 includes:
A certain number of patterns are printed on the 14 elements 2 and the resistor 3 by screen printing using respective inks. At this time, the aforementioned recess 6 forms a hole 8 in line with the recess 6 of the ceramic substrate I of the adjacent chip resistor. This hole group 8 is formed in advance when the ceramic motherboard 7 is formed.

端子2のパターンを印刷する工程において、導電性材料
インクは流動性があるので上記の孔8の内側面に垂れ込
んで皮膜を形成するから、その為め特別の工程を要しな
い。更に前述のスクリーン印刷工程中で、第7図の断面
図で概念的に示すように、排気治具9を用いて前記セラ
ミック母基板7の背面を軽くエアポンプで排気して減圧
すれば。
In the process of printing the pattern of the terminal 2, the conductive material ink is fluid and drips onto the inner surface of the hole 8 to form a film, so no special process is required. Furthermore, during the screen printing process described above, as conceptually shown in the cross-sectional view of FIG. 7, the back surface of the ceramic motherboard 7 is lightly evacuated with an air pump using the exhaust jig 9 to reduce the pressure.

導電性材料インクを孔8の内側面に吸引するのは一層容
易になる。
It becomes easier to attract the conductive material ink to the inner surface of the holes 8.

その後の導電性皮膜と抵抗皮膜の焼成工程は従来と同様
である。
The subsequent firing process for the conductive film and the resistive film is the same as the conventional method.

スリット5は従来のように予めセラミック母基板7の表
面に形成されているか、あるいはレーサ゛光線で後から
形、成されてもよいが2図に見るように孔8を横切って
いるから、セラミック基板7をスリット5を利用して個
々のチップ抵抗器1に切断分離しても、前述凹所6の内
側面1bは導電性皮膜に覆われた侭である。
The slit 5 may be formed in advance on the surface of the ceramic motherboard 7 as in the prior art, or may be formed later with a laser beam, but as shown in Figure 2, the slit 5 crosses the hole 8. Even if the chip resistor 7 is cut and separated into individual chip resistors 1 using the slit 5, the inner surface 1b of the recess 6 is still covered with a conductive film.

以上の工程によって本発明に基づく構造のチップ抵抗器
が完成される。
Through the above steps, a chip resistor having a structure based on the present invention is completed.

これまでの説明では、前記の凹所6は半円形。In the explanation so far, the recess 6 is semicircular.

従って孔8は円形であるとしてきたが、この変形例は第
8図の平面図に示すように各種がある。該凹所6の形は
(a1図のように矩形でもfb1図のように三角形でも
、あるいはその他の形でもよいことは自明である。その
形は2個の凹所6を対にして組み合せて出来た孔8が導
電性材料インクの流入を妨げる(例えば細いスリット状
の孔)ものでな4ノればよく1 またセラミック母基板
7に配設された孔群8の寸法が大き過ぎて、該セラミッ
ク母基板7の強度が低く過ぎて取り扱いに不便というこ
とがなければよい。
Therefore, although it has been assumed that the hole 8 is circular, there are various variations as shown in the plan view of FIG. It is obvious that the shape of the recess 6 may be rectangular as shown in Fig. a1, triangular as shown in Fig. fb1, or any other shape. It is sufficient that the holes 8 formed do not obstruct the inflow of the conductive material ink (for example, thin slit-like holes).1 Also, if the dimensions of the hole group 8 arranged in the ceramic motherboard 7 are too large, It is sufficient as long as the strength of the ceramic motherboard 7 is not so low that it is inconvenient to handle.

また前記凹所6の位置は端子2に接続する基板1の側面
1aとしたが、その位置は接続する基板1の一辺の中央
にあっても、第8図のfC1図に示すように片方に偏っ
ていても差支えはない。
Furthermore, the recess 6 is located on the side surface 1a of the board 1 connected to the terminal 2, but even if the recess 6 is located at the center of one side of the board 1 to be connected, it may be located on one side as shown in Fig. fC1 of Fig. 8. It doesn't matter if you are biased.

殊に第4図の平面図に$111念的にに示すような。Especially as shown in the plan view of FIG.

複数個の抵抗体を有する抵抗アレイにおいては。In a resistor array having multiple resistors.

多くの端子を有するが、第9図に示すように本発明の構
造を容易に適用することが出来る大いにその製作工数を
削減することが出来る。
Although it has many terminals, the structure of the present invention can be easily applied as shown in FIG. 9, and the number of manufacturing steps can be greatly reduced.

(gl  発明の効果 以上の説明から明らかなように9本発明に基づく構造の
チップ抵抗器においては、極めて簡単で低源な方法で、
プリント板上のプリン1〜配線に容易に半田付り法で接
続出来る端子構造を形成出来るという効果がある。
(gl) Effects of the Invention As is clear from the above explanation, in the chip resistor having the structure based on the present invention, it is possible to
This has the effect of forming a terminal structure that can be easily connected to the wiring on the printed board by soldering.

殊にこの効果は複数の抵抗体を有する抵抗アレイにおい
て著しい。
This effect is particularly remarkable in a resistor array having a plurality of resistors.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のデツプ抵抗器の構造を示す斜視図、第2
図はパターン印刷をしたセラミック母基板を示す平面図
、第3図はセラミック基板の端子側の側面に導電性皮膜
を形成した従来のチップ抵抗器の構造を示す斜視図、第
4図は従来の抵抗アレイを概念的に示す平面図、第5図
は本発明に基づく改良されたチップ抵抗器の構造を示す
斜視図。 第6図は本発明に基づく構造のチップ抵抗器を製作する
丸めのパターン印刷をしたセラミック母基板を示す平面
図、第7図はセラミック母基板の背抗器の構造の変形の
2,30例を示す概念的な平面図、第9図は本発明に基
づく構造を通用した抵抗アレイを概念的に示す平面図で
ある。 図において、■はセラミック基板、2は端子。 3は抵抗体、4,7はセラミック母基板、5はスリット
 6は凹所、8は孔をそれぞれ示す。 第1図 第5図 第4閣 第7閃
Figure 1 is a perspective view showing the structure of a conventional depth resistor;
The figure is a plan view showing a pattern-printed ceramic motherboard, Figure 3 is a perspective view showing the structure of a conventional chip resistor in which a conductive film is formed on the side surface of the ceramic substrate on the terminal side, and Figure 4 is a conventional chip resistor. FIG. 5 is a plan view conceptually showing a resistor array, and FIG. 5 is a perspective view showing the structure of an improved chip resistor based on the present invention. Fig. 6 is a plan view showing a ceramic motherboard printed with a round pattern for manufacturing a chip resistor having a structure based on the present invention, and Fig. 7 is a 2 to 30 example of variations in the structure of a resistor on a ceramic motherboard. FIG. 9 is a conceptual plan view showing a resistor array using the structure based on the present invention. In the figure, ■ is a ceramic substrate, and 2 is a terminal. 3 is a resistor, 4 and 7 are ceramic motherboards, 5 is a slit, 6 is a recess, and 8 is a hole. Figure 1 Figure 5 Figure 4 Cabinet 7th Flash

Claims (1)

【特許請求の範囲】[Claims] セラミック基板の表面上にスクリーン印刷により形成さ
れた抵抗体および端子より構成されたチップ抵抗器であ
って、該端子に接する前記セラミック基板の辺縁部に該
端子の各々に対応して凹所を有し、かつ該凹所は該端子
と接続した導電性皮膜により被覆されてなることとを特
徴とするチップ抵抗器
A chip resistor comprising a resistor and a terminal formed by screen printing on the surface of a ceramic substrate, wherein a recess is formed in a peripheral portion of the ceramic substrate in contact with the terminal, corresponding to each of the terminals. and the recess is covered with a conductive film connected to the terminal.
JP57149477A 1982-08-27 1982-08-27 Chip resistor Pending JPS5939001A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57149477A JPS5939001A (en) 1982-08-27 1982-08-27 Chip resistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57149477A JPS5939001A (en) 1982-08-27 1982-08-27 Chip resistor

Publications (1)

Publication Number Publication Date
JPS5939001A true JPS5939001A (en) 1984-03-03

Family

ID=15476000

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57149477A Pending JPS5939001A (en) 1982-08-27 1982-08-27 Chip resistor

Country Status (1)

Country Link
JP (1) JPS5939001A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0292905U (en) * 1989-01-10 1990-07-24
JPH02110302U (en) * 1989-02-18 1990-09-04

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0292905U (en) * 1989-01-10 1990-07-24
JPH0650961Y2 (en) * 1989-01-10 1994-12-21 株式会社村田製作所 Multiple chip resistors
JPH02110302U (en) * 1989-02-18 1990-09-04

Similar Documents

Publication Publication Date Title
GB2208044A (en) An improved circuit board
JPS5939001A (en) Chip resistor
JPH06111869A (en) Surface mount terminal
JP3167968B2 (en) Manufacturing method of chip resistor
US5219607A (en) Method of manufacturing printed circuit board
JPS6341003A (en) Manufacture of chip electronic parts
JP2775718B2 (en) Chip resistor and manufacturing method thereof
JPS6262586A (en) Printed circuit board
JPH04346492A (en) Manufacture of hybrid integrated circuit board
JPH0224395B2 (en)
JP2643125B2 (en) Printing method of printed wiring board
JPS5947704A (en) Angular chip resistor and method of producing same
JPS5848910A (en) Microminiature part ceramic substrate and method of producing same
JPH0682571B2 (en) Electronic component manufacturing method
JPS6144453A (en) Manufacture of hybrid ic
JPS62125692A (en) Via filling of green sheet
JPS60186086A (en) Printed circuit board
JPS6151892A (en) Circuit board
JPH0648750B2 (en) Printed circuit board and method of soldering printed circuit board
JPH03250701A (en) Manufacture of chip resistor
JPS58111395A (en) Method of producing hybrid integrated circuit
JPS59165490A (en) Porcelain substrate printed circuit board and method of producing same
JPH03242901A (en) Chip type resistor and manufacture thereof
JPS6027185A (en) Method of producing hybrid integrated circuit board
JPS6149495A (en) Printed board