JPH0292905U - - Google Patents

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Publication number
JPH0292905U
JPH0292905U JP150789U JP150789U JPH0292905U JP H0292905 U JPH0292905 U JP H0292905U JP 150789 U JP150789 U JP 150789U JP 150789 U JP150789 U JP 150789U JP H0292905 U JPH0292905 U JP H0292905U
Authority
JP
Japan
Prior art keywords
terminal electrodes
insulating substrate
chip resistor
wiring pattern
edge side
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP150789U
Other languages
Japanese (ja)
Other versions
JPH0650961Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989001507U priority Critical patent/JPH0650961Y2/en
Publication of JPH0292905U publication Critical patent/JPH0292905U/ja
Application granted granted Critical
Publication of JPH0650961Y2 publication Critical patent/JPH0650961Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Details Of Resistors (AREA)
  • Non-Adjustable Resistors (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の実施例の多連チツプ型抵抗器
の平面図、第２図はその断面側面図、第３図およ
び第４図は本考案に係る多連チツプ型抵抗器を取
り付ける配線基板の配線パターン図、第５図およ
び第６図は本考案の多の実施例の多連チツプ型抵
抗器の平面図である。第７図は従来例の他連チツ
プ型抵抗器の平面図、第８図はその多連チツプ型
抵抗器を取り付ける配線基板の配線パターン図で
ある。 １，１１，１２……多連チツプ型抵抗器、２…
…絶縁基板、３……抵抗膜、４，５……端子電極
、６，７……凹溝、８，９，１０……配線パター
ン、１３……共通電極。 Figure 1 is a plan view of a multiple chip resistor according to an embodiment of the present invention, Figure 2 is a cross-sectional side view thereof, and Figures 3 and 4 are wiring for attaching the multiple chip resistor according to the present invention. The circuit board wiring pattern diagrams, FIGS. 5 and 6, are plan views of multiple chip resistors according to various embodiments of the present invention. FIG. 7 is a plan view of a conventional multi-chip resistor, and FIG. 8 is a wiring pattern diagram of a wiring board to which the multi-chip resistor is attached. 1, 11, 12...multiple chip resistor, 2...
... Insulating substrate, 3 ... Resistive film, 4, 5 ... Terminal electrode, 6, 7 ... Concave groove, 8, 9, 10 ... Wiring pattern, 13 ... Common electrode.

Claims (1)

【実用新案登録請求の範囲】 方形の絶縁基板の上面に複数個の抵抗膜を形成
するとともに、その絶縁基板の対向する両端縁に
抵抗膜と接続された複数個の端子電極をそれぞれ
形成してなる多連チツプ型抵抗器であつて、 その絶縁基板の対向する両端縁の端子電極のピ
ツチをこの多連チツプ型抵抗器を取り付ける配線
基板の配線パターンピツチの２倍かあるいはそれ
に近似した値にするとともに、一方の端縁側の端
子電極と他方の端縁側の端子電極とを互いに配線
パターンピツチかあるいはそれに近似した値だけ
位置をずらせて形成したことを特徴とする多連チ
ツプ型抵抗器。[Claims for Utility Model Registration] A plurality of resistive films are formed on the upper surface of a rectangular insulating substrate, and a plurality of terminal electrodes connected to the resistive films are respectively formed on opposite edges of the insulating substrate. The pitch of the terminal electrodes on opposite edges of the insulating substrate is twice the wiring pattern pitch of the wiring board on which the multi-chip resistor is attached, or a value close to it. A multi-chip resistor characterized in that the terminal electrodes on one edge side and the terminal electrodes on the other edge side are shifted from each other by the wiring pattern pitch or a value close to it.
JP1989001507U 1989-01-10 1989-01-10 Multiple chip resistors Expired - Lifetime JPH0650961Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989001507U JPH0650961Y2 (en) 1989-01-10 1989-01-10 Multiple chip resistors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989001507U JPH0650961Y2 (en) 1989-01-10 1989-01-10 Multiple chip resistors

Publications (2)

Publication Number Publication Date
JPH0292905U true JPH0292905U (en) 1990-07-24
JPH0650961Y2 JPH0650961Y2 (en) 1994-12-21

Family

ID=31201454

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989001507U Expired - Lifetime JPH0650961Y2 (en) 1989-01-10 1989-01-10 Multiple chip resistors

Country Status (1)

Country Link
JP (1) JPH0650961Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0292906U (en) * 1989-01-12 1990-07-24

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52135048A (en) * 1975-12-11 1977-11-11 Toyo Dengu Seisakushiyo Kk Method of making chip resistors
JPS57199228A (en) * 1981-06-02 1982-12-07 Toshiba Corp Wire bonding pad device
JPS5939001A (en) * 1982-08-27 1984-03-03 富士通株式会社 Chip resistor
JPS61186227U (en) * 1985-05-13 1986-11-20

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52135048A (en) * 1975-12-11 1977-11-11 Toyo Dengu Seisakushiyo Kk Method of making chip resistors
JPS57199228A (en) * 1981-06-02 1982-12-07 Toshiba Corp Wire bonding pad device
JPS5939001A (en) * 1982-08-27 1984-03-03 富士通株式会社 Chip resistor
JPS61186227U (en) * 1985-05-13 1986-11-20

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0292906U (en) * 1989-01-12 1990-07-24

Also Published As

Publication number Publication date
JPH0650961Y2 (en) 1994-12-21

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term