JPS5938849A - 演算回路 - Google Patents

演算回路

Info

Publication number
JPS5938849A
JPS5938849A JP57148945A JP14894582A JPS5938849A JP S5938849 A JPS5938849 A JP S5938849A JP 57148945 A JP57148945 A JP 57148945A JP 14894582 A JP14894582 A JP 14894582A JP S5938849 A JPS5938849 A JP S5938849A
Authority
JP
Japan
Prior art keywords
time
register
bit
adder
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57148945A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6259828B2 (enrdf_load_stackoverflow
Inventor
Noboru Kobayashi
登 小林
Isato Yoshida
勇人 吉田
Masuyuki Ikezawa
池沢　斗志
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57148945A priority Critical patent/JPS5938849A/ja
Publication of JPS5938849A publication Critical patent/JPS5938849A/ja
Publication of JPS6259828B2 publication Critical patent/JPS6259828B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
JP57148945A 1982-08-27 1982-08-27 演算回路 Granted JPS5938849A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57148945A JPS5938849A (ja) 1982-08-27 1982-08-27 演算回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57148945A JPS5938849A (ja) 1982-08-27 1982-08-27 演算回路

Publications (2)

Publication Number Publication Date
JPS5938849A true JPS5938849A (ja) 1984-03-02
JPS6259828B2 JPS6259828B2 (enrdf_load_stackoverflow) 1987-12-12

Family

ID=15464166

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57148945A Granted JPS5938849A (ja) 1982-08-27 1982-08-27 演算回路

Country Status (1)

Country Link
JP (1) JPS5938849A (enrdf_load_stackoverflow)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60254373A (ja) * 1984-05-31 1985-12-16 Nippon Precision Saakitsutsu Kk 積和演算装置
JPS62151976A (ja) * 1985-12-25 1987-07-06 Nec Corp 積和演算回路
US5289399A (en) * 1991-12-06 1994-02-22 Sharp Kabushiki Kaisha Multiplier for processing multi-valued data
JPH06110659A (ja) * 1992-06-30 1994-04-22 Nec Corp マイクロコンピュータ

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5622018A (en) * 1979-07-30 1981-03-02 Tokyo Shibaura Electric Co Vacuum breaker

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5622018A (en) * 1979-07-30 1981-03-02 Tokyo Shibaura Electric Co Vacuum breaker

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60254373A (ja) * 1984-05-31 1985-12-16 Nippon Precision Saakitsutsu Kk 積和演算装置
JPS62151976A (ja) * 1985-12-25 1987-07-06 Nec Corp 積和演算回路
US5289399A (en) * 1991-12-06 1994-02-22 Sharp Kabushiki Kaisha Multiplier for processing multi-valued data
JPH06110659A (ja) * 1992-06-30 1994-04-22 Nec Corp マイクロコンピュータ

Also Published As

Publication number Publication date
JPS6259828B2 (enrdf_load_stackoverflow) 1987-12-12

Similar Documents

Publication Publication Date Title
JP3244506B2 (ja) 小型乗算器
JP2002108606A (ja) スティッキービット生成回路及び乗算器
JPS6347874A (ja) 算術演算装置
JPH0612229A (ja) 乗累算回路
JPH0368416B2 (enrdf_load_stackoverflow)
JP2676410B2 (ja) ステイツキ‐ビツト値を予測する回路およびその方法
JPH0477932B2 (enrdf_load_stackoverflow)
JPS60140422A (ja) 演算処理装置
JPH04205026A (ja) 除算回路
JP2597775B2 (ja) 除算方法および除算装置
JPS5938849A (ja) 演算回路
US5377134A (en) Leading constant eliminator for extended precision in pipelined division
JPH10111791A (ja) 除算装置
US4041296A (en) High-speed digital multiply-by-device
JP3137131B2 (ja) 浮動小数点乗算器及び乗算方法
JP2972326B2 (ja) 平方根計算装置
JPH0578049B2 (enrdf_load_stackoverflow)
JP2685645B2 (ja) パイプライン処理装置
JP3517162B2 (ja) 除算・開平演算装置
JPS63254525A (ja) 除算装置
JPS59116852A (ja) 高速除算装置
JP3201097B2 (ja) 乗算器における乗算処方方法
JP2608090B2 (ja) 高基数非回復型除算装置
JPH06301710A (ja) 倍精度積和演算方法および装置
JPS63159930A (ja) 乗算器