JPS5936971A - Buried gate formation of semiconductor device - Google Patents
Buried gate formation of semiconductor deviceInfo
- Publication number
- JPS5936971A JPS5936971A JP14695782A JP14695782A JPS5936971A JP S5936971 A JPS5936971 A JP S5936971A JP 14695782 A JP14695782 A JP 14695782A JP 14695782 A JP14695782 A JP 14695782A JP S5936971 A JPS5936971 A JP S5936971A
- Authority
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- Japan
- Prior art keywords
- gate
- epitaxial growth
- concentration
- layer
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 230000015572 biosynthetic process Effects 0.000 title claims description 5
- 238000000034 method Methods 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000010438 heat treatment Methods 0.000 claims abstract description 15
- 239000013078 crystal Substances 0.000 claims abstract description 8
- 238000009792 diffusion process Methods 0.000 claims description 17
- 238000009826 distribution Methods 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 238000005245 sintering Methods 0.000 claims 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052796 boron Inorganic materials 0.000 abstract description 4
- 230000002708 enhancing effect Effects 0.000 abstract 2
- 238000009933 burial Methods 0.000 abstract 1
- 239000012535 impurity Substances 0.000 description 13
- 238000010586 diagram Methods 0.000 description 5
- 230000007423 decrease Effects 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 241000894006 Bacteria Species 0.000 description 1
- 206010062717 Increased upper airway secretion Diseases 0.000 description 1
- 241000282330 Procyon lotor Species 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005191 phase separation Methods 0.000 description 1
- 208000026435 phlegm Diseases 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 241000894007 species Species 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 210000002700 urine Anatomy 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66416—Static induction transistors [SIT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は靜１１［樽形テイリスタやゲートターンオアサ
イリスタ等の半導体装置、特に埋込みゲートを有する顧
込みゲート方式半導体装置の埋込みゲート形成法に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming a buried gate in a semiconductor device such as a barrel-shaped thyristor or a gate turn-or-thyristor, and in particular, a buried gate type semiconductor device having a buried gate.
埋込みゲート方・大半導体装置においては、埋込みゲー
トを介して電気信号の伝播が行われるためにゲートの抵
抗値が小さい根早いスイッチング速度を得られることが
公知であり、いかにしてゲートの抵抗値を小さくするか
が重要な課題となっている。そして、埋込みゲート方式
半導体装置における埋込みゲートの形成法とし、
１） 拡散法でゲートを形成したのちこの面に対して
エピタキシャル成長を施し埋込みゲートを形成する。Buried gate method: It is well known that in large semiconductor devices, electric signals are propagated through the buried gate, so a fast switching speed with a small gate resistance can be obtained. An important issue is how to reduce this. The method for forming a buried gate in a buried gate type semiconductor device is as follows: 1) After forming a gate by a diffusion method, epitaxial growth is performed on this surface to form a buried gate.
（２） シリコン基板（以下単に基板という）表向に
凹状の切込み溝を設け、この切込み溝内をエピタキシャ
ル成長で埋めてゲートを形成する。その後ゲート面上憂
こエピタキシャル成長を施して埋込みゲートを形成する
。(2) A concave cut groove is provided on the surface of a silicon substrate (hereinafter simply referred to as a substrate), and the inside of the cut groove is filled with epitaxial growth to form a gate. After that, epitaxial growth is performed on the gate surface to form a buried gate.
の２つの方法が主流である。The following two methods are mainstream.
第１図は拡散法を用いて狸込みゲートを形成する概念を
示す半導体装置の縦方向断面説明図であり、ここで具体
的な説明の便宜上基板はＮ形、ゲートはＰ形の態様とす
る。すなわち、第１図（ａ）においてｌは基板、２は酸
化膜、３は酸化膜２に選択的に開かれた窓であり、第１
図（ｂ）にて４は窓３よりＰ形不純物を拡散して形成せ
しめられたゲートである。また第１図（Ｃ）にてゲート
４が形成されたのちにへ？化膜２を除去した状態が示さ
れる。さらに第１図（ｄ）はゲート４を形成した面にエ
ピタキシャル成長法によりｎ形シリコン単結晶層５を形
成した状噛を示している。ここに、Ｃ川ま電流の通路と
なるチャンネル領域である。FIG. 1 is a longitudinal cross-sectional view of a semiconductor device showing the concept of forming a raccoon gate using a diffusion method. Here, for convenience of concrete explanation, the substrate is assumed to be N-type and the gate is assumed to be P-type. . That is, in FIG. 1(a), l is a substrate, 2 is an oxide film, 3 is a window selectively opened in the oxide film 2, and the first
In FIG. 3B, 4 is a gate formed by diffusing P-type impurities through the window 3. Also, after the gate 4 is formed in FIG. 1(C)? A state in which the chemical film 2 has been removed is shown. Further, FIG. 1(d) shows a structure in which an n-type silicon single crystal layer 5 is formed by epitaxial growth on the surface on which the gate 4 is formed. This is the channel region where the C river current passes.
かようにして、ゲート４を拡散法で形成する際にゲート
抵抗を小さくするためには必然的にゲート拡散時Ｐ形不
純物の表面製置を昼める必要が生じる。しかしながらこ
のことはっぎのような弊害をもたらすものになってしま
う。例えば、Ｐゲートの拡散不純物原子としては酸化膜
に対してマスク効果がありかつ萬い表面濃度が得られる
ことからＳ（ロンが広く用いられるところであるが、Ｐ
形不純物のボロンを４１１８１ Ｉｆで拡散したゲート
拡散面へ不純物濃度が１０１４〜１０１０１ｊ（ａｔｏ
／ｃｃ）オーダーと低いル形シリコン単結晶層をエピタ
キシャル成長させるに、その成長時に狭いゲート間隔で
設計される隣合ったＰゲート同志が短絡する現象、いわ
ゆるエピタキシャル成長時のオートドープ現象を発生し
てチャンネル領域の閉鎖を引起こすことになる。かくの
如く、拡散法でゲートを形成する場合ゲート抵抗を犠牲
にしてもチャンネル閉鎖を防止する必要が生じ、このこ
とは埋込みゲートを有する半導体装置の製作にあって好
ましい姿とは百い難いものとなっていた。In order to reduce the gate resistance when forming the gate 4 by the diffusion method as described above, it is inevitably necessary to avoid forming P-type impurities on the surface during gate diffusion. However, this results in a number of negative effects. For example, S (Ron) is widely used as a diffusion impurity atom for the P gate because it has a masking effect on the oxide film and can obtain a high surface concentration.
The impurity concentration is 1014 to 10101j (ato
/cc) When epitaxially growing a low-order L-shaped silicon single crystal layer, a phenomenon in which adjacent P gates designed with a narrow gate interval are shorted together during growth, the so-called autodoping phenomenon during epitaxial growth, occurs, resulting in channel failure. This will cause the area to close. As described above, when forming a gate using the diffusion method, it is necessary to prevent channel closure even at the expense of gate resistance, which is hardly a desirable situation when manufacturing a semiconductor device with a buried gate. It became.
第２図はｇ１図と同様な態様でエピタキシャル成長法に
よるゲート形成を示すもので、６は切込みＮｂ ｚはエ
ピタキシャル成長層である。すなわち、８ｇ２図（ａ）
１こおいて１′は基板、２′は酸化膜であり切込み溝６
は基板１′に切込まれた１行であってこれは酸化膜２′
を利用して湿式または乾式のエツチングをｈ＆すことに
より拌易に形成可能である。また第２図（ｂ）は、第２
図（ａ）に示される酸化膜２′を除去したのちに切込み
溝６を有する面に対してＰ形のエピタキシャル成長を施
すことによってゲート４′を形成し、さらｌこはＰ形エ
ピタキシャル成長層Ｚを形成させた状態を示している。FIG. 2 shows gate formation by epitaxial growth in the same manner as in FIG. That is, 8g2 diagram (a)
1, 1' is the substrate, 2' is the oxide film, and the cut groove 6
is a row cut into the substrate 1', which is the oxide film 2'
It can be easily formed by performing wet or dry etching using . In addition, Fig. 2(b) shows the second
After removing the oxide film 2' shown in Figure (a), a P-type epitaxial growth layer is formed on the surface having the groove 6 to form a gate 4'. It shows the formed state.
またＰ形エピタキシャル成長層Ｚ面をミラー研磨するこ
とにより第２図ｆｃ）の如く示されるものとなる。その
後ゲート４′を形成した面にｎ形シリコン単結晶層５′
を成長させることによって埋込みゲートが完成されて第
２図ｆｄ）のように示される。Further, by mirror polishing the Z plane of the P-type epitaxial growth layer, it becomes as shown in FIG. 2 fc). After that, an n-type silicon single crystal layer 5' is formed on the surface where the gate 4' is formed.
The buried gate is completed by growing the wafer as shown in FIG.
かくの如きエピタキシャル成長法による場合、ゲート４
′内の不純物＆！ｋｌｌ）ｋの分布は一様なためゲート
抵抗を小さくすることができる。例えば、このゲート４
′の不純物濃度と第１図により形成したゲート４の表面
不純物ｍ１度が同じであると仮定するならば、ゲート抵
抗は拡散法に比較してエピタキシャル法が（１１５）〜
（ｌ／ｌｏ） ８度に小さくなる。When using such an epitaxial growth method, the gate 4
Impurities in &! Since the distribution of kll)k is uniform, the gate resistance can be reduced. For example, this gate 4
Assuming that the impurity concentration of ' and the surface impurity m1 degrees of the gate 4 formed according to FIG. 1 are the same, the gate resistance is (115) to
(l/lo) decreases to 8 degrees.
この理由は拡散法では不純物濃度分布が表面から底部へ
指故函数的に減少されるものとなるＩこある。The reason for this is that in the diffusion method, the impurity concentration distribution decreases in a direct function from the surface to the bottom.
したがって、ゲート抵抗を小さくする観点からみればエ
ピタキシャル法による形成法は有利である。Therefore, from the viewpoint of reducing gate resistance, the epitaxial formation method is advantageous.
しかるに、エピタキシャル成長法によるものは、例示の
如く切込まれた部分にエピタキシャル成長を施すため、
基板とゲート界面の結晶性が良好でないためにゲート接
合のリーク電流の増大をきたすなど逆方向特性が悪く、
他方、エピタキシャル成長層を一様な濃度で高めるもの
とすれば埋込みエピタキシャル成長にチャンネルの閉鎖
をまねく等の欠点を有する。それゆえ商業的規模で生産
する上では満足できる方法とは言えなかった。However, in the epitaxial growth method, epitaxial growth is performed on the cut portion as shown in the example, so
Due to poor crystallinity between the substrate and the gate interface, reverse characteristics are poor, such as increased leakage current at the gate junction.
On the other hand, if the epitaxial growth layer is made to have a uniform concentration, it has drawbacks such as channel closure during buried epitaxial growth. Therefore, it could not be said to be a satisfactory method for production on a commercial scale.
本発明は上述したような問題点を解消するためなされた
もので、エピタキシャル成長法およびその熱処理を用い
て特にエピタキシャル成長法を巧み、に効用せしめた新
規なゲート形成法を提供せんとするものである。The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a new gate forming method that makes the epitaxial growth method particularly effective by using the epitaxial growth method and its heat treatment.
第３図は本発明による一例の概念を示すもので、図中第
１図および第２図と同符号のものは同じ構成部分もしく
は同じ機能を有する部分を示す。ここ遥こ、第３図は本
発明の基本技術思想の理解を容易にするため１前述の第
１図およびＭｚ図に類して表し、さらには以下具体的な
数値を用いて詳細説明することにする。FIG. 3 shows the concept of an example according to the present invention, and in the figure, the same reference numerals as in FIGS. 1 and 2 indicate the same components or parts having the same function. To facilitate understanding of the basic technical idea of the present invention, Figure 3 will be expressed in a manner similar to Figure 1 and the Mz diagram described above, and will be explained in detail below using specific numerical values. Make it.
すなわち、第３図（ａ） Ｉ （ｂ）は比抵抗１００（
Ωａｒｔ）。That is, Fig. 3 (a) I (b) has a specific resistance of 100 (
Ωart).
厚ミ２５０（μｍｒＬ）のＮ形の基板１ 、１’、厚み
２（μｍ）を有する酸化膜２．２′、酸化膜２ （Ｃ選
択的Ｊこ開けられた幅２０（μｍ）を有する窓３、窓３
を利用して深さ１５（μフル）の切り込み溝６を形成し
たものを示している。ここで、かような切込みＩ＃６は
第２図説明の如く容易に形成できる。ｊＪ３図（Ｃ）は
切込み溝６をモノシランによるエピタキシャル成長法で
Ｉ）形不純物のボロ／をドープしてｌ０５０″Ｃの温度
で成長させて埋めた状態を示している。したがってエピ
タキシャル成長のｖＡ敵化膜２“面上にもＰ形エピタキ
シャル成長層２′が成長する。ここに、４″はゲートで
ある。しかしながら、かように切込み溝６をＰ形エピタ
キシャル成長層２′で埋めた状態のみでは基板１“とエ
ピタキシャル層との界面における結晶性が悪いため、接
合のリーク′ｖｔ流が増大する原因となる。これを改善
せしめるべく、さらにエピタキシャル成長１時の温度１
０５０ ’０よりも備かに崎箭高い温度で熱処理を施す
主要な過程が設けられる。そして、ＳＡ３図（Ｃ）に示
す如き形成菌にかくの如き熱処理を施すことによってＰ
形エピタキシャル層を不純物源として基板内に浅い拡散
が一様に行われるものとすることができる。つまり、第
３図（ｄ）に示すようｌこ、第３図（Ｃ）のものに対し
て１１００’０のｍｒｉで３時間の熱処理を行うことに
より、約３〜５（μｍ）のＰ膨拡散層７が形成し得る。An N-type substrate 1, 1' with a thickness of 250 (μm), an oxide film 2.2' with a thickness of 2 (μm), and an oxide film 2 (C selectively opened window with a width of 20 (μm)) 3. Window 3
The cut groove 6 having a depth of 15 (μ full) is formed using the following method. Here, such a cut I#6 can be easily formed as explained in FIG. Fig. JJ3 (C) shows the state in which the cut groove 6 is filled by epitaxial growth using monosilane, doped with I) type impurity boro/, grown at a temperature of 1050''C.Therefore, the vA enemy film of epitaxial growth is A P-type epitaxial growth layer 2' is also grown on the 2'' plane. Here, 4" is the gate. However, if the cut groove 6 is filled with the P-type epitaxial growth layer 2' alone, the crystallinity at the interface between the substrate 1" and the epitaxial layer is poor, resulting in junction leakage. 'vt flow increases. In order to improve this, the temperature during epitaxial growth 1
A main step is provided in which the heat treatment is performed at a temperature higher than 0.050'. Then, by applying heat treatment to the forming bacteria as shown in Figure SA3 (C), P.
The epitaxial layer can be used as an impurity source to uniformly shallowly diffuse into the substrate. In other words, as shown in FIG. 3(d), by heat-treating the material in FIG. 3(C) for 3 hours at an MRI of 1100'0, a P expansion of about 3 to 5 (μm) is obtained. A diffusion layer 7 may be formed.
かくの如く、熱処理を施すことは、Ｐ形エピタキシャル
層と基板とが接したＰＮ結合が結晶のよい基板側へ（３
〜５）（μｍ）移動する結果を生み接合特性の改善が行
われるものとなり、しかもＰＮ結合の特性改善のみなら
ず後述する如く埋込みゲート形成時ｌこチャンネルの閉
塞を防止する上で大きな役割を演じるものとなる。そし
てかかる熱処理を施すことは本発明の主眼の１つである
。As described above, performing heat treatment causes the PN bond where the P-type epitaxial layer and the substrate are in contact to move toward the substrate side with good crystallization (3
~5) (μm), which results in an improvement in the junction characteristics.Moreover, as will be described later, it plays a major role in preventing blockage of this channel when forming a buried gate. It becomes something to act out. And performing such heat treatment is one of the main objectives of the present invention.
また、第３図（ｄ）に示すように形成後酸化膜２／／’
とＰ形エピタキシャル成長層２′をミラー研磨で除去し
て第３図（ｅ）の如き形状に仕上げることができ、その
のちこの研磨面にゲートを埋込むため濃度１０”−１０
”（ａｔｏｍｓ／ｃｃ）を有するｎ形シリコｙ 単結晶
層５″が１５〜２０（μＷＬ）の厚みに形成されて第３
図（ｆ）のものとすることができる。In addition, as shown in FIG. 3(d), the oxide film 2//'
The P-type epitaxial growth layer 2' can be removed by mirror polishing to form a shape as shown in FIG.
An n-type silico single crystal layer 5'' having a thickness of 15 to 20 (μWL) is formed to a thickness of 15 to 20 (μWL).
It can be as shown in Figure (f).
かくの如く８ｇ３図に示すものは、特に第３図（Ｃ）に
示されるように基板ｌ“は切込み溝６が設けられた凹状
面内側にＰ形のエピタキシャル層で埋めるようＩこした
ものであって、その２段階のＰ形不純物譲度に差をもた
せて続いて熱処理を廁される大きな特長を有する。すな
わち、これを具体的にさらに記述するならば、凹状底部
よりモノシランにボロンをドープしてボロン濃度が（Ｉ
ＸＩＯＩ９）（ａｔｏｍｓ／ｃｃ）オーダーのＰ形エピ
タキシャル成長層を１０５０’Ｏの温度で１０（μＷＬ
）成長させ、さらに連続してこの上にボロン義度が（Ｉ
ＸＩＯｌｌ） （ａｔｏｍｓ／ｃｃ）オーダーのＰ形エ
ピタキシャル成長層を５〜７（μｍ）成長させる。した
がって、尿さ１５（μ７ＦＬ）に凹状に切込まれた切込
み＃４６部分が埋まることになる。As shown in Fig. 8g3, the substrate l'' is cut so that the inner side of the concave surface in which the cut groove 6 is provided is filled with a P-type epitaxial layer, as shown in Fig. 3(C). It has the great feature that the two stages are made to have different degrees of P-type impurity yield and are then subjected to heat treatment.In other words, to describe this more specifically, monosilane is doped with boron from the concave bottom. Then the boron concentration is (I
XIOI9) (atoms/cc) order P-type epitaxial growth layer is grown at a temperature of 1050'
), and then continuously grow boron on top of this (I
A P-type epitaxial growth layer of (atoms/cc) order is grown to a thickness of 5 to 7 (μm). Therefore, the concave cut #46 portion made in the urine plate 15 (μ7FL) is buried.
その後、Ｐ形エピタキシャル成長温度より僅か１ζ高い
１１００°０の温度で３時間の熱処理を施すことにより
、ＰＮ接合を基板側へ約３〜５（μ桐移動させられたＰ
膨拡散層７を形成し得るものである。これらの関係をさ
らにまた第４図〜第６図を参照して説明する。Thereafter, heat treatment is performed for 3 hours at a temperature of 1100°0, which is only 1ζ higher than the P-type epitaxial growth temperature, to transfer the PN junction to the substrate side by approximately 3 to 5 μm.
The expansion diffusion layer 7 can be formed therein. These relationships will be further explained with reference to FIGS. 4 to 6.
ここに、第４図は第３図（ｃ）に示される（Ｘ−Ｘ）の
縦方向相離における不純物の分布を表わすものであり、
第５図はゲートが埋込まれる前のゲート表面から厚み方
向深さすなわち第３図（ｃ）に示す（ｘ’ −ｘ’ ）
の縦方向における不純物濃度の分布を表すものであり、
第６図は第３図（ｅｌこ示す０７−Ｘ“）のゲート領域
の表面濃度分布を表わすものであり。Here, FIG. 4 represents the distribution of impurities in the vertical phase separation of (X-X) shown in FIG. 3(c),
Figure 5 shows the depth in the thickness direction from the gate surface before the gate is embedded, that is, the depth shown in Figure 3(c) (x' - x')
It represents the distribution of impurity concentration in the vertical direction of
FIG. 6 shows the surface concentration distribution of the gate region of FIG. 3 (el 07-X").
これら第４図〜第６図の縦軸を！り目盛で示している。The vertical axis of these figures 4 to 6! It is shown on a scale.
かかる第４図、第５図および第６図においては、まず第
４図においてゲート４“領域の縦方向濃度分布にてその
底部は（ＩＸＩＯＩす（ａｔｏｍｓ／ｃｃ）オーダーと
なり、その上面側が（ＩＸＩＯＩＱ（ａｔｏｍｓ／ｃｃ
）オーダとなるＨ 、 Ｌの２段階で形成されるものと
なることが示される。つぎに％第５図は第４図に形成さ
れたものに熱処理が加えられて変化した濃度分布が示さ
れる。すなわち、前述の２段階の突変分布を有するＰ形
エピタキシャル成長層部分はその上面側が表面濃度が（
ｌＸｌ０”）（ａｔｏｍ＠／ｃｃ）オーダーを有するＰ
Ｊ−、このＰ層より内側が（ｌＸ１０１す（ａｔｏｍｓ
／ｃｃ）オーダーを有するＰ 層かりなり、これに接し
てゲート領域形成後の熱処理によりＰ＋＋層を拡散源と
して拡散形成されたＰ層の拡散層が連なる如く形成され
る。したがって、Ｐゲート部分においてはその上部より
り、ＨおよびＭすなわら低映度域、高濃度域および中濃
度域を構成する分布を有することが示されるものとなる
。かようにＰゲートの表面露出部の濃度が低くその内部
側に高い濃度をもたせた３つの濃度分布を有するものと
することができる。4, 5, and 6, first of all, in the vertical concentration distribution of the gate 4'' region in FIG. (atoms/cc
) order is shown to be formed in two steps, H and L. Next, % FIG. 5 shows the concentration distribution changed by applying heat treatment to the one formed in FIG. 4. That is, in the P-type epitaxial growth layer portion having the above-mentioned two-stage distribution, the surface concentration on the upper surface side is (
P with order lXl0”)(atom@/cc)
J-, the inside of this P layer is (lX101(atoms
/cc) order, and in contact with this, a series of diffusion layers of the P layer are formed by heat treatment after forming the gate region, using the P++ layer as a diffusion source. Therefore, it can be seen that the P gate portion has a distribution in which H and M constitute a low image intensity area, a high density area, and a medium density area from the top. In this way, the P gate can have three concentration distributions in which the concentration is low in the surface exposed portion and the concentration is high inside.
つぎにまた、第６図においては、エピタキシャル法で形
成したＰゲートの高一度（ｌｘｌｏｌす（ａ ｔｏｎｓ
／ｃｃ）と低濃度ｉｌｌ、 （ｌＸｌ０”）（、ａｔｏ
ｍｓ／ｃｃ）を有する部分にて、その高濃度域の濃度が
（５ＸｌＧ”）（ａｔｏｍｔ／ｃｃ）オーダーに低下さ
れてなるものが示される。これは、Ｍ３図（ｃ）に示す
如く形成してさらに熱処理が施されることにより、凹状
の内側へのＰ形エピタキシャル成長工程においては、最
初に成長する高一度域が拡散源となって基板ｌ“へ拡散
するために濃度低下を生じるものとなるからである。そ
して、エピタキシャル成長より（ＩＸＩＯ”）（ａｔｏ
ｍｓ／ｃｃ）の製置を有していたものを、前述した如き
熱処理したのちには前記の値に減少されたものとなるこ
とが実験によっても得ることができた。かように特に表
面痰度の高いＰ＋十層の表面露出部の濃度を低く抑える
ように工夫したことは本ゲート形成法にあっても注目す
べき点である。Next, in FIG. 6, the height of the P gate formed by the epitaxial method (lxlol(a tons)
/cc) and low concentration ill, (lXl0”)(,ato
ms/cc), the concentration in the high concentration region is reduced to the order of (5 In the P-type epitaxial growth process on the inside of the concave shape, the high-temperature region that grows first becomes a diffusion source and diffuses into the substrate l'', resulting in a decrease in concentration. It is from. Then, from epitaxial growth (IXIO”) (ato
ms/cc), it was found through experiments that the value was reduced to the above-mentioned value after the heat treatment as described above. It is noteworthy that this gate formation method was designed to keep the concentration low in the surface exposed part of the P+ layer, which has a particularly high surface phlegm content.
さらに、前記第５図および第６図に示す如き機能より、
堀込みゲートを有する半導体装置の製造上および特性上
つぎに列挙するような大きなメリットをもたらすものと
なる。Furthermore, from the functions shown in FIGS. 5 and 6,
This brings about the following great advantages in manufacturing and characteristics of a semiconductor device having a trenched gate.
（１） 製造面より
（１−１） 表面に露出したＰゲートの濃度が１０１
′（ａｔｏｍｓ／ｃｃ）オーダーと低いのでゲート埋込
みのために引続いて行われるゲートと反対の導電形を有
して濃度カミ０” 〜１０”（ａｔｏｍｓ／ｃｃ）を有
する３形エピタキシャル層の成長時にオートドープ現象
が発生し離＜、チャンネルの閉鎖を確実に防止でき歩留
りを大巾に高めることが可能になる。(1) From the manufacturing aspect (1-1) The concentration of the P gate exposed on the surface is 101
Growth of a 3-type epitaxial layer having a conductivity type opposite to that of the gate and having a concentration of 0" to 10" (atoms/cc) is subsequently performed for gate embedding. When an autodoping phenomenon occurs, channel closure can be reliably prevented and yields can be greatly increased.
（ｌ−２） Ｐゲートの中心部カミＱｌ” （ａｔｏ
ｍｓ／ｃｃ）オーダーと尚濃度エピタキシャル成長層で
形成されるため、ゲート抵抗が小さくゲート取出し電極
間距離を大巾にのばすことが可能になって、取出し電極
数を低減できさらには作業工程の簡素化をもたらす。(l-2) Center part of P gate Ql” (ato
ms/cc) order and is formed using a high-concentration epitaxially grown layer, the gate resistance is small, and the distance between the gate lead-out electrodes can be widened, reducing the number of lead-out electrodes and simplifying the work process. bring about.
（２）特性面より
（２−１） ゲート接合は拡散法で形成されるために
逆方向特注に浸れリーク電流が小さい。(2) From the characteristics aspect (2-1) Since the gate junction is formed by a diffusion method, leakage current is small because it can be custom-made in the reverse direction.
（２−ｚ ） ゲート抵抗値が小さいので早いスイッ
チング特性が得られる。(2-z) Since the gate resistance value is small, fast switching characteristics can be obtained.
（２−３） 前記取出し電極数を大巾に低減可能なた
め、例えばこの面積増加分だり素子の熱抵抗を減少でき
る。(2-3) Since the number of lead-out electrodes can be greatly reduced, for example, the increased area and the thermal resistance of the element can be reduced.
以上説明した如く本発明によれば、２段階の濃↓
度分布をもたらす如を件エピタキシャル成長とこれに続
く熱処理を巧みに用い、埋込みを行うゲートと反対の導
電形層に接するゲートの一度を低くしゲート中心部の一
度を高くすることにより、檀々の利点を有して効用し得
る産業的価値の篩い埋込みゲートの形成法を提供できる
。As explained above, according to the present invention, by skillfully using epitaxial growth and subsequent heat treatment to produce a two-step concentration distribution, the thickness of the gate in contact with the conductivity type layer opposite to that of the gate to be buried is lowered. By increasing the height of the central part of the gate, it is possible to provide a method of forming a buried gate with a number of advantages and useful industrial value.
なお本説明はＮ形の基板のＰゲート構造のものによった
が、Ｐ形を用いた基板のｎ形グート構造のものであって
も本発明が同一に適用できることは勿論である。Although this explanation has been based on a P-gate structure with an N-type substrate, it goes without saying that the present invention is equally applicable to a P-gate structure with a P-type substrate.
第１図、第２図は従来方式の拡散法、エピタキシャル成
長法を用いて埋込みゲートを形成する概念を示す半導体
装置の縦方向断面説明図、第３図は第１図および第２図
に類して表した本発明による一例の概念を示す縦方向断
面説明図である。第４図、第５図および第６図はＭ３図
の説明のため表した減産分布を示す図である。
ｌｔｌ’ｅｌ“・・・・・シリコン基Ｉ！＜基［）、２
，２’。
ｉ・・・・・・酸化種、４．４’、４“・・・・・・グ
ー）、５．５’。
５“・・・・・・ｎ形シリコン単結晶層、６・・・・・
・切込み溝、７・・・・・・Ｐ形拡散發。
Ｍ 、！’ｆ出＃峨人
東洋環イ、貞ユ諸、；’１ ｉｊ：式会社代表者 土
井 、ヅ
葡１１叉 躬２図
（Ｃ）（り
第 Ｊ 図
［1 and 2 are longitudinal cross-sectional explanatory diagrams of a semiconductor device showing the concept of forming a buried gate using the conventional diffusion method and epitaxial growth method, and FIG. 3 is similar to FIGS. 1 and 2. FIG. 2 is an explanatory longitudinal cross-sectional view showing an example of the concept according to the present invention. FIG. 4, FIG. 5, and FIG. 6 are diagrams showing the production reduction distribution shown for explanation of the M3 diagram. ltl'el"...Silicon group I! < group [), 2
,2'. i...Oxidized species, 4.4', 4"...Goo), 5.5'. 5"...N-type silicon single crystal layer, 6...・・・
- Cut groove, 7...P-type diffusion. M,! 'F appearance #Ajin Toyokan I, Teiyu, ;'1 ij: Shiki company representative Doi, Tsuguo 11, 萬 2 (C) (ri Figure J [
Claims (1)
いて、埋込みゲートを形成するに際してシリコン基板に
凹状の切込み溝を設け、この凹状の切込みＴｊｉｊをエ
ピタキシャル成長法を用いることにより凹状−」込み溝
の縦方向断面が２つの濃度分布を有する如く前記シリコ
ン基板と反対の導電形をもつシリコン単結晶で満たして
ゲートを形成せしめるとともに、続いてエピタキシャル
成長温度よりも僅かに高い温度の熱処理を施したのちこ
の上にシリコン基板と同じ導電形のシリコン結晶を積む
ようにしたことを特徴とする半導体装置の埋込みゲート
形成法。 （２） 前記凹状切込み溝の縦方向断面の底部を、エピ
タキシャル成長法で形成される高濃度層を熱地Ｊにによ
り中濃度の拡散層＋形成し、この拡散層の上にエピタキ
シャル成焼法による高濃度層を設けるとともに、凹状切
込み溝の縦方向断面の上層部をエピタキシャル成長法で
低１１１Ｉｆ層を設けるようにした特許請求の範囲第（
１）項記載の半導体装置の塊込みゲート形成法。[Claims] (In a method for producing an 11m deep gate type semiconductor device, a concave cut groove is provided in a silicon substrate when forming a buried gate, and this concave cut Tjij is formed into a concave shape by using an epitaxial growth method.) The vertical cross section of the groove is filled with a silicon single crystal having a conductivity type opposite to that of the silicon substrate so as to have two concentration distributions to form a gate, and then heat treatment is performed at a temperature slightly higher than the epitaxial growth temperature. A buried gate forming method for a semiconductor device characterized in that a silicon crystal having the same conductivity type as the silicon substrate is then stacked thereon. (2) The bottom of the vertical cross section of the recessed groove is formed by an epitaxial growth method. A medium-concentration diffusion layer + is formed using a hot ground J, and a high concentration layer is formed on this diffusion layer by epitaxial sintering, and the upper layer of the vertical cross section of the concave groove is formed by epitaxial growth. Claim No.
1) A lump gate formation method for a semiconductor device as described in section 1).
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14695782A JPS5936971A (en) | 1982-08-26 | 1982-08-26 | Buried gate formation of semiconductor device |
| US06/511,193 US4528745A (en) | 1982-07-13 | 1983-07-06 | Method for the formation of buried gates of a semiconductor device utilizing etch and refill techniques |
| DE8383304079T DE3381267D1 (en) | 1982-07-13 | 1983-07-13 | METHOD FOR PRODUCING BURNED GATES FOR A SEMICONDUCTOR ARRANGEMENT. |
| EP83304079A EP0099270B1 (en) | 1982-07-13 | 1983-07-13 | Method for the formation of buried gates of a semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14695782A JPS5936971A (en) | 1982-08-26 | 1982-08-26 | Buried gate formation of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5936971A true JPS5936971A (en) | 1984-02-29 |
Family
ID=15419400
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14695782A Pending JPS5936971A (en) | 1982-07-13 | 1982-08-26 | Buried gate formation of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5936971A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60253279A (en) * | 1984-05-29 | 1985-12-13 | Toyota Central Res & Dev Lab Inc | Measuring instrument for strain in semiconductor |
| JPS61130769A (en) * | 1984-11-30 | 1986-06-18 | 株式会社日立製作所 | Chilliness generating method utilizing cryogenic waste gas |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49130185A (en) * | 1973-04-12 | 1974-12-13 | ||
| JPS50117373A (en) * | 1974-02-28 | 1975-09-13 | ||
| JPS5269585A (en) * | 1975-12-09 | 1977-06-09 | Nippon Gakki Seizo Kk | Semiconductor device |
| JPS56157058A (en) * | 1980-04-14 | 1981-12-04 | Thomson Csf | Semiconductor device and method of manufacturing same |
-
1982
- 1982-08-26 JP JP14695782A patent/JPS5936971A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49130185A (en) * | 1973-04-12 | 1974-12-13 | ||
| JPS50117373A (en) * | 1974-02-28 | 1975-09-13 | ||
| JPS5269585A (en) * | 1975-12-09 | 1977-06-09 | Nippon Gakki Seizo Kk | Semiconductor device |
| JPS56157058A (en) * | 1980-04-14 | 1981-12-04 | Thomson Csf | Semiconductor device and method of manufacturing same |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60253279A (en) * | 1984-05-29 | 1985-12-13 | Toyota Central Res & Dev Lab Inc | Measuring instrument for strain in semiconductor |
| JPH0337750B2 (en) * | 1984-05-29 | 1991-06-06 | Toyoda Chuo Kenkyusho Kk | |
| JPS61130769A (en) * | 1984-11-30 | 1986-06-18 | 株式会社日立製作所 | Chilliness generating method utilizing cryogenic waste gas |
| JPH0449029B2 (en) * | 1984-11-30 | 1992-08-10 | Hitachi Ltd |
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