JPS5911684A - Forming method for buried gate of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming a buried gate in a semiconductor device such as a static induction thyristor or a gate turn-off thyristor, and particularly in a buried gate type semiconductor device having a buried gate.

In a buried gate type semiconductor device, it is well known that the lower the gate resistance value, the faster the switching speed can be obtained because electric signals are propagated through the buried gate. ◇The method for forming a buried gate in a buried gate type semiconductor device is to form a gate using a diffusion method and then perform epitaxial growth on this surface to form a buried gate. (2) A concave cut groove is provided on the surface of a silicon substrate (hereinafter simply referred to as a substrate), and the inside of the cut groove is filled with epitaxial growth to form a gate. Thereafter, epitaxial growth is performed on the gate surface to form a buried gate.

The following two methods are mainstream.

FIG. 1 is a longitudinal cross-sectional view of a semiconductor device illustrating the concept of forming a buried gate using a diffusion method. For convenience of detailed explanation, the substrate is assumed to be N-type and the gate is assumed to be P-type. That is, in FIG. 1(a), 1 is a substrate, 2 is an oxide film, 3 is a window selectively opened in the oxide film 2, and in FIG. 1(b), 4 is a P-type impurity from window 3. This is a gate formed by diffusing . Further, FIG. 1C shows a state in which the oxide film 2 is removed after the gate 4 is formed.

Further, FIG. 1(d) shows a state in which a type 1 silicon single crystal layer 5 is formed by epitaxial growth on the surface where the gate 4 is formed. Here, CH is a channel region that serves as a current path.In order to reduce the gate resistance when forming the gate 4 by the diffusion method, it is necessary to increase the surface concentration of P-type impurities during gate diffusion. It becomes necessary to increase the However, this brings about the following disadvantages. For example, boron is widely used as a diffusion impurity atom for the P gate because it has a masking effect on the oxide film and can obtain a high surface concentration. However, a type 1 silicon single crystal layer with a low impurity concentration on the order of 10'4 to 10'' (atoms/cc) is epitaxially grown on the gate diffusion surface where boron, a P type impurity, is diffused at a high concentration, and it is necessary to A phenomenon in which adjacent P gates designed with a large gate spacing are short-circuited, a so-called autodoping phenomenon during epitaxial growth, which causes closure of the channel region. When forming a buried gate, it becomes necessary to prevent channel closure even at the expense of gate resistance, which is not a desirable situation when manufacturing a semiconductor device with a buried gate. In the same way as in Fig. 1, the epitaxial growth method is shown, where 6 is a cut groove and 2 is an epitaxial growth layer.That is, Fig. 2(a) 1ctd, 1' is a substrate, 2' is an oxide film, and 2' is an oxide film. The cut groove 6 is a groove cut into the substrate 1', and this can be easily done by performing wet or dry etching using the oxide film 2'.
This can be formed. Figure 2 (b) is the length of Figure 2 (,)
After removing the oxide film 2' shown in FIG. ing. Further, by mirror-polishing the two surfaces of the P-type epitaxial growth layer, it becomes as shown in FIG. 2(c). then gate 4
A buried gate is completed by growing a type 1 silicon single crystal layer 5' on the surface on which the gate is formed, as shown in FIG. 2(d).
It is shown as follows.

When using such an epitaxial growth method, the gate 4
Since the impurity concentration distribution within ' is uniform, the gate resistance can be reduced. For example, assuming that the impurity concentration of this gate 4' is the same as the surface impurity concentration of the gate 4 formed according to FIG. 1, the gate resistance will be (115) to (115) /10
) The reason for this is that in the diffusion method, the impurity concentration distribution decreases exponentially from the surface to the bottom.

Therefore, from the viewpoint of reducing gate resistance, the epitaxial formation method is advantageous.However,
In the epitaxial growth method, epitaxial growth is performed on the cut portion as shown in the example, so the crystallinity of the interface between the substrate and the gate is not good, resulting in an increase in leakage current at the gate junction, resulting in poor reverse direction characteristics and uniform growth. If the concentration is increased, there are drawbacks such as channel closure during buried epitaxial growth. Therefore, it could not be said to be a satisfactory method for production on a commercial scale.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a new gate formation method in which a diffusion method and an epitaxial growth method are used in combination to make the epitaxial growth method particularly effective. be.

FIG. 3 shows the concept of an example according to the present invention. In the figure, the same reference numerals as in FIGS. In order to facilitate understanding of the basic technical idea of the present invention, the present invention will be expressed in a manner similar to the above-mentioned FIGS. 1 and 2, and will be explained in detail below using specific numerical values.

That is, Fig. 3(a) and (b) have a specific resistance of 100 (
ΩCrn).

N-type substrates 1 and 1' with a thickness of 250 (μm) and a thickness of 2 (a
An oxide film 2.2' having a width of 2.2' m), a window 3 having a width of 20 (μfn) selectively opened in the oxide film 2, and a cut groove 6 having a depth of 15 (μfn) using the window 3 were formed. showing something. Here, such an incision #I6 can be easily formed as explained in FIG. In addition, FIG.
Using the inner surface of the groove 6 shown in b), the surface concentration is (I x 1
0”) (atoms/cc) and depth (3~5)
(, am) shows a state in which a P-type diffusion N7 is formed. In this case, since the inner surface of the cut groove 6' is formed by a diffusion method, the reverse breakdown voltage of the gate junction can be made to have a hard characteristic. Furthermore, as shown in FIG. 3(d), after boron is diffused using a trowel, the oxide film 2'' is removed by the depth of the boron diffusion using photoresist technology to form an oxide film 2'' with a reduced surface area of the oxide film. FIG. 3(e) shows a state in which the cut groove 6' is filled with a P-type epitaxial layer doped with boron as a P-type impurity and the oxide film 21 is grown during epitaxial growth.
A state in which a P-type epitaxial growth layer 2' has grown also on the surface is shown. Here, 4' is a gate. Furthermore, as shown in FIG. 3(1), after the formation, the oxide film 2'# and the P-type epitaxial growth layer 2' are removed by mirror polishing, and the third
It is possible to finish the shape as shown in figure (f), and after that, in order to embed the gate in this polished surface, the concentration is 10'4 to 10''.
(atoms/cc) is formed to a thickness of about 15 to 20 μfF.
It can be the one shown in Figure (g).

As shown in FIG. 3, boron as a P-type impurity is diffused inside the concave surface of the substrate 1' having cut grooves 6', as shown in FIG. 3(d). A P expansion diffusion layer 7 as shown in (f) is formed, and this cut groove 6'
The portion is filled with a P-type epitaxial layer, and has the feature of the present invention that the P-type impurity concentration is different between the two stages. That is, to describe this specifically, the P swelling diffusion layer 7 formed by the diffusion method has a surface concentration of (I x 10") (atoms/cc
), and silicon tetrachloride is doped with boron from the concave bottom having this surface concentration, and the boron concentration is (lXl0'').
A P-type epitaxial growth layer of (atoms/cc) order is grown for 10 (μflt). Continuously, the boron concentration (I x 10I?) (atom
s/cc) order P-type epitaxial growth layer.
Grow ~7 (μff1). Therefore, depth 15 (
The portion of the notch tPI6 cut in a concave shape in μfn) is filled in, and the gate 4# region can be formed as shown in FIG. 3(g) by using a diffusion method and an epitaxial growth method.

These relationships will be further explained with reference to FIGS. 4 to 6. Here, FIG. 4 shows the depth in the thickness direction from the gate surface before the gate is buried, that is, the depth shown in FIG. 3(f) (X-
Figure 5 represents the distribution of impurity concentration in the vertical distance of
It represents the surface concentration distribution of the gate region of
The figures show the time course of changes in the concentration of P-type impurities during epitaxial growth, and the vertical axes of these Figures 4 to 6 are shown on a log scale.

First, in FIG. 4 among FIGS. 4 to 6, the P-type epitaxial growth layer portion having a two-stage concentration distribution as described above has a surface concentration of (I x 10") on the upper surface side.
) P layer with (atoms/cc) order.

The inside of this P layer is (I x 10”) (atom
s/cc), which consists of a P+ layer with order I
Surface concentration (IXIO”) (atoms/cc)
It is connected to the P+ layer formed by diffusion in the P gate region, and as shown above, in the P gate part, the low concentration #L, medium concentration medium range, and 5 shows the concentration distribution of the surface exposed part of the gate 4# region, and the surface concentration (IXIO")
(atoms/cc) diffusion layer 7 formed by the diffusion method and the surface concentration (ixi
o”)(atoms/ce), the surface concentration due to the diffusion method is (5X10”)(a
toms/cc) order. The reason for this is that, as shown in the oxide films 2# and 2M in FIGS. 3(e) and 3(d), the surface area of the oxide film 2'' is equal to the depth of the P diffusion layer 7 of the p++ layer formed of boron. A major factor is the reduction in P.
In the swelling diffusion layer 7, the P type impurity evaporates significantly from the surface of the P++ layer during epitaxial growth at the concave corner A in FIG. 3(d), so the surface concentration decreases rapidly compared to other locations. becomes. This situation is shown, for example, in FIG. Furthermore, what had (I
/cc) could also be obtained experimentally. Particularly noteworthy in the gate forming method of the present invention is that the concentration of the exposed surface portion of the P++ layer, which has such a high surface concentration, is kept low.

In this way, it is possible to have three concentration distributions in which the surface exposed portion of the P gate has a low concentration and the inside thereof has a high concentration.

Furthermore, the function of the concentration distribution as shown in FIGS. 4 and 5 provides the following great advantages in terms of manufacturing and characteristics of a semiconductor device having a buried gate. From the surface (1-1) The concentration of P gate exposed on the surface is 10''
Growth of a type 1 epitaxial layer having a conductivity type opposite to that of the gate and having a concentration of 10'4 to 10'' (atoms/cc) is subsequently performed for gate burying. At times, the autodoping phenomenon is difficult to occur, and channel closure can be reliably prevented and yields can be greatly increased.

(1-2) The center of the P gate is 10” (atoms/
cc) Formed with high-concentration epitaxial growth layers, the gate resistance is low and the distance between the gate lead-out electrodes can be widened, reducing the number of lead-out electrodes and simplifying the work process. 0 (2) From the characteristics aspect (2-1) Since the gate junction is formed by a diffusion method, it has excellent reverse characteristics and a small leakage current.

(2-2) Fast switching characteristics can be obtained because the gate resistance value in contact with the channel, which is a factor in determining dynamic characteristics, is small.

(2-3) Since the number of lead-out electrodes can be greatly reduced, for example, the thermal resistance of the element can be reduced by this increased area.

As explained above, according to the present invention, the diffusion method and the epitaxial growth method are used together to provide a two-stage concentration distribution in the epitaxially grown layer, and the concentration of the gate in contact with the conductivity type layer opposite to that of the gate to be buried is lowered. By increasing the concentration in the central region, it is possible to provide a method of forming a buried gate with various advantages and useful industrial value.

Although this explanation has been based on a P-gate structure with an N-type substrate, it goes without saying that the present invention is equally applicable to a type-1 gate structure with a P-type substrate.

[Brief explanation of drawings]

1 and 2 are longitudinal cross-sectional explanatory diagrams of a semiconductor device showing the concept of forming a buried gate using the conventional diffusion method and epitaxial growth method, and FIG. 3 is similar to FIGS. 1 and 2. FIGS. 4, 5, and 6 are longitudinal cross-sectional explanatory diagrams showing the concept of an example of the present invention as shown in FIG. FIG. 1, 1', 1'...Silicon substrate (substrate)
, 2.2'. 2', 2''...Oxide film, 4.4', 4'...
...Gate, 5゜5', 5"...1 type silicon single crystal layer, 6, 6'... Cut groove, 7...
... P swelling diffusion layer, L ... low concentration area, M ...
...Medium concentration range, H...High concentration range. Patent applicant Toyo Denki Seizo Co., Ltd. Representative Atsushi Doi No. t +W (C) Fig. 2 (C) No. 31 Shisaki 1fl Fig. 5, Sakio Kabuto distance procedure amendment (voluntary) August 1980 Commissioner of the Japan Patent Office on the 2nd, Mr. 1, Indication of the case 1988 Patent Wi No. 120460 4 Name of the invention Method for forming buried gates in semiconductor devices 3 Person making the amendment Relationship to the case Patent applicant postal code 104 Tokyo Yaesu 2-7-2-4, Chuo-ku, Tokyo, “Claims J” and “Detailed Description of the Invention” Column 5, Contents of the Amendment (1) of the specification to be amended. (2) On page 4 of the specification, lines 17 to 18, "indicates that the gate is formed by the epitaxial growth method in the same manner" is changed to "indicates that the gate is formed by the epitaxial growth method in the same manner". ,” is corrected. (3) On page 6, line 9 of the same document, "...increase the concentration uniformly" is corrected to "...on the other hand, increase the concentration in the epitaxially grown layer uniformly." (4) Page 8, lines 4-5 [From boron dope]
is corrected to "doped with boron." Claims (1) In a method for producing a 1m deep gate type semiconductor device, when forming a buried gate, a concave cut groove is provided in a silicon plate, and the concave cut groove is formed using a diffusion epitaxial growth method. By filling the concave groove with a silicon single crystal having a conductivity type opposite to that of the silicon substrate so as to have three concentration distributions such that the vertical cross section thereof increases from the top surface 11Th toward the bottom surface, a gate is formed; A buried gate forming method for a semiconductor device, characterized in that a silicon single crystal having the same conductivity type as a silicon substrate is stacked thereon. (2) By providing a diffusion layer with a high surface concentration at the bottom of the vertical cross section of the recessed groove by a diffusion method, and by forming a medium concentration layer on this diffusion layer by an epitaxial growth method, 1. A buried gate forming method for a semiconductor device according to claim 1, wherein a low 111 degree layer is formed in the upper layer of the vertical cross section by epitaxial growth.

Claims (1)

[Claims] (1) In a method for producing a buried gate type semiconductor device, a concave notch is provided in a silicon substrate when forming a buried gate, and the concave notch is formed by using a diffusion method and an epitaxial growth method. A gate is formed by filling a silicon single crystal with a conductivity type opposite to that of the silicon substrate so that the vertical cross section has three concentration distributions increasing from the top surface side to the bottom surface side, and a silicon substrate and a silicon substrate are formed on the silicon single crystal. A buried gate forming method for a semiconductor device characterized in that silicon single crystals of the same conductivity type are stacked◇(2) A diffusion layer with a high surface concentration is provided at the bottom of the vertical cross section of the recessed groove by a diffusion method. Claim (1) states that a medium concentration layer is formed on the diffusion layer by epitaxial growth, and a low concentration layer is formed in the upper layer of the longitudinal section of the concave groove by epitaxial growth. buried gate formation method for semiconductor devices.