JPS5936823B2 - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS5936823B2
JPS5936823B2 JP51064442A JP6444276A JPS5936823B2 JP S5936823 B2 JPS5936823 B2 JP S5936823B2 JP 51064442 A JP51064442 A JP 51064442A JP 6444276 A JP6444276 A JP 6444276A JP S5936823 B2 JPS5936823 B2 JP S5936823B2
Authority
JP
Japan
Prior art keywords
gold
bonding
copper
layer
interconnect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP51064442A
Other languages
Japanese (ja)
Other versions
JPS527678A (en
Inventor
カーメン・デイー・バーンズ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Semiconductor Corp
Original Assignee
National Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corp filed Critical National Semiconductor Corp
Publication of JPS527678A publication Critical patent/JPS527678A/en
Publication of JPS5936823B2 publication Critical patent/JPS5936823B2/en
Expired legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/86Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
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    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • HELECTRICITY
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    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/79Apparatus for Tape Automated Bonding [TAB]
    • HELECTRICITY
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01015Phosphorus [P]
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    • H01L2924/01027Cobalt [Co]
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    • H01L2924/01029Copper [Cu]
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】 本発明は、一般的に、半導体装置の熱圧縮ギャングボン
ディングに関し、より詳細には、半導体装置を使用回路
に相互接続するための構造体の銅及び金部分間で得られ
る熱圧縮ギャングボンディングに関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates generally to thermal compression gang bonding of semiconductor devices, and more particularly to thermal compression gang bonding between copper and gold portions of structures for interconnecting semiconductor devices to circuits used. related to thermocompression gang bonding.

このような接続構造体は、例えば、半導体装置上のリー
ドフレーム、相互接続リード及びギャングボンディング
バンプを含む。
Such connection structures include, for example, lead frames, interconnect leads, and gang bonding bumps on semiconductor devices.

従来、半導体装置の熱圧縮ギャングボンディングが達成
されていた。
Conventionally, thermocompression gang bonding of semiconductor devices has been accomplished.

これら従来の接合に於いて、りホン状相互接続リードの
銅パターンはニッケル層でメッキされていて、このニッ
ケル層は0.762〜1.524ミクロン(30〜60
マイクロインチ)の範囲内の厚味に金でメッキされてい
る。この金メッキされた相互接続リボン・リードは半導
体装置の表面から支持されてからその上に立上つた金キ
ー丁ングボンデイングバンノにボンディングされた熱圧
縮ギャングである。熱圧縮ギャングボンディングステッ
プ間に、ニッケル層は金対金ボンディングが金メッキ銅
相互接続リードと金ギャングボンディングバンプとの間
に得られるように金の層の下で拡散バリアとして働らく
。同様の金対金熱圧縮ボンディングは金メッキ相互接続
リードと金メッキ・リードフレームとの間で相互接続り
−ドの外側端に於いて得られる。この金対金熱圧縮ボ
ンディング技術に伴なつた問題の1つは、接合を作る際
に使用される金のコストのため高価になることである。
In these conventional connections, the copper pattern of the wire-like interconnect leads is plated with a nickel layer, which is 0.762 to 1.524 microns (30 to 60 microns).
It is plated with gold to a thickness within the range of microinches. The gold-plated interconnect ribbon leads are thermocompression gangs supported from the surface of the semiconductor device and then bonded to gold keying bonding rings that rise above it. During the thermocompression gang bonding step, the nickel layer acts as a diffusion barrier under the gold layer so that a gold-to-gold bond is obtained between the gold plated copper interconnect leads and the gold gang bond bumps. A similar gold-to-gold thermocompression bond is obtained between the gold-plated interconnect leads and the gold-plated lead frame at the outer ends of the interconnect leads. One of the problems with this gold-to-gold thermocompression bonding technique is that it is expensive due to the cost of the gold used in making the bond.

本発明の主たる目的は、リード構造体を半導体装置に熱
圧縮ギャングボンディングするための改良した方法を提
供することにある。
A primary object of the present invention is to provide an improved method for thermocompression gang bonding lead structures to semiconductor devices.

本発明の1つの特徴に於いては、半導体装置を使用回路
に相互接続するための構造体の銅部分は、銅部分の金部
分へのソリツドステート拡散を生じさせかつ冷却時に銅
部分と金部分との間のボンデイングインターフエイスを
得るように他のそのような相互接続構造体の金部分に接
合される熱圧縮ギヤングであり、そのようなインターフ
エイスは銅の金へのソリツドステート拡散からなる。
In one aspect of the invention, the copper portions of the structure for interconnecting the semiconductor device to the circuit used are capable of solid-state diffusion of the copper portions into the gold portions and upon cooling. A thermocompression gang bonded to the gold portion of another such interconnect structure to obtain a bonding interface between the copper and gold portions; Become.

本発明の他の特徴に於いて、銅部分へ熱圧縮ボンデイン
グされた金部分は鋼部材上の金の層からなジ、拡散バリ
ア層は金の層と銅部材との間に配置される。本発明の更
に他の特徴に於いて、リードフレーム構造体上の金の層
は銅の相互接続リードに熱圧縮ボンデイングされる。
In another feature of the invention, the gold portion hot compression bonded to the copper portion comprises a layer of gold on the steel member, and the diffusion barrier layer is disposed between the gold layer and the copper member. In yet another feature of the invention, the gold layer on the leadframe structure is heat compression bonded to the copper interconnect leads.

本発明の今一つの特徴に於いては、銅の相互接続リード
構造体の内側端はギャングボンデイングバンプの金部分
にそれらの間の熱圧縮ボンデイングによつてボンデイン
グされる。
In another feature of the invention, the inner ends of the copper interconnect lead structures are bonded to the gold portions of the gang bonding bumps by thermocompression bonding therebetween.

第1図及び第2図には、相互接続リードをダイに取付け
るための自動的熱圧縮ギヤングボンデイング機に使用さ
れるボンデイングテープ11が示されている。
1 and 2, a bonding tape 11 is shown for use in an automatic thermocompression gang bonding machine for attaching interconnect leads to a die.

テープ11は、そのテープを供給リールから自動的ギヤ
ングボンデイング機を通して進めるためにスプロケツト
駆動ホイールを受けるように両端に沿つて13に於いて
孔があけられた錬銅シート12を含んでいる。金属ホイ
ル14の複数の相互接続リボン・リード・パターンが錬
銅ホイル12に形成され、典型的なパターンが第2図に
示されている。ポリイミド樹脂のフイルム15はパター
ン14の相互接続リード部分16を所望位置に保持する
ために銅のシート12の下側に固着される。矩形の中央
孔18がフイルム15に設けられ、相互接続リボン・リ
ード16の内方端は矩形孔18のリツプの上方に伸びる
。複数の開口19が、接合プロセスの次のステツプでホ
イル12及びフイルム15の切断を容易にするために相
互接続リード・パターン14のそれぞれの周囲に配置さ
れる。第3図及び第4図には、ダイ即ち半導体チツプ2
2の周囲に配置された複数のギヤングボンデイングバン
プ21に相互接続リード16の内方端の熱圧縮ガング接
合のためのダイ結合機の一部が示されている。
Tape 11 includes a wrought copper sheet 12 that is perforated at 13 along each edge to receive a sprocket drive wheel for advancing the tape from a supply reel through an automatic gang bonding machine. A plurality of interconnecting ribbon lead patterns of metal foil 14 are formed in wrought copper foil 12, with a typical pattern shown in FIG. A polyimide resin film 15 is secured to the underside of the copper sheet 12 to hold the interconnect lead portions 16 of the pattern 14 in the desired position. A rectangular central hole 18 is provided in the film 15 with the inner ends of interconnecting ribbon leads 16 extending above the lip of the rectangular hole 18. A plurality of openings 19 are placed around each of the interconnect lead patterns 14 to facilitate cutting of the foil 12 and film 15 in the next step of the bonding process. 3 and 4, a die or semiconductor chip 2 is shown.
A portion of a die bonding machine is shown for thermocompression gang bonding of the inner ends of interconnect leads 16 to a plurality of gang bonding bumps 21 disposed around the periphery of the interconnect leads 16 .

個別のチツプ22は半導体基板部分23を含み、この基
板部分23はそこに成長せしめられたエピタキシヤルn
形導電領域24を有している。
The individual chip 22 includes a semiconductor substrate portion 23 with an epitaxial layer grown thereon.
It has a shaped conductive area 24.

複数のp+導電領域25はn領域24へ拡散されている
。n+導電領域26はnエビタキシヤル層24に拡散さ
れ、そこに電気的接触を作る。n層24の上方表面は二
酸化シリコンのようなパツシベーシヨン層27で覆われ
ている。複数の孔29は領域25及び26のあるものと
整合して二酸化シリコン層27に設けられている.アル
ミニウムからなるような相互接続金属化パターン28が
二酸化シリコン層の上方でかつ孔29を通して設けられ
、n+及びp+形領域に電気的接触を作る。
A plurality of p+ conductive regions 25 are diffused into n region 24. An n+ conductive region 26 is diffused into the n-evitaxial layer 24 to make electrical contact thereto. The upper surface of n-layer 24 is covered with a passivation layer 27, such as silicon dioxide. A plurality of holes 29 are provided in silicon dioxide layer 27 in alignment with some of regions 25 and 26. An interconnect metallization pattern 28, such as made of aluminum, is provided above the silicon dioxide layer and through the hole 29 to make electrical contact to the n+ and p+ type regions.

ある領域に於いて、ギヤングボンデイングバンプ21は
相互接続金属化パターン28上に例えば電気メツキによ
つて配置され、それに電気的接触が作られる。典型例に
於いて、ギャングボンデイングバンプ21は厚さ1〜2
ミルであり、基部に於いて約12平方ミルの横断面を有
する。半導体ダイ22の他の領域に於いて、相互接続メ
タライゼーシヨンパターン28は二酸化シリコンのよう
な第2のバシベーシヨン層31で覆われ″(いる。半導
体ダイ又はチツプ22はワツクス35を介してガラス板
33に接合された高温フイルム34を介してガラス板3
3から支持されている。
In some areas, the gigantic bonding bumps 21 are placed on the interconnect metallization pattern 28, for example by electroplating, and electrical contacts are made thereto. In a typical example, the gang bonding bump 21 has a thickness of 1 to 2
mill and has a cross section of approximately 12 square mils at the base. In other areas of the semiconductor die 22, the interconnect metallization pattern 28 is covered with a second vacillation layer 31, such as silicon dioxide. Glass plate 3 via high temperature film 34 bonded to plate 33
Supported by 3.

このダイはリリース・ワツクス36の層の媒介を介して
フイルム34から支持される。この組立体は、リリース
・ワツクスを通クかつ部分的に高温フイルム34に入る
鋸歯状切り込み37によつて刻み目をつけられる。ダイ
ボンデイング機はボンディングさるべき個個のチツプ2
2を、ギヤングボンデイングのために例えば550℃の
温度まで加熱されるカーボンのようなダイボンデイング
ツール38と整合せしめられる。
The die is supported from film 34 through a layer of release wax 36. This assembly is scored by serrations 37 passing through the release wax and partially into the hot film 34. The die bonding machine separates the individual chips to be bonded 2
2 is aligned with a die bonding tool 38, such as carbon, which is heated to a temperature of, for example, 550° C. for gigantic bonding.

ボンデイングツール38は、ほぼ0.2秒の時間の間バ
ンプ当リ約1009即ち平方ミリメートル当り1.24
×1049(平方ミル当う89)の圧力でガング接合バ
ンプ21の上方端に向けて下向きに相互接続リード16
の内方端を加圧せしめる。典型例に於いて、ボンデイン
グツール38はギヤングボンデイング、ギヤングボンデ
イングバンプを同時に加圧する。各ギヤングボンデイン
グバンプ21は50ノープ(KnOOp)よりも硬い銅
の比較的薄いベース層部分39を含んでいる。
The bonding tool 38 applies approximately 1009 bumps per square millimeter or 1.24 per square millimeter for a period of approximately 0.2 seconds.
interconnection leads 16 downwardly towards the upper end of gang bond bump 21 at a pressure of
Pressurize the inner end of the Typically, the bonding tool 38 applies pressure to the guyang bond and the guyang bonding bump simultaneously. Each gigantic bonding bump 21 includes a relatively thin base layer portion 39 of copper harder than 50 KnOOp.

0.381〜1.52ミクロン(15〜60マイクロイ
ンチ)の如き厚さの金の層41が銅の層39を覆つて設
けられ、ニツケルのような拡散バリア40が金の層41
と下側の銅の層39との間に配置される。
A layer of gold 41, such as 0.381-1.52 microns (15-60 microinches) thick, is provided over the copper layer 39, and a diffusion barrier 40, such as nickel, is provided over the gold layer 41.
and the lower copper layer 39.

典型例に於いて、熱圧縮ボンデイングがなされるべき金
の層41は0.381ミクロン(15マイクロインチ)
以上、好ましくは0.762〜1.52ミクロン(30
〜60マイクロインチ)の範囲の厚昧を有している。ニ
ツケル層は2.54〜17.8ミクロン(0.1〜0.
7ミル)の厚さを有し、バンプ21の全厚昧は7.62
〜50.8ミクロン(0.3〜2.0ミル)の範囲内に
ある。銅の相互接続リード16は、好ましくは、熱圧縮
ボンデイングが非常に薄い酸化防止層42を介して作ら
れることができるように、金、銅、リン酸塩、クローム
酸塩のような非常に薄い酸化防止被覆でおおわれている
。銅対金熱圧縮ボンデイングは、上述したように、銅の
リードを金の層41と熱圧縮ボンデイング係合するよう
加圧せしめることによつて銅の相互接続リード16の内
方端と熱圧縮ギヤングボンデイングバンプ21の金の層
41との間で得られ、このため相互接続リード16から
の銅のソリツドステート拡散が金の層41に於いて得ら
れ、その冷却時に、銅部分及び金部分の間のボンデイン
グインターフエイスが与えられ、このインターフエイス
は金部分への銅のソリツドステート拡散からなる。
In a typical example, the gold layer 41 to be thermocompression bonded is 15 microinches thick.
Above, preferably 0.762 to 1.52 microns (30
~60 microinches). The nickel layer is 2.54-17.8 microns (0.1-0.
7 mil), and the total thickness of bump 21 is 7.62
~50.8 microns (0.3-2.0 mils). The copper interconnect leads 16 are preferably very thin, such as gold, copper, phosphate, chromate, etc. so that thermocompression bonding can be made through the very thin anti-oxidation layer 42. Covered with an antioxidant coating. Copper-to-gold thermocompression bonding involves bonding the inner ends of the copper interconnect leads 16 with the thermocompression bonding by compressing the copper leads into thermocompression bonding engagement with the gold layer 41, as described above. A solid-state diffusion of copper from the interconnect lead 16 is obtained in the gold layer 41 of the young bonding bump 21, so that upon cooling, the copper and gold portions A bonding interface between the two is provided, which consists of a solid state diffusion of copper into the gold portion.

拡散バリア40は、熱圧縮ボンデイングツール38によ
つての金の層の加熱による層39から金の層41への銅
の拡散を防止するように働く。
Diffusion barrier 40 serves to prevent diffusion of copper from layer 39 into gold layer 41 due to heating of the gold layer by thermocompression bonding tool 38 .

また、拡散バリア層40は金の層41を介して銅の層3
9への銅の拡散を防止する。生じた銅対金の熱圧縮ボン
デイングは、銅対銅又は金対金熱圧縮ボンデイングよジ
も強度が大である。加えて、銅対金ボンデイングは、相
互接続リード16が従来技術の金対金ボンデイングと異
な)拡散バリアでメツキされる必要がなくしかも比較的
に薄い金の層でメツキされる必要がないため、従来の金
対金ボンデイングよりも材料及び処理のコストがかなり
少で作られることができる。金の層即ちカツプ41を使
用する代ジに、全バンプ21は金で作られてもよく、熱
圧縮ボンデイングと同じ態様でそれに作られる銅対金熱
圧縮ボンデイングは金の層41に作られる。
Further, the diffusion barrier layer 40 is connected to the copper layer 3 through the gold layer 41.
Prevent copper diffusion into 9. The resulting copper-to-gold thermocompression bond is even stronger than copper-to-copper or gold-to-gold thermocompression bonding. In addition, copper-to-gold bonding does not require interconnect leads 16 to be plated with a diffusion barrier (unlike prior art gold-to-gold bonding) and does not need to be plated with a relatively thin layer of gold. It can be made with significantly less material and processing cost than traditional gold-to-gold bonding. As an alternative to using a gold layer or cup 41, the entire bump 21 may be made of gold, with a copper-to-gold thermocompression bond made to the gold layer 41 in the same manner as a thermocompression bond.

ダイ22が熱圧縮ボンデイングツール38によつてのダ
イの加熱により相互接続リードパターン16の内方端に
ギヤングボンデイングされると、ワツクスはダイを解放
し、それによつて銅のシート即ちテーブ12に移送され
る。
Once the die 22 is gang bonded to the inner edge of the interconnect lead pattern 16 by heating the die with the thermocompression bonding tool 38, the wax releases the die, thereby bonding the die to the copper sheet or table 12. be transported.

ダイを取付けたテープ12は相互接続リード16の外方
部分をリードフレーム部材43(第5,6図)の内方端
に熱圧縮ボンデイングする第2の機械に送られる。リー
ドフレーム43が銅で作られる場合に、それは最初にニ
ツケルのようなバリア層材料44でメツキされ、次いで
金の層45で選択的にメツキされ、これに銅の相互接続
リード16が熱圧縮ボンデイングされる。選択的にメツ
キされた金の層45にボンデイングされる相互接続リー
ド16の上方表面は、好ましくは、熱圧縮接合を可能に
するために充分に薄く金、クローム酸塩又は銅リン酸塩
のような酸化防止被覆で被覆される。熱圧縮ボンデイン
グツール46は相互接続りード16の下側に向けて上向
きに金の層45の下方表面と係合するように相互接続リ
ード16の上方表面を加圧するようにされる。
The die-attached tape 12 is fed to a second machine that heat compression bonds the outer portions of the interconnect leads 16 to the inner ends of the lead frame member 43 (FIGS. 5 and 6). If the lead frame 43 is made of copper, it is first plated with a barrier layer material 44, such as nickel, and then selectively plated with a layer of gold 45, to which the copper interconnect leads 16 are heat compression bonded. be done. The upper surface of the interconnect leads 16 that are bonded to the selectively plated gold layer 45 are preferably thin enough to allow thermocompression bonding, such as gold, chromate or copper phosphate. coated with an anti-oxidant coating. The thermocompression bonding tool 46 is adapted to press the upper surface of the interconnect lead 16 upwardly toward the underside of the interconnect lead 16 into engagement with the lower surface of the gold layer 45 .

典型例に於いて、ボンデイングツール46の温度は45
0℃であり、約1.5秒の間相互接続リード16と係合
して保持される。平方ミリメートル当9の接合圧力は、
典型的には、相互接続リード16の内方端をギヤングボ
ンデイングバンプ21にボンデイングするために使用さ
れる圧力の約3倍、即ち平方ミリメートル当り1.55
〜4,64×104グラム(平方ミル当り10〜30グ
ラム)である。選択的な金メツキの層45は相互接続リ
ード16とインターフエイスする例えば0.145平方
ミリメートル(225平方ミノ(ハ)の面積を有してい
る。銅の相互接続リード16とリードフレーム43上の
金の層45との間で達成される接合強度は通常509よ
りも大であジ、リードフレーム43と相互接続リード1
6の外方端との間で0.145平方ミリメートル(22
5平方ミル)の熱圧縮銅対金インターフエイスポンデイ
ング面積に対して2009程高い。リードフレーム43
が相互接続リード16にボンデイングされた後に、リー
ドフレームは第5図に示されるようにモールドされたエ
ポキシ・パツケージ48に装着される。熱圧縮ボンデイ
ングが相互接続リード16とリードフレーム43の内方
端との間でなされると、銅の相互接続リードパターン1
4は孔あき部19の線に沿つて切断され、それによつて
テーブ11からリードフレーム構造体43にリード取付
けダイ22を移送する。
In a typical example, the temperature of the bonding tool 46 is 45
0° C. and is held in engagement with interconnect lead 16 for approximately 1.5 seconds. The joining pressure per square millimeter is
Typically, about three times the pressure used to bond the inner ends of interconnect leads 16 to gigantic bonding bumps 21, or 1.55 per square millimeter.
~4.64 x 104 grams (10-30 grams per square mil). The selective gold plating layer 45 interfaces with the interconnect leads 16 and has an area of, for example, 0.145 square millimeters (225 square millimeters). The bond strength achieved between the gold layer 45 is typically greater than 509 and the lead frame 43 and the interconnect leads 1
0.145 square millimeters (22
As high as 2009 for a thermally compressed copper-to-gold interface supporting area of 5.5 square mils). Lead frame 43
After bonding to interconnect leads 16, the lead frame is mounted in a molded epoxy package 48 as shown in FIG. When thermocompression bonding is done between the interconnect leads 16 and the inner ends of the lead frame 43, the copper interconnect lead pattern 1
4 is cut along the line of perforation 19, thereby transferring lead attach die 22 from table 11 to leadframe structure 43.

第7図には、本発明の他の実施例が示され、リードフレ
ーム43はニツケル合金42即ちノーバ(KOvar)
から作られる。
Another embodiment of the invention is shown in FIG. 7, in which the lead frame 43 is made of nickel alloy 42 or KOvar.
made from.

このような場合に於いて、金の層45は、好ましくは1
.27〜1.52ミクロン(50〜60マイクロインチ
)の範囲内の厚さに上述したように選択された領域に於
いてリードフレーム43に直接メツキされる。上述のよ
うに、銅の相互接続リード16は、好ましくは、酸化防
止被覆で被覆され、この部材は第6図に関連して記載さ
れたように熱圧縮ボンデイング関係にもたらされ、金の
層45と銅の相互接続リード16との度で熱圧縮ボンデ
イングを得る。リード構造体を半導体装置にギャングボ
ンデイングするための本発明の銅対金熱圧縮ボンデイン
グの使用の長所は、比較的に廉価な銅部材が比較的に高
価な金の層又はバンプと共に使用されうるというところ
にある。
In such a case, the gold layer 45 preferably has a thickness of 1
.. A thickness in the range of 50-60 microinches is plated directly onto the lead frame 43 in selected areas as described above. As mentioned above, the copper interconnect leads 16 are preferably coated with an anti-oxidant coating, and this member is brought into hot compression bonding relationship as described in connection with FIG. 45 and copper interconnect leads 16 to obtain thermal compression bonding. An advantage of using the copper-to-gold thermocompression bonding of the present invention for gang bonding lead structures to semiconductor devices is that relatively inexpensive copper components can be used with relatively expensive gold layers or bumps. There it is.

金部分はバンプ及びリードフレーム43の選択された領
域に制限されてもよく、それによつて金の使用及び部品
のコストを最少にする。また、従来の金対金又は銅対銅
ボンデイングよりもよジ強固のボンデイングが得られる
The gold portions may be confined to the bumps and selected areas of the lead frame 43, thereby minimizing gold usage and component cost. Additionally, a stronger bond can be obtained than conventional gold-to-gold or copper-to-copper bonding.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は自動的ギヤングボンデイング機械によつて半導
体チツプ即ちダイに熱圧縮ボンデイングするための金属
相互接続リード・パターンを有するフイルム形のギヤン
グボンデイングテープの平面図、第2図は2−2線によ
つて表わされた第1図の構造体の一部の拡大平面図、第
3図は相互接続リード構造体を半導体チツプ即ちダイに
ギヤングボンデイングするための熱圧縮ダイボンデイン
グヘツドの拡大断面図、第4図は4−4線によつて表わ
された第3図の構造体の一部の拡大詳細図、第5図はリ
ードフレーム構造体に装着された集積回路ダイ即ちチツ
プを有する集積回路パッケージの断面図、第6図は6−
6線によつて表わされた第5図の構造体の一部の拡大詳
細図、第7図は7ー7線によつて表わされた第6図の構
造体の一部の他の実施例の詳細図である。 図で16は銅の金属相互接続リード、41はギヤングボ
ンデイングバンプ21の金の層を示す。
FIG. 1 is a plan view of a film-shaped gang bonding tape having a metal interconnect lead pattern for thermal compression bonding to a semiconductor chip or die by an automatic gang bonding machine; FIG. An enlarged plan view of a portion of the structure of FIG. 1 represented by lines; FIG. 3 is an enlarged view of a thermocompression die bonding head for gang bonding an interconnect lead structure to a semiconductor chip or die; A cross-sectional view, FIG. 4 is an enlarged detail of a portion of the structure of FIG. 3 represented by line 4--4, and FIG. 5 shows an integrated circuit die or chip mounted on a lead frame structure. FIG. 6 is a cross-sectional view of an integrated circuit package having 6-
6 is an enlarged detail of a portion of the structure of FIG. 5 represented by line 6; FIG. 7 is an enlarged detail of a portion of the structure of FIG. 6 represented by line 7-7; FIG. 3 is a detailed diagram of the embodiment. In the figure, reference numeral 16 indicates the copper metal interconnection lead, and reference numeral 41 indicates the gold layer of the gigantic bonding bump 21.

Claims (1)

【特許請求の範囲】[Claims] 1 半導体チップ手段とリードフレーム手段と金属相互
接続手段とから成り、上記半導体チップ手段はこの半導
体チップ手段の種々の異なつた領域への電気的接続を作
るための相互接続メタライゼーシヨンパターンと上記半
導体チップ手段の表面から持ち上げられかつ上記相互接
続メタライゼーシヨンパターンに基部で接続された複数
のギャングボンディング金属バンプとを有しており、上
記リードフレーム手段は半導体装置を使用する他の回路
装置に電気的に接続するようになつており、上記金属相
互接続手段は銅部分から1つのギャングボンディングバ
ンプの金部分への銅のソリッドステート拡散からなるボ
ンディングインターフェイスを介して少なくとも1つの
上記ギャングボンディングバンプの金部分にボンディン
グされた銅部分を有し、かつ上記半導体チップ手段の上
記ギャングボンデイングバンプを上記リードフレーム手
段に電気的に相互接続するようになつていることを特徴
とする半導体装置。
1 a semiconductor chip means, a lead frame means, and a metal interconnect means, the semiconductor chip means comprising an interconnect metallization pattern and an interconnect metallization pattern for making electrical connections to various different areas of the semiconductor chip means; a plurality of gang bonding metal bumps raised from the surface of the semiconductor chip means and connected at bases to the interconnect metallization pattern, the lead frame means being connected to other circuit devices using the semiconductor device; said metal interconnection means being adapted to electrically connect to at least one said gang bonding bump through a bonding interface comprising a solid state diffusion of copper from a copper portion to a gold portion of said gang bonding bump. A semiconductor device having a copper portion bonded to a gold portion of the semiconductor chip means and electrically interconnecting the gang bonding bumps of the semiconductor chip means to the lead frame means.
JP51064442A 1975-06-02 1976-06-02 semiconductor equipment Expired JPS5936823B2 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/582,620 US4000842A (en) 1975-06-02 1975-06-02 Copper-to-gold thermal compression gang bonding of interconnect leads to semiconductive devices

Publications (2)

Publication Number Publication Date
JPS527678A JPS527678A (en) 1977-01-20
JPS5936823B2 true JPS5936823B2 (en) 1984-09-06

Family

ID=24329846

Family Applications (1)

Application Number Title Priority Date Filing Date
JP51064442A Expired JPS5936823B2 (en) 1975-06-02 1976-06-02 semiconductor equipment

Country Status (7)

Country Link
US (1) US4000842A (en)
JP (1) JPS5936823B2 (en)
BR (1) BR7603301A (en)
CA (1) CA1050668A (en)
DE (1) DE2624313A1 (en)
FR (1) FR2313771A1 (en)
GB (1) GB1530216A (en)

Families Citing this family (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4188438A (en) * 1975-06-02 1980-02-12 National Semiconductor Corporation Antioxidant coating of copper parts for thermal compression gang bonding of semiconductive devices
US4115799A (en) * 1977-01-26 1978-09-19 Westinghouse Electric Corp. Thin film copper transition between aluminum and indium copper films
JPS53123074A (en) * 1977-04-01 1978-10-27 Nec Corp Semiconductor device
FR2402304A1 (en) * 1977-08-31 1979-03-30 Int Computers Ltd ELECTRICAL CONNECTION PROCESS OF AN INTEGRATED CIRCUIT PAD
US4609936A (en) * 1979-09-19 1986-09-02 Motorola, Inc. Semiconductor chip with direct-bonded external leadframe
US4330790A (en) * 1980-03-24 1982-05-18 National Semiconductor Corporation Tape operated semiconductor device packaging
US4331740A (en) * 1980-04-14 1982-05-25 National Semiconductor Corporation Gang bonding interconnect tape process and structure for semiconductor device automatic assembly
US4413404A (en) * 1980-04-14 1983-11-08 National Semiconductor Corporation Process for manufacturing a tear strip planarization ring for gang bonded semiconductor device interconnect tape
JPS57152147A (en) * 1981-03-16 1982-09-20 Matsushita Electric Ind Co Ltd Formation of metal projection on metal lead
US4607779A (en) * 1983-08-11 1986-08-26 National Semiconductor Corporation Non-impact thermocompression gang bonding method
DE3343251A1 (en) * 1983-11-30 1985-06-05 W.C. Heraeus Gmbh, 6450 Hanau SYSTEM CARRIER FOR ELECTRICAL COMPONENTS
US4560826A (en) * 1983-12-29 1985-12-24 Amp Incorporated Hermetically sealed chip carrier
EP0152189A3 (en) * 1984-01-25 1987-12-09 Luc Technologies Limited Bonding electrical conductors and bonded products
IT1213261B (en) * 1984-12-20 1989-12-14 Sgs Thomson Microelectronics SEMICONDUCTOR DEVICE WITH METALLISATION WITH MORE THICKNESS AND PROCEDURE FOR ITS MANUFACTURE.
NL188488C (en) * 1985-05-10 1992-07-01 Asahi Chemical Ind MAGNETO-ELECTRIC TRANSDUCENT.
US4707418A (en) * 1985-06-26 1987-11-17 National Semiconductor Corporation Nickel plated copper tape
US5134460A (en) * 1986-08-11 1992-07-28 International Business Machines Corporation Aluminum bump, reworkable bump, and titanium nitride structure for tab bonding
US4739917A (en) * 1987-01-12 1988-04-26 Ford Motor Company Dual solder process for connecting electrically conducting terminals of electrical components to printed circuit conductors
EP0284820A3 (en) * 1987-03-04 1989-03-08 Canon Kabushiki Kaisha Electrically connecting member, and electric circuit member and electric circuit device with the connecting member
US5046657A (en) * 1988-02-09 1991-09-10 National Semiconductor Corporation Tape automated bonding of bumped tape on bumped die
US5197892A (en) * 1988-05-31 1993-03-30 Canon Kabushiki Kaisha Electric circuit device having an electric connecting member and electric circuit components
US5130275A (en) * 1990-07-02 1992-07-14 Digital Equipment Corp. Post fabrication processing of semiconductor chips
JPH0484449A (en) * 1990-07-27 1992-03-17 Shinko Electric Ind Co Ltd Tab tape
US5508561A (en) * 1993-11-15 1996-04-16 Nec Corporation Apparatus for forming a double-bump structure used for flip-chip mounting
US5591649A (en) * 1995-01-19 1997-01-07 Texas Instruments Incorporated Process of removing a tape automated bonded semiconductor from bonded leads
US5619068A (en) * 1995-04-28 1997-04-08 Lucent Technologies Inc. Externally bondable overmolded package arrangements
US5597470A (en) * 1995-06-18 1997-01-28 Tessera, Inc. Method for making a flexible lead for a microelectronic device
US6020640A (en) * 1996-12-19 2000-02-01 Texas Instruments Incorporated Thick plated interconnect and associated auxillary interconnect
US6060341A (en) * 1998-01-12 2000-05-09 International Business Machines Corporation Method of making an electronic package
DE19916177B4 (en) * 1999-04-10 2006-01-26 Sokymat Gmbh Method for contacting the semiconductor chip and semiconductor chip with wire-shaped connecting pieces
US6940178B2 (en) * 2001-02-27 2005-09-06 Chippac, Inc. Self-coplanarity bumping shape for flip chip
US6768210B2 (en) * 2001-11-01 2004-07-27 Texas Instruments Incorporated Bumpless wafer scale device and board assembly
EP1389802A1 (en) * 2002-08-16 2004-02-18 ABB Schweiz AG Protective layer for an intermediate contact plate in a power semiconductor module
US7176580B1 (en) * 2003-10-24 2007-02-13 Joseph Fjelstad Structures and methods for wire bonding over active, brittle and low K dielectric areas of an IC chip
US7910471B2 (en) * 2004-02-02 2011-03-22 Texas Instruments Incorporated Bumpless wafer scale device and board assembly
US20050230262A1 (en) * 2004-04-20 2005-10-20 Semitool, Inc. Electrochemical methods for the formation of protective features on metallized features
DE102005028951B4 (en) * 2005-06-22 2018-05-30 Infineon Technologies Ag Arrangement for the electrical connection of a semiconductor circuit arrangement with an external contact device
US7439100B2 (en) * 2005-08-18 2008-10-21 Semiconductor Components Industries, L.L.C. Encapsulated chip scale package having flip-chip on lead frame structure and method
US8169081B1 (en) 2007-12-27 2012-05-01 Volterra Semiconductor Corporation Conductive routings in integrated circuits using under bump metallization
US20100133671A1 (en) * 2008-12-02 2010-06-03 Chung Hsing Tzu Flip-chip package structure and the die attach method thereof
TW201114114A (en) * 2009-10-14 2011-04-16 Hon Hai Prec Ind Co Ltd Electrical connector contact and electroplating method thereof
JP6001956B2 (en) * 2012-08-10 2016-10-05 株式会社東芝 Semiconductor device
US11538778B2 (en) * 2020-12-18 2022-12-27 Advanced Semiconductor Engineering, Inc. Semiconductor package including alignment material and method for manufacturing semiconductor package

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3506880A (en) * 1963-06-28 1970-04-14 Ibm Semiconductor device
US3396454A (en) * 1964-01-23 1968-08-13 Allis Chalmers Mfg Co Method of forming ohmic contacts in semiconductor devices
US3787958A (en) * 1965-08-18 1974-01-29 Atomic Energy Commission Thermo-electric modular structure and method of making same
US3689991A (en) * 1968-03-01 1972-09-12 Gen Electric A method of manufacturing a semiconductor device utilizing a flexible carrier
US3480412A (en) * 1968-09-03 1969-11-25 Fairchild Camera Instr Co Method of fabrication of solder reflow interconnections for face down bonding of semiconductor devices
US3713575A (en) * 1971-06-29 1973-01-30 Western Electric Co Bonding apparatus having means for continuous monitoring of the bond
US3760238A (en) * 1972-02-28 1973-09-18 Microsystems Int Ltd Fabrication of beam leads
US3777365A (en) * 1972-03-06 1973-12-11 Honeywell Inf Systems Circuit chips having beam leads attached by film strip process
US3778685A (en) * 1972-03-27 1973-12-11 Nasa Integrated circuit package with lead structure and method of preparing the same
US3838984A (en) * 1973-04-16 1974-10-01 Sperry Rand Corp Flexible carrier and interconnect for uncased ic chips
US4005472A (en) * 1975-05-19 1977-01-25 National Semiconductor Corporation Method for gold plating of metallic layers on semiconductive devices

Also Published As

Publication number Publication date
CA1050668A (en) 1979-03-13
GB1530216A (en) 1978-10-25
FR2313771A1 (en) 1976-12-31
DE2624313A1 (en) 1976-12-23
JPS527678A (en) 1977-01-20
FR2313771B1 (en) 1982-07-02
US4000842A (en) 1977-01-04
BR7603301A (en) 1977-02-15

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