JPS593549U - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS593549U
JPS593549U JP1982098790U JP9879082U JPS593549U JP S593549 U JPS593549 U JP S593549U JP 1982098790 U JP1982098790 U JP 1982098790U JP 9879082 U JP9879082 U JP 9879082U JP S593549 U JPS593549 U JP S593549U
Authority
JP
Japan
Prior art keywords
substrate
semiconductor equipment
semiconductor device
semiconductor chip
grooves
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1982098790U
Other languages
English (en)
Inventor
辻村　剛久
Original Assignee
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to JP1982098790U priority Critical patent/JPS593549U/ja
Priority to EP83303642A priority patent/EP0098114B1/en
Priority to DE8383303642T priority patent/DE3375861D1/de
Priority to IE1529/83A priority patent/IE54714B1/en
Publication of JPS593549U publication Critical patent/JPS593549U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09145—Edge details
    • H05K2201/09181—Notches in edge pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09709—Staggered pads, lands or terminals; Parallel conductors in different planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10727—Leadless chip carrier [LCC], e.g. chip-modules for cards
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図、第２図、第３図は夫々従来の半導体装置の組立
断面図、パッケージ主体部の分解斜視図及びパッケージ
裏面図、第４図、第５図、第６図は、夫々本考案半導体
装置の一実施例の組立断面図、パッケージ主体部の分解
斜視図及びパッケージの裏面図を示す。 図中１・６はセラミック基体、２は半導体チップ、１１
２・１２２・６１２・６２２は側縁、１１３・１２３・
６１３・６２３は溝、１１４・１２４・６１４・６２４
はメタライズ層。

Claims (1)

    【実用新案登録請求の範囲】
  1. 半導体チップを搭載するセラミック基体の側縁にそって
    所定の間隔に配列された複数個の溝を有し、該溝を通じ
    て上記半導体チップの端子を基体裏面に導出してなる半
    導体装置において、前記溝の基体側縁からの深さが交互
    に異なるように形成されてなることを特徴とする半導体
    装置。
JP1982098790U 1982-06-29 1982-06-29 半導体装置 Pending JPS593549U (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP1982098790U JPS593549U (ja) 1982-06-29 1982-06-29 半導体装置
EP83303642A EP0098114B1 (en) 1982-06-29 1983-06-24 Leadless chip carrier semiconductor integrated circuit device
DE8383303642T DE3375861D1 (en) 1982-06-29 1983-06-24 Leadless chip carrier semiconductor integrated circuit device
IE1529/83A IE54714B1 (en) 1982-06-29 1983-06-29 Leadless chip carrier semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1982098790U JPS593549U (ja) 1982-06-29 1982-06-29 半導体装置

Publications (1)

Publication Number Publication Date
JPS593549U true JPS593549U (ja) 1984-01-11

Family

ID=14229157

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1982098790U Pending JPS593549U (ja) 1982-06-29 1982-06-29 半導体装置

Country Status (4)

Country Link
EP (1) EP0098114B1 (ja)
JP (1) JPS593549U (ja)
DE (1) DE3375861D1 (ja)
IE (1) IE54714B1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05211204A (ja) * 1991-11-29 1993-08-20 Akira Kitahara 表面実装電子部品
JPH05275561A (ja) * 1992-03-25 1993-10-22 Nec Corp リードレスチップキャリア基板

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4906802A (en) * 1988-02-18 1990-03-06 Neal Castleman Molded chip carrier
FR2675632B1 (fr) * 1991-04-18 1997-04-30 Texas Instruments France Dispositif de conditionnement de circuits integres
TWM274641U (en) * 2005-04-01 2005-09-01 Lingsen Precision Ind Ltd Packaging carrier for integrated circuit

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2056772B (en) * 1980-08-12 1983-09-01 Amdahl Corp Integrated circuit package and module

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05211204A (ja) * 1991-11-29 1993-08-20 Akira Kitahara 表面実装電子部品
JPH05275561A (ja) * 1992-03-25 1993-10-22 Nec Corp リードレスチップキャリア基板

Also Published As

Publication number Publication date
EP0098114B1 (en) 1988-03-02
EP0098114A2 (en) 1984-01-11
DE3375861D1 (en) 1988-04-07
IE54714B1 (en) 1990-01-17
EP0098114A3 (en) 1985-07-31
IE831529L (en) 1983-12-29

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